HW-SW Interfaces Abstraction and Design for Multi-Processor SoC

Transcription

1 HW-SW Interfaces Abstraction and Desin for Multi-Processor SoC MPSoC 04 Dr. Ahmed Amine JERRAYA TIMA Laboratory 46 Avenue Felix Viallet Grenoble Cedex France Tel: Fax:

2 This is Team Work Staff members: P. Amblard, W. Cesário, X. Chen, F. Rousseau, S. Yoo (left April 04), N. Zerainoh Ph.D. students: Y. Atat, I. Bacivarov, M. Bonaciu, A. Bouchhima, A. Grasset, L. Kriaa, Y. Paviot, A. Sarmento, A. Sasonko, W. Youssef Industrial Ph.D.: A. Blampey, M. Fiandino, F. Hunsiner, (STMicroelectronics) L. Pieralisi Collaborative Ph.D.: Y. Cho, S. Han (Korea) G. Majauskas (Lithuania) I. Petkov (Bularia) Master students and Underraduates: F. Dumitrascu, S. Hadhri, R. Khrouf, K. Popovici, M. Yahia, MPSoC 04-2

3 The SoC Era Challenes SoC: put on a chip what we used to put on one or several boards (ASIC, CPU, Memories, Analo/RF, MEMS, ) Facts: 90% of new ASICs already include a CPU in 130nm. Multimedia, network processors, mobile terminals and ame applications are already multiprocessors. Fundamental chanes: Challenes MPSoC is different from ASIC MPSoC is different from SW MPSoC requires abstract HW-SW interfaces to allow fast interations. Generic MPSoC platform (prorammable, reconfiurable, ) Specific MPSoCs usin standard IP with specific interconnect. MPSoC 04-3

4 Generic SoC Platform vs. Application-Specific MPSoC (MPSoC 03 after dinner discussion) Example: The GSM History/Roadmap 1986 Rack in a van 1990 PCB 1995 Chip set in a hand-set 2002 SoC 2006 SW component on a eneric platform, e.. Nomadic (ST) Same roadmap for ame computers, MP3, STB, NP, DVD MPSoC 04-4

5 Outline 1. HW-SW Interfaces: From Wires to Abstract Interconnect 2. Abstractin HW-SW Interfaces 3. HW-SW Interfaces Desin & Debu: The ROSES Environment 4. MPSoC Desin 4.1. MPEG4 Desin Example 4.2. Results Analysis MPSoC 04-5

6 SoC Platform vs. Embedded Software Application software Platform_API HdS CPU sub-system HW interfaces NoC HW interfaces HW components MPSoC Desin Application SW desin: Real time SW Models Platform model, e.. Sony PlayStation, Nomadic Key Issue: Complexity (GB, ms) Platform_API: Prorammin model to build software Specific to application Hides HW details Hardware dependent SW (HdS) Provided by SoC desiner in case of specific HW Lower SW layers to access HW Specific SoC function (e.. DSP SW code) Key issue: Performances (K&MB, ns) Hardware sub-system CPU sub-systems Specific hardware, Analo, memories, Network-on-Chip HW interfaces: required for application specific HW/SW interfaces MPSoC 04-6

7 Hardware dependent SW Desin & Debu is The Bottelneck Example: SW Debu of an MPEG4 CoDec Data dependent computation C library bu Application SW Bootin is not synchronized amon processors. Lost some interrupts 13 5 Bus % 5 13 Wron interrupt priority levels HAL Context switch does not work correctly. µ-kernel Incorrect FIFO counter value causes deadlock. Parallel Pro. Model Result of compressed video is not correct. Memory Map Abnormal execution of a portion of C code Desin Environment HdS (78%) MPSoC 04-7

8 Outline 1. HW-SW Interfaces: From Wires to Abstract Interconnect 2. Abstractin HW-SW Interfaces 3. HW-SW Interfaces Desin & Debu: The ROSES Environment 4. MPSoC Desin 4.1. MPEG4 Desin Example 4.2. Results Analysis MPSoC 04-8

9 Heteroeneous MPSoC Desin Space Software Prorammin model on an existin platform Concurrency Decomposition Mappin Communication Synchronisation Interconnect NoC Prorammin Model HW Adaptation for application specific communication T 1 T 6 T 2 API HdS CPU 1 CPU 1 sub system sub system HW IF T 3 T 5 T 4 API HdS CPU 2 sub system HW IF Computation subsystem model CPU sub-system for application specific computation SW Adaptation Com. Network MPSoC 04-9

10 Which Parallel Prorammin Model to Use? concurrency decomposition Interconnection mappincommunication synchronization More IMPLICIT Interface Explicit concurrency, decomposition, mappin; Implicit communication, synchronization, Interconnection and Interface SDL, compositional C++ Explicit concurrency, decomposition, mappin, communication, synchronization; Implicit Interconnection and Interface MPI, TLM Messae, thread packae, concurrent C More Explicit Explicit concurrency, decomposition, mappin, communication, synchronization, Interconnection; Implicit Interface TLM Transaction All explicit ISA SW + RTL HW MPSoC 04-10

11 Abstractin HW-SW Interfaces for A Software Sub-system SW API-SW HW-SW Interfaces API-HW NoC SW adaptation (HdS) HAL Abstract CPU SS HW services HW adaptation API-SW = SW prorammin model API-HW = NoC prorammin model Abstract CPU sub-system HAL = HW abstraction layer HW services: local architecture (e.. bus) SW adaptation : implement prorammin model on CPU subsystem HW adaptation: adapt CPU subsystem to NoC MPSoC 04-11

12 The Virtual Component Model Virtual component Component Hardware IP Software IP Functional IP Abstract Interfaces Required Services Provided Services Control Services Synchronization Parameters,. Component 1 Component 2 Abstract Abstract Interface 1 Interface 2 Execution Environment Execution Environment Abstract Platform (e.. NoC, Cosimulation backplane, ) Heteroeneous components thanks to adaptation between different prorammin models. MPSoC 04-12

13 The Virtual Component Model for MPSoC Basic model: a set of hierarchically interconnected virtual modules and an execution environment Virtual Module: Content: Tasks/Instances + communication channels) Abstract interface: set of virtual ports Internal/external ports Virtual SW component Processor Structure and services HW Virtual component IP Internal port (comp. pro. model) Abs. level TLM Protocol rd/wr SW task 1 SW task 2 HW block 1 HW block 2 Execution environment (e.. AMBA bus) External port (NoC pro. Model) RT level Colif: An XML object-oriented database for virtual architectures Components prorammin models NoC prorammin models MPSoC prorammin model is the composition of NoC and components prorammin models. AMBA MPSoC 04-13

14 Outline 1. HW-SW Interfaces: From Wires to Abstract Interconnect 2. Abstractin HW-SW Interfaces 3. HW-SW Interfaces Desin & Debu: The ROSES Environment 4. MPSoC Desin 4.1. MPEG4 Desin Example 4.2. Results Analysis MPSoC 04-14

15 System-level SoC Desin Flow System specification is a virtual architecture: virtual modules usin specific prorammin models connected throuh an execution environment. Architecture implementation: heteroeneous components and sophisticated communication interconnect to adapt different prorammin models. Automatic eneration of application-specific HW/SW interface sub-systems from basic interface components and CPU sub-system models. Virtual Virtual Processor Processor Virtual SW component Processor SW task 1 SW components (Tasks) SW interface sub-system (SW wrapper) CPU sub-system HW interface sub-system (HW wrapper) System Specification SW task 2 Virtual Virtual IP IP HW Virtual component IP HW block 1 Execution environment (e.. AMBA bus) API SW comp. API CPU HW block 2 Basic SW interface component Basic HW interface component API HW comp. API network Communication interconnect (e.. NoC) HW component HW interface sub-system (HW wrapper) MPSoC 04-15

16 Key Technoloy: Composin Interfaces Component services Abstract interface services Execution environment Component interface Required/Provided services Control and Synchronization services Parameters Interface sub-system composition Services matchin User-extensible library Code specialization Component Interface component library MPI channel Data conv. ARM7 boot I/O driver Scheduler Unix IPC Interface sub-system composition Works for HW, SW, and Functional interface sub-systems send send Sched. IT ISR I/O write Execution environment MPSoC 04-16

17 Outline 1. HW-SW Interfaces: From Wires to Abstract Interconnect 2. Abstractin HW-SW Interfaces 3. HW-SW Interfaces Desin & Debu: The ROSES Environment 4. MPSoC Desin 4.1. MPEG4 Desin Example 4.2. Results Analysis MPSoC 04-17

18 MPSoC Desin of a DivX Encoder OpenDivX Open source Mpe4 encoder/decoder - fdct Quant DeQuant Modified to work concurrently on 1/4 th of each frame Movement detection & compensation i fdct Goals Refinement of HW/SW interfaces Multi-level simulation and early validation SW debu before HW platform is ready. MPSoC 04-18

19 DivX Encoder: Overview INPUT : Split comin frame in 4 parts and send it to CPUs CPU_# : Treat comin data and prepare it for compression VLC : Finalize compression and prepare the whole imae COMBINER : prepare for output and adjust compression parameters DMA : Direct access to local memories of processors. Data flow CPU_0 HW IP SW Node CPU_1 Video stream Input CPU_2 VLC Combiner MPEG video CPU_3 DMA MPSoC 04-19

20 DivX Encoder: Overview Major architecture specificities Specific Memory Controller : Switch bank service Specific Interface : Core IT + 2 Synchronization Sinals Point to Point communication scheme bank0 bank0 ARM Core Add Dec bank0 ARM ARM Core bank0 ARM Core Core bank1 bank1 bank1 RAM/ROM Mem Ctrler Mem Ctrler Mem Ctrler Interface Mem Controler bank1 INPUT DMA Combiner MPSoC 04-20

21 CPU Sub-system Architecture With An ARM9 Core MemCtrl MemCtrl SRAM0 SRAM1 SRAM ROM Bus Matrix Address Decoder Memory Controller AHB AMBA Link to DMA MPSoC 04-21

22 Prorammin Model for DivX (DMA) HW component Virtual IP(I/O) HW component Virtual IP(DMA) SW component SW component (P1) SW component (P2) SW component (P3) (P4) HW block 1 HW block 2 HW block 1 HW block 2 Stand by SW encoder task 1 p1 p2 p3 SW SW task task 1 2 SW SW task task 1 2 SW task 2 RT-level channels SystemC transaction level channels Shared-memory Prorammin Model Shared memory: p1.switch_banks() p2.waitevent() DMA control: p3.sendevent() memory_bank_struct *memory_io; // initialize encoder library initialize(5, true, 0, 900); // loop forever while(1) { // waits for data p1.waitevent(); // ets the data address memory_io = (memory_bank_struct*) p2.switch_banks(); // sinals computation startin p3.sendevent(); // calls encodin function divx_compress(&(memory_io->ins), &memory_io->outs, 1); // sinals computation ended p3.sendevent(); wait(); } MPSoC 04-22

23 Prorammin Model for DivX (DMS) HW component Virtual IP(I/O) HW component Virtual IP(DMS) SW component SW component (P1) SW component (P2) SW component (P3) (P4) HW block 1 HW block 2 HW block 1 HW block 2 Stand by SW encoder task 1 p1 p2 SW SW task task 1 2 SW SW task task 1 2 SW task 2 RT-level channels SystemC transaction level channels Messae Passin Prorammin Model Messae passin: DMS control: p1.sram_init(base_address) p2.conn_setup (rmt_id,lch,rch) p2.send (lch,laddress,size) p2.recv (lch,laddress,size) p2.rwrite (lch,laddr,raddr,size) p2.rread (lch,laddr,raddr,size) p2.iwait (lch) p2.pwait (lch) memory_bank_struct *memory_io; // initialize messae structure p1.sram_init(&mes); // loop forever while(1) { // input data p2.recv( ); p2.pwait( ); // ets the data while (mes!= end_data) { memory_io[mes.addr] = mes.data; } // calls encodin function divx_compress(&(memory_io->ins), &memory_io->outs, 1); // sends output data for ( ) { p2.send( ); p2.pwait( ); } wait(); } MPSoC 04-23

24 The ROSES Environment MPSoC 04-24

25 Outline 1. HW-SW Interfaces: From Wires to Abstract Interconnect 2. Abstractin HW-SW Interfaces 3. HW-SW Interfaces Desin & Debu: The ROSES Environment 4. MPSoC Desin 4.1. MPEG4 Desin Example 4.2. Results Analysis MPSoC 04-25

26 Key Results Early and multi-level simulation allows for: Architecture exploration Debu cost reduction Debu software before hardware is ready Mitiate hardware prototypin step Automatic eneration of HW and SW adaptation layers: a drastic improvement of desin productivity. MPSoC 04-26

27 Multi-level Simulation Speed-up and Accuracy SW simulation at prorammin model level Application SW Abstract SW Interface Model RTL (or TLM) Speed-up ~500 (>>) Accuracy 75% (<<) HW Native SW simulation with abstract CPU sub-system model (HAL) Application SW OS HAL Model HW RTL ~100 85% HW/SW co-simulation with ISS ISS 1 100% HW RTL MPSoC 04-27

28 Architecture Exploration for QCIF Resolution, 25 frames/s QCIF RESOLUTION, 25 frames/s MPSoC 04-28

29 Solution 1: QCIF usin ARM7 (60MHz) Processors Frame clock cycles Processor 2 Processors 4 Processors 8 Processors 12 Processors 16 Processors 32 Processors REAL TIME MPSoC 04-29

30 Solution 2: QCIF Usin ARM9SE46-4kI$,4kD$ (60MHz) Processors Frame clock cycles Processor 2 Processors 4 Processors 8 Processors 16 Processors 32 Processors REAL TIME MPSoC 04-30

31 Architecture Exploration for CIF Resolution, 25 frames/s MPSoC 04-31

32 Performance Results: CIF Usin ARM7 (60MHz) Processors (+3 for VLCs) Frame clock cycles Processor 2 Processors 4 Processors 8 Processors 12 Processors 16 Processors 20 Processors 32 Processors REAL TIME 0 MPSoC 04-32

33 Performance Results: CIF Usin ARM9SE46-4kI$,4kD$ (60MHz) Processors (+2 for VLC) Frame clock cycles Processor 2 Processors 4 Processors 8 Processors 16 Processors 32 Processors REAL TIME MPSoC 04-33

34 Early Simulation to Reduce HW/SW Interface Debu Cycle Validate HdS at several levels of abstraction: Applied to 83 % case study = = 17 % % HdS bus 0 % 13 % 40 % 30% % Ti T1 App. SW Ti T1 App. SW Ti T1 App. SW Ti T1 App. SW Ti T1 App. SW Ti T1 App. SW API Parallel Pro. Model API API PPM API PPM API PPM API PPM µ-kernel Hardware Abstraction Layer CPU Core CPU interface Network adapt. MPICH MPI SC Simulation Model µ-kernel + HAL + CPU µ-kernel Simulation Model (HAL + CPU) Instruction Set Simulator (ISS) µ-kernel HAL Simulation Model CPU ISS µ-kernel HAL On HW prototype MPSoC 04-34

35 MPSoC Desin Issues Generic MPSoC platform vs. Application specific MPSoC HdS vs. Application specific HW-SW interfaces SW prorammin model vs. a composition of heteroeneous prorammin models Application specific HW-SW interfaces Computation specific CPU sub-system Interconnect SW adaptation: HdS HW adaptation Early validation to reduce desin and debu cost. MPSoC 04-35

36 Thank You MPSoC 04-36