Beyond IC Design: Challenges for the Next Generation of EDA Software

Transcription

1 Beyond IC Design: Challenges for the Next Generation of EDA Software Hermann Eul Member of the Management Board Infineon Technologies AG edaforum07 December 6th, 2007

2 Outline! Introduction: Communication Market! Engineering Challenges! Opportunities and Challenges for EDA " System Level Design " System on Chip: RF and Digital Baseband in CMOS " Chip Package Co-Design! Summary and Conclusions Page 2

3 Outline! Introduction: Communication Market! Engineering Challenges! Opportunities and Challenges for EDA " System Level Design " System on Chip: RF and Digital Baseband in CMOS " Chip Package Co-Design! Summary and Conclusions Page 3

4 Infineon Addressing 3 Big Questions of Modern Society Energy Efficiency, Communications and Security Automotive Industrial Electronics Chip Card & Security Mobile Phone Platforms RF Solutions Broadband Access Analog/Mixed Signal RF Power Embedded Control Page 4

5 Market Share of Communication Semiconductors Semiconductor Market Development Total market $351bn $260bn 6% CAGR 8% $93bn Communication $64bn Data processing Consumer Industrial Automotive Source: Gartner, Feb Page 5

6 Mobile Phone Market Mobile Phone Market by Standard (mio Units) Current Situation GSM GPRS EDGE UMTS/WCDMA UMTS/HSDPA UMTS/HSUPA CDMA 2000 CDMA 1XEVDV/DO Other! GPRS market keeps on shrinking will be more and more replaced by EDGE and GSM ULC segment! EDGE market will be one dominate segment! HSDPA will become the second dominate segment! WCDMA for 3G entry segment will have significant volume! HSUPA significant market share in 2010! Multimedia feature requirements are increasing strongly Sources: Strategy Analytics, August 2006; Infineon Page 6

7 Mobile Device is Becoming an All-In-One Solution 3D Graphics A-GPS DVD Sensors Security DSC Camera Video conferencing Digital TV Audio UWB WiMAX Camcorder WLAN Bluetooth Gaming HSxPA Music/MP3 Page 7

8 The Wireless Evolution WLANs 54Mbps WLANs 500Mbps Mobile WLANs Bits per second NOMADIC MAN / LAN / PAN Bluetooth 2G GSM 802.llb Digital Voice 802.lln 802.llag 3G UMTS HSDPA Multimedia Messaging, Medium-Speed, Packet Data UWB LTE CELLULAR 4G Broadband Multimedia, Broadcast Video, High-Speed Packet Data Page 8

9 Convergence of Multimedia Content over Home and Mobile Networks Mobile World to Seamless Connectivity Home World Content Provider Broadband Service Provider Cellular Service Provider Page 9

10 Market Boost for Ultra Low End Phones in Emerging Countries Market Forecast Wireless Handset Shipments by Value Shipments (Millions) Smartphone Enhanced Phone Low-End Ultra-Low-End Source: ABI research, Q Page 10

11 Outline! Introduction: Communication Market! Engineering Challenges! Opportunities and Challenges for EDA " System Level Design " System on Chip: RF and Digital Baseband in CMOS " Chip Package Co-Design! Summary and Conclusions Page 11

12 Phones based on Infineon System Platforms >100 Models in the Market Page 12

13 Ultra Low End Phones: Engineering Challenges Integration to Reduce System BoM! ULC2 dual-band Phone Module (25 x 17 x 2.5 mm)! Module mounted on low-cost 2- layer carrier PCB! PCB cost savings! Pre-tested and pre-calibrated! Fast time-to-market 2005 P ULC ULC2 ULC2 Features! Modem footprint: 4cm²! Modem components: <50! 4-layer PCB! Color display support! Polyphonic tones & TrueTones! Local languages, text messaging and speakerphone Page 13

14 Ultra Low End Phones: Engineering Challenges SoC Integration of BB, RF and PMU and more.. E-GOLDvoice TM Single-Chip GSM Mobile Phone Solution Mixed signal Audio PMU RF µc + DSP RAM RAM Page 14

15 Feature Phones: Engineering Challenges System Complexity in an All-in-One Device 5 pxl Power Controller Vibrator Charger Backlight Battery * # Display b&w or colour SIM Card MMC/SD Card FastIrDA Driver and Diodes Direct USIM Interface FastIrDA Interface Application Subsystem NOR Flash DDR SDRA NAND Flash Modem Subsystem GSM/EDGE/ WCDMA/HSDPA DVB-H Bluetooth RF Transceiver A-GPS WLAN UWB WiMax Nearfield Page 15

16 Feature Phones: Engineering Challenges PCB Space Limited System Verification Explodes 3G Co-Processor 3G TRX UMTS PA/Band 2 WLAN PMU GSM/EDGE TRX FEM UWB GSM BB Processor GSM/EDGE PA UMTS PA/Band 1 GPS NOR-Flash UMTS PA/Band 5 NAND-Flash DVB SD-RAM FM-Radio Bluetooth Modem WiMax Page 16

17 Outline! Introduction: Communication Market! Engineering Challenges! Opportunities and Challenges for EDA " System Level Design " System on Chip: RF and Digital Baseband in CMOS " Chip Package Co-Design! Summary and Conclusions Page 17

18 System Development, Integration & Verification Key Challenges for Semiconductor IDM System Design Hardware Development Software & Firmware Development System Integration & Verification Page 18

19 Opportunities and Challenges for EDA System Design System Architecture Exploration and Optimization Algorithm Design Transaction Level Models (TLM) Virtual Prototyping (VP) Software & Firmware Development Analog/RF Design Hardware Development Digital Design Package/PCB Design System Integration & Verification Page 19

20 Outline! Introduction: Communication Market! Engineering Challenges! Opportunities and Challenges for EDA " System Level Design " System on Chip: RF and Digital Baseband in CMOS " Chip Package Co-Design! Summary and Conclusions Page 20

21 Standardization is a Challenge for Transaction Level Modeling Algorithm Design System Design Architecture Exploration and Optimization TLM VP TLM-IP TLM-IP TLM-IP TLM-IP Software & Firmware Development Algorithm Algorithm Dataflow Dataflow Simulation Simulation Virtual Virtual Prototype Prototype Transaction Transaction Level Level Modeling Modeling Export VP SW/FW SW/FW Simulation Simulation based based on on VP VP Hardware Development System Verification IP System Level Tests System Integration & Verification Platform Platform Debugging Debugging Page 22

22 Improvement TLM Standards v1.0 required Modeling of IP in Standard TLM Algorithm Design System Design Architecture Exploration and Optimization TLM VP TLM-IP TLM-IP TLM-IP TLM-IP Software & Firmware Development Algorithm Algorithm Dataflow Dataflow Simulation Simulation Virtual Virtual Prototype Prototype Transaction Transaction Level Level Modeling Modeling Export VP SW/FW SW/FW Simulation Simulation based based on on VP VP Hardware Development Improve TLM Standard to reduce adaptation efforts TLM Modeling of IP as Business Opportunity for IP Providers System Integration & Verification Page 23

23 Redundant Models increase Effort in a Heterogeneous Modeling Environment Algorithm Design System Design Architecture Exploration and Optimization Transaction Level Modeling Virtual Prototype Software & Firmware Algorithm Algorithm Dataflow Dataflow Simulation Simulation Integrate SystemC Transaction Transaction Level Level Model Model [SystemC] [SystemC] Functional Verification Testbench Testbench [ [ e/sv] e/sv] Reference Reference Model Model [ [ e/sv e/sv ] ] Checking Checking Coverage Coverage Hardware Development RTL RTL Model Model [ [ VHDL/ VHDL/ Verilog Verilog ] ] Workaround: Verify TLM against RTL using reference model in e/sv Page 25

24 Provide Interfaces for different Modeling Languages Algorithm Design System Design Architecture Exploration and Optimization Transaction Level Modeling Virtual Prototype Software & Firmware Algorithm Algorithm Dataflow Dataflow Simulation Simulation Integrate SystemC Transaction Transaction Level Level Model Model [SystemC] [SystemC] Functional Verification Testbench Testbench [ [ e/sv] e/sv] TLM TLM Model Model [ [ e/sv e/sv ] ] Checking Checking Coverage Coverage Hardware Development RTL RTL Model Model [ [ VHDL/ VHDL/ Verilog Verilog ] ] Preferred Solution: Use TLM model as reference for RTL verification Page 26

25 Data Consistency is a Challenge in System - Hardware - Software Co-Design Algorithm Design System Design Architecture Exploration and Optimization TLM VP Registers [ SystemC ] Interfaces [ SystemC ] Software & Firmware Development Interfaces [ C / C++ ] Hardware Development Registers [ VHDL / Verilog ] Interfaces [ VHDL / Verilog ] Registers [ C / C++ ] Registers [ e/sv ] Interfaces [ e/sv] System Integration & Verification Page 27

26 Consistency by Single Source of Design Data Single Source for Specification and Implementation Algorithm Design System Design Architecture Exploration and Optimization TLM VP Generated SystemC Software & Firmware Development Registers [ XML ] Interfaces [ XML ] Hardware Development Generated VHDL / Verilog Generated e/sv Generated C / C++ Preferred Solution: Single Source and Code Generators System Integration & Verification Page 28

27 Outline! Introduction: Communication Market! Engineering Challenges! Opportunities and Challenges for EDA " System Level Design " System on Chip: RF and Digital Baseband in CMOS " Chip Package Co-Design! Summary and Conclusions Page 29

28 Next Generation of RF Products Cover Frequency Band up to 77 GHz Highly selective filters for many bands Strong demand to replace external filters "Frontend challenge" Flexible Reconfigurable High Performance Radio Multiple Radios on One Chip MIMO Systems "Multi-mode challenge" GSM / UMTS CDMA2000 in CMOS Electromagnetic Design on Chip Power-Amplifier challenge PA DECT Single Chip including 27dBm PA Page 30

29 Today s Analog RFIC Architecture LPF ADC BPF LNA 0 90 :2 :4 PLL DFE+DigIO DSP LPF ADC RFIC (low digital content) BBIC " Analog channel selection " Analog IQ interface " Technology for the BB-IC needs to have an analog option Page 31

30 Next generation: ADC, DFE, Adjustment and Digital IQ Interface integrated in 1 SoC ADC LPF BPF LNA 0 90 :2 :4 PLL Adjust DFE+DigIO DSP Adjust ADC LPF RFIC (strongly increased digital content) " Channel selection moved to the digital domain " Increased ADC requirements " RF impairment correction in the digital domain BBIC SoC Page 32

31 Challenges for RF Design Environment System Design Hardware Development New Methodologies for RF SoC Design and Simulation Strongly increased digital contents in RF Very high analog complexity Software & Firmware Development We need the help of the EDA Industry for Integrated Development Solutions Functional Verification Performance Verification System Integration & Verification Page 33

32 Today's RF / Digital Design System System Design Hardware Development Analog/RF Design Functional spice verilog-a vhdl mixed signal Performance extracted netlist resimulation DB(A) Development schematic layout extraction verification Transformation Development synthesis place&route extraction verification Digital Design DB(D) Functional verilog vhdl Performance SDF Back-annotation STA $ RF and Digital circuit design mainly isolated $ Separate databases, data management and constraint systems $ Dedicated transformation required Page 34

33 Next-Generation Design System System Design Hardware Development Analog/RF Design Development schematic layout extraction DB Functional spice, verilog-a, verilog vhdl, hdl-ams, mixed signal Performance extracted netlist, resimulation SDF, backannotation, STA Physical Verification Digital Design Development synthesis Place &route extraction Combined: Database - Configuration Management - Constraint System Integrated Functional Verification.. Page 35

34 Close the Functional Verification Gap Abstraction of Information is the Key Analog/RF Design Digital Design VHDL/Verilog VHDL/Verilog Mixed-Signal, FastMOS VHDL-AMS VHDL/Verilog SPICE Key Requirements VHDL/Verilog netlist generation of RF+Mixed Signal parts Consistency Check: VHDL/Verilog model vs. Spice Page 36

35 Complexity Challenges for Analog System Performance Simulations Netlist reduction techniques Enhanced Spice Solver Capabilities Number of Netlist Elements Current Complexity in our RF Designs Required Complexity Reduction: ~ Manageable Complexity Behavioral Circuit Block Modeling Analog Simulation Capability Page 37

36 Outline! Introduction: Communication Market! Engineering Challenges! Opportunities and Challenges for EDA " System Level Design " System on Chip: RF and Digital Baseband in CMOS " Chip Package Co-Design! Summary and Conclusions Page 38

37 Next Generation High Density logic IC Packages Wafer-Level Ball-Grid Arrays (WLB) SG-VLWLB (Silicon Green Very Thin Fine Pitch Wafer Level Ball Grid Array) - based on thin-film technology - solder ball grid array fabricated on wafer level. WLB QFP BGA FC-BGA SIP Features: % True chip size package % Thinnest packages possible % Applicable for a wide range of chip sizes % Various ball pitches available % Good thermal and electrical performance Infineon s Hammerhead 2 SG-VFWLB-49 Page 39

38 Many Advantages but very challenging for our Chip-Package Design Environment Advantages in Size / Dimensions & Smallest package heights & Minimum lateral area WLB-49 Electrical / Thermal Performance & Smaller interconnect line length & Reduced package parasitics & Higher package speed Improved Chip to Board Coupling & Better heat dissipation Solder Ball Dielectric 2 (Solder Stop) Redistribution layer with UBM Dielectric 1 Chip with Al-pad Page 40

39 The Dimension Challenge PCB RDL Constraint management Printed Board (PCB) WLB (Package) System on Chip only 6 µm distance millimeter routability micrometer extraction nanometer Dimension gap IC Macro Design Floorplan Today s isolated development domains (PCB, Package, IC) come together Page 41

40 Integrated Chip-Package Co-Design Environment System Design Chip Package Co-Design Concurrent Design of IC and Package: ' Common routing of IC and RDL (= ReDistribution Layer) ' Solution for common extraction (package and IC) ' Simulation of electromagnetic inference (EMI) ' Support for multi technology simulation System Integration & Verification Page 42

41 Outlook: WLB offers new Design Options Embedded Passives in Wafer Level BGA Using RDL Layer for signal routing & cheaper masks & higher flexibility for Re-Designs & better electrical performance for supply nets Capacitors Inductors We will need a Design Environment to handle this! Inductor Capacitor Feeding Using of metal layer surrounding thin film dielectric Die Loops Feeding Feeding Plate 2 PBO Plate 1 PBO Mold Compound Resistors Page 43

42 Outline! Introduction: Communication Market! Engineering Challenges! Opportunities and Challenges for EDA " System Level Design " System on Chip: RF and Digital Baseband in CMOS " Chip Package Co-Design! Summary and Conclusions Page 44

43 Beyond IC Design Challenges for EDA Summary and Conclusions System Level Design " Deploy and improve TLM standards " Enable TLM as executable spec and verification reference " Embrace single source concept and code generation " Complement System Level tool centric business model with strong System Level IP offering SoC Design: RF and Digital " Common Design Database for Digital and Analog/RF designs " More efficient functional verification methodology for RF " More powerful performance simulation Advanced Packaging: Chip-Package Co-Design " Design Environment for co-design of ICs, packages, and PCBs " Enable concurrent verification of ICs, packages, and PCBs Page 45

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