TechSearch International, Inc.

Transcription

1 On the Road to 3D ICs: Markets and Solutions E. Jan Vardaman President TechSearch International, Inc.

2 High future cost of lithography Severe interconnect delay Noted in ITRS roadmap Bottleneck for higher bandwidth Device latency issues Power management, delivery, and distribution needs Demand for smaller form factor, low profile packages Drivers for 3D ICs Remain the Same Source: Intel Source: Renesas Source: Intel

3 Stacked Memory with TSV Flash memory R&D at IM Flash, Samsung, Toshiba, etc. DRAM prototypes and programs Micron/Elpida SK Hynix Samsung Nanya? Tezzaron high-speed SRAM memory in production IBM and Intel have agreements with Micron for cube Engineering samples promised, HVM scheduled for 2014 Source: Tezzaron Source: Elpida

4 Challenges for 3D IC High Volume Manufacturing Availability of commercial 3D EDA tools: IMPROVEMNTS HAVE BEEN MADE Floorplanning Routing Power/signal integrity Micro bumping and assembly for finer pitch Higher throughput for fine pitch bonding Wafer thinning, specifically the debonding step in the temporary bonding process Higher yields required Thermal, where logic is part of the stack: NO COMMERCIAL SOLUTION Need cost effective thermal solution Thermally aware design tools Test methodology and solution: NEEDS MORE WORK KGD Yield Test methods Infrastructure related issues: NEEDS MORE WORK Logistics Supply chain handoff Who is responsible for bad parts Reliability data to meet customer requirements Cost reduction compared to alternatives NEEDS MORE WORK Cost/performance trade-off is key

5 Thermal Considerations DRAM expects uniform temperature of device Logic chip can generate hot spots caused by non-uniform duty cycle of modules Source: Intel

6 Current State of 3D/2.5D Cost Via fabrication and via fill have seen great improvement Yield is the biggest cost drive today Assembly yield of fine pitch micro bumped components on thin wafers or chips with TSVs is still low Any yield loss in this step is a problem because good die and interposers must be scrapped TSV process costs (via etch, fill, and reveal) are lower than RDL process costs Thin wafer bond/debond throughput is low and yield loss is expensive, although both cost drivers are expected to improve in the future Source: SavanSys Solutions

7 2.5D/3D Cost Modeling Can Be Useful 2.5D/3D Cost Model from SavanSys Solutions Comprehensive model including total product costs and yield for all major flows chip on wafer, chip on chip, chip on substrate Current model focuses on a via middle flow; via last will be added in late 2013/early 2014 Provides two trade-off environments: Design and Process Flow Trade-offs User defines design characteristics and process flow Detailed Cost Trade-offs User adjusts individual equipment costs, yields, throughputs, etc. Current State of 2.5D/3D Cost Issues Yield is the biggest cost driver Assembly yield of fine pitch micro bumped components on thin wafers or chips with TSVs is still low Any yield loss in this step is a problem because good die and interposers must be scrapped TSV process costs (via etch, fill, and reveal) are lower than RDL process costs Thin wafer bond/debond throughput is low and yield loss is expensive, although both cost drivers are expected to improve in the future

8 Alternatives to 3D IC with TSVs 2.5D interposers with TSVs in interposer Allows partitioned design (large chips can be partitioned into smaller ones) Manage chip/package interaction stress for large die with ultra low-k dielectrics Can incorporate integrated passives An interim solution before 3D IC with TSV is possible Planar module with stacked memory adjacent to the processor for high speed memory requirements, can be tested prior to stacking Stacked Packages (packages can be tested, infrastructure exists) PoP Embedded die in bottom PoP Fan-out for bottom PoP

9 High-Performance Interposer Market FPGA Four products shipping today from Xilinx, various sizes of interposers Homogeneous integration solution is partition die so that the large die can be fabricated in slices providing better yield, improved performance Heterogeneous solutions includes FPGA slices and transceiver die plus SERDES Small volume, but helps to develop infrastructure GPU/CPU Provide higher performance with memory stack next to processor ASIC High-end applications where ASIC is mounted on an interposer next to a memory stack An interposer to mount the silicon with ELK dielectric before mounting on package substrate Tablets Potential solution with lower cost interposer Automotive 3D IC stacks with image sensors and other sensors for obstacle detection, collision avoidance, driving and parking assistance Stacks mounted on silicon interposer demonstrated in ASET program

10 IBM worked with Semtech to develop a silicon interposer to connect analog converter functions in a logic device with an interleaver IC in IBM s BiCMOS SiGe technology Applications are fiber optic telecom, highperformance RF, test equipment, processing for phased array radar systems IBM s Silicon Interposer

11 Xilinx Heterogeneous Integration on Interposer Highest bandwidth FPGA with 2.78 Tb/s serial connectivity Form-fit-function die for varying design requirements Electrically isolated 28G transceivers for optimal signal integrity Process: 28nm High Performance Low Power Process: 40nm High Performance 28G Transceivers FPGA Fabric 28G Transceivers Passive Interposer Process: 65nm 13G Transceivers Noise Isolation: Digital and analog separated for lowest noise and jitter Source: Xilinx Page 11 Copyright 2012 Xilinx

12 Progression to Stacked Silicon Interconnect (SSI): It Takes Time Stacked Silicon Interconnect Development Started 90nm Process Integration And Modular Development 90nm Test Vehicle Completed 65nm Test Vehicle Completed 28nm Test Vehicle Completed Design Tools Available Heterogeneous Stacked Silicon Interconnect Technology Initial Reliability Assessment Design Enablement and Supply Chain Validation Process Qualification Design Validation Today World s First 3D Stacked Silicon Interconnect Device Source: Xilinx

13 Barriers to Silicon Interposer Implementation Infrastructure immaturity All components of technology are not ready for immediate implementation, especially for fabless companies Supply chain handoff needs to be defined Assembly by OSAT or Foundry? Is there test or only inspection? Who is in charge? Cost Especially for high via counts Yield hit for large substrates Biggest cost driver is yield loss, not process cost (SavanSys Solutions) Glass interposers for lower cost? Organic interposers as an alternative? Routing Density Trade-offs Longer reach lower density/data-rate Higher IO power can address long reach Reticle Field Size Maximum front-end reticle field size = 26mm x 32mm Back-end steppers have larger exposure fields, coarser traces Source: Ultratech

14 Silicon Interposers Foundry Interposers with TSVs ALLVIA TSMC UMC IBM GLOBALFOUNDRIES Novati Technologies YOUR NAME HERE OSAT Interposers with TSVs ASE SPIL Interposers for MEMS with TSVs DNP IMT Silex Microsystems Others Interposers with Integrated Passives (with or without TSVs) IPDiA STATS ChipPAC Source: Xilinx Source: DNP Source: IPDiA

15 PoP and other packages Fan-out WLP Embedded active components Other Alternatives

16 Package-on-Package (PoP) Replaced stacked die with wire bond for memory and logic Memory sourcing Test issues Individual packages are stacked on top of each other Separate package for logic Separate package for memory Packages individually tested before stacking Smartphones and tablets use PoP, some digital cameras New developments enabling thinner packages Embedded PoP with die embedded in the substrate of the bottom package ewlb versions using a fan-out technology Source: Amkor Source: TI

17 CoC with no TSV Lid (Heatsink) Substrate Mother-Daughter Connections for Predictable Joint Height Solder Ball Connection Cu Post (plated from top or bottom) Copper Pillar Connection Mother Die Source: Amkor Cu Pillar array with SnAg cap (plated from top and/or bottom) Daughter Die

18 FO-WLP Reconstituted wafer and perimeter mold compound allows for redistribution of I/O beyond current chip footprint Considered an embedded package by some Fan-out WLP from ADL Engineering, Amkor, ASE, Deca Technologies, Freescale Semiconductor, FCI/Fujikura, J-Devices, NANIUM, Nepes, SPIL, STATS ChipPAC, TSMC, and YOUR NAME HERE Infineon ewlb (wireless operation acquired by Intel) Technology licensed by ASE, STATS ChipPAC, NANIUM Companies have installed production lines Applications Wireless products today Potential for memory, PMIC, ASIC, RF, AP/BB, controllers, media chips, medical devices, sensors Future possibility in automotive and other applications FO-WLP shipments of 616 million units in 2012 Infineon (now Intel s IMC) wireless products Spreadtrum announced adoption in Jan for China market Others Future growth requires cost reduction Panel process? Lower cost materials? Intel Wireless Division LTE analog baseband 5.32 x 5.04 x 0.7mm ewlb 127 balls, 0.4mm pitch Source: TPSS

19 Embedded Components Formed Materials are added to the printed circuit structure to create the passive element. Placed The component is placed on an internal layer then buried as additional layers are added. Resistors Capacitors Active Passive Source: JISSO International Council, May 2004 KGDpanel TechSearch International, Inc.

20 Conclusions 3D IC? Industry is working to resolve issues that will allow 3D with TSVs Much work needed 2.5D Before 3DIC (silicon interposers?, organic? glass?) ASIC GPU/CPU Depends on timing of stacked memory Concern about suppliers and assembly capability Expect new players Business models still evolving Cost remains a concern in every discussion