Three Dimensional Integration

Transcription

1 Three Dimensional Integration Paul Franzon North Carolina State University Raleigh, NC

2 Outline 3DIC Motivation Performance and Memory Bandwidth Power Efficiency Power per unit of cost Miniaturization 3DIC Manufacturing Bulk TSV formation Wafer and chip assembly flows Interposers Relative costs 3DIC Design Power and power efficiency Memories and memory interfaces Electrical modeling & design ESD protection The potential for logic partitioning Heterogeneous Computing Design Support Thermal Design Test issues Potential Test Flows Conclusions and Future perspectives 2

3 Outline 3DIC Motivation Performance and Memory Bandwidth Power Efficiency Power per unit of cost Miniaturization 3DIC Manufacturing Bulk TSV formation Wafer and chip assembly flows Interposers Relative costs 3DIC Design Power and power efficiency Memories and memory interfaces Electrical modeling & design ESD protection The potential for logic partitioning Heterogeneous Computing Design Support Thermal Design Test issues Potential Test Flows Conclusions and Future perspectives 3

4 Memory Bandwidth Most compute systems have rapidly growing memory bandwidth demands Mulitcore Mobile: 50 GBps and more Graphics, Networking: Can easilly benefit from 1 TBps Networking needs high capacity as well Data-driven workloads: High cross-system bandwidth Interposers and 3DIC can provide high memory bandwidth at better power efficiencies than conventional packaging 4

5 Off-chip vs. ON-chip Scaling Trends Source: Poulton, NVidea 5

6 Dark Silicon Performance per unit power Systems increasingly limited by power consumption, not number of transistors Dark Silicon : Most of the chip will be OFF to meet thermal limits 6

7 Server Power Costs 2% of worlds electrical power consumption, predicted to be 30% of US power by 2030 Cost of power growing percentage of cost of ownership Source: IBM 7

8 Compute Cost Scaling beyond 7 nm CMOS CMOS scaling assumed to end around 2020 at around the 7 nm node. We ve achieved exponential gains before without silicon scaling. We can again. 8

9 Cost reduction 3DIC processing adds 15%+ to wafer processing cost Silicon interposers add 25%+ to cost of silicon before packaging Thus seek potential cost reductions Heterogeneous integration Saving on high pin count packaging Reduced cooling overhead Yielded silicon cost savings Yield decreases exponentially with chip area 22 x 22 mm chip : Yield = 44%; Say $62 / part 11 x 22 mm chip: Yield = 64%; Say $42 per pair of parts As long as cost of 3D or 2.5D integration is less than $20, then saved money due to increased yield 9

10 Heterogeneous Integration Digital logic in advanced node (e.g. 22 nm) on top of analog circuits in legacy node (e.g. 45 nm) Optimizes cost per transistor since analog transistors scale poorly Reduces design cost Mixed technologies E.g. InP or GaN on top of silicon Ultra high performance or high power Low power (low leakage) CMOS on top of high performance CMOS Silicon Photonics; MEMS Image Sensors Stack image collection layer on top of information processing layer Lower cost; Specialized sensors; More in-situ computation Xilinx: 28 nm FPGA slices nm SERDES (IO) 10

11 3D Miniaturization Cell phone cameras Height reduction through TSVs Miniature Sensors mm 3 scale Implantable cm 3 scale Food Safety & Agriculture TSVs provide a lot more interconenct than wire bonds MEMS RF harvester/sensor + Antenna Low-power mixed signal ASIC Low power Nonvolatile memory Secondary battery/ultracapacitor 11

12 Outline 3DIC Motivation Performance and Memory Bandwidth Power Efficiency Power per unit of cost Miniaturization 3DIC Manufacturing Bulk TSV formation Wafer and chip assembly flows Interposers Relative costs 3DIC Design Power and power efficiency Memories and memory interfaces Electrical modeling & design ESD protection The potential for logic partitioning Heterogeneous Computing Design Support Thermal Design Test issues Potential Test Flows Conclusions and Future perspectives 12

13 3DIC with TSVs Technology set: Underfill Wafer Thinning 13

14 Commercial TSV Options Tezzaron Down to 1.2 µm features, Tungsten IBM, Samsung, Elpida IMEC 5-10 µm features, Copper CETI/LEA (ST-Micro and others) 5-10 µm features Cu TSMC (& other) interposer 10 µm features, 100 µm pitch Copper Tezzaron IMEC 30µm AllVia 14

15 Transistor/TSV Integration Options Via-First/ Via-Middle Face-to-Face Face-to-Back Back-to-Back Via-Last 15

16 Attachment technologies Solder micobumps Today typically 40 µm pitch; Tomorrow possibly 5 µm high temperature (> 400 Room temperature (Ziptronix DBI) Typical 2 5 µm pitch Potential for 1 µm pitch IBM 16

17 Chip to Wafer (C2W) vs. Wafer to Wafer (W2W) Wafer to Wafer (W2W) Wafer 1 Mount Thin Wafer 2 Wafer 3 Mount Thin Bump Advantages Disadvantages Simpler Identical sized chips Lower Cost Higher via Density Better Alignment Thinner Chips Accumulated Yield Loss 1 tier 2 tiers 3 tiers 4 tiers 90% 81% 73% 65% 17

18 Chip to Wafer (C2W) vs. Wafer to Wafer (W2W) ONE chip to wafer (or wafer stack) (face mounted) Test Wafer 1 Wafer 2 Test Dice Advantages Known Good Die no accumulated yield loss Different die sizes Disadvantages Higher cost serial pick and place Worse alignment Wafer die size largest Solder bump requires coarse TSVs in one layer Limited to stack of two 18

19 Chip to Wafer (C2W) vs. Wafer to Wafer (W2W) Multiple chips to wafer (or wafer stack) Temporary Carrier Wafer 1 Mount Thin Test Dice Attach/Demount Wafer 2 Wafer 3 Test Advantages Known Good Die in multiple chips Thin TSV Little area loss to connections to solder bumps Disadvantages Highest cost temporary carrier Still in research Limited to stack of two 19

20 Interposers and RDLs Redistribution layer = thick metal (layers) added to wafers to customize interface to next chip in 3D stack Interposer = Silicon or other carrier used to mount chips WITHIN package Examples: 1-2 µm thick metal µm Modified Legacy Process Modified 65 nm or 90 nm Back End of Line Process 20

21 Relative Manufacturing Costs ASIC Chip DRAM Chip DRAM KGD Test/chip ASIC KGD Test/chip Assembled stack test W2W 3D steps / chip C2W 3D steps / chip Interposer / chip stack 2,000 pin package ($10) 21

22 Outline 3DIC Motivation Performance and Memory Bandwidth Power Efficiency Power per unit of cost Miniaturization 3DIC Manufacturing Bulk TSV formation Wafer and chip assembly flows Interposers Relative costs 3DIC Design Power and power efficiency Memories and memory interfaces Electrical modeling & design ESD protection The potential for logic partitioning Heterogeneous Computing Design Support Thermal Design Test issues Potential Test Flows Conclusions and Future perspectives 22

23 Energy per Operation DDR3 4.8 nj/word Optimized DRAM core 128 pj/word MIPS 64 core 400 pj/cycle 11 nm 0.4 V core 200 pj/op 45 nm 0.8 V FPU 38 pj/op SERDES I/O 1.9 nj/word Low swing I/O 128 pj/word LPDDR2 512 pj/word 1 cm / high-loss interposer 300 pj/word 0.4 V / low-loss interposer 45 pj/word On-chip/mm 7 pj/word TSV I/O (ESD) 7 pj/word TSV I/O (secondary ESD) 2 pj/word (64 bit words) Various Sources 23

24 Energy/Operation 32 bit ops Energy / Operation (pj) PCB 2MB L2 Cache 3 mm on-chip Interposer Multiply Accumu 8kB L2 Cache TSV 50 Register File Node (nm) 24

25 Energy/Operation Ratio TSV 3 mm on-chip Interposer IO PCB IO 2MB L2 8kB cache RF FPU-MAC 1.15x 3.6x pj/32-bit op 25

26 Detailed Comparison Simulation Study pj/bit 26

27 Memory on Logic Conventional TSV Enabled Less Overhead Flexible bank access Nx32 Less interface power N x 128 wide I/O Flexible architecture nvidea or Short on-chip wires or Processor Mobile 27 27

28 Wide IO SOC Standard aimed at mainly at Mobile First standard was under-specified limiting interoperability ST, STM, LETI, Cadence ST-Ericsson 28

29 HBM and HMC 128 GBps ST-Ericsson 29

30 Tezzaron Dis-integrated RAM Mixed technology concept DRAM arrays in low-leakage DRAM technology (at node N) Peripheral circuits in highperformance logic process (at node N-1) Bit and word lines fed vertically at array edge No repair or test prior to assembly BIST and CAM based remapping in logic layer Claimed results Reduced overall cost/bit Two metals only in DRAM tiers Effective ~ 60-70% fill factor (?) Faster timing on interfaces, down to 3 ns RAS-RAS cycle Configuration Density Burst access in page/port 8 x 128-bit ports 90 nm DRAM on 130 nm logic 1 Gb/layer of DRAM 1 Gword/s (128 Gbps) 30

31 IMEC TSV Parasitics Plas et.al., ISSCC ff On-chip interconnect: ~ ff/mm 31

32 ElectroStatic Discharge (ESD) Protection There are NO published definitive studies as to what level of ESD protection is needed R Current working assumptions 3D integration through interposer Need full ESD protection (~ 1 pf) Can distribute amongst tiers 3D integration through stacking in separate fabs Need machine model ESD protection only (~250 ff) 3D integration within fab Fab can specify (Tezzaron: Antenna diode) 32

33 Logic Partitioning Approaches 1. Modular Partitioning 30% improvement in power/performance 2. Cell level partitioning 18% - 35% improvement in power/performance 3. Heterogeneous Integration 30% improvement in power/performance 4. Extreme 3DIC Stacking > 4 chips to effect HP CPU Low Power CPU Specialized RAM General RAM Interconnect Modular Bus 33

34 Modular Partitioning 3D FFT Engine 60% energy per op savings in memory 9% energy per op savings in logic 25% more silicon as 2DIC Thor Thorolfsson 34

35 Tezzaron 130 nm 3D SAR DSP Complete Synthetic Aperture Radar processor 10.3 mw/gflops 2 layer 3D logic All Flip-flops on bottom partition Removes need for 3D clock router Logic only Logic, clocks, flip-flops HMETIS partitioning used to drive 3D placement Thor Thorolfsson 35

36 Cell level partitioning Relying on wire-length reduction alone is not enough 2D Design 0.13 µm Cell Placement split across 6.6 µm face-to-face bump structure 36

37 Fast thread transfer Two heterogeneous cores Different clocks Nominally different process nodes PISA (MIPS-like) instruction set 3D-enabled bus provides fast thread transfer (FTT) <50 CPU cycles to move process from one core to another, or to swap process Varies as controlled by a third, faster clock Switch L1 cache connection at same time (CTT) Comparison with Running Data in 2-issue CPU alone: Energy / op Performance 1-issue CPU alone 28% savings 39% reduction Two CPU stick with FTT and CTT 27% savings 7% reduction 2-issue CPU 1-issue CPU c/- Brandown Dwiel, Eric Rotenberg 37

38 Specialized RAM as L2/L3 cache Specialized Tezzaron DRAM as combined L2/L3 Cache Capable of 3 ns RAS-RAS cycle Specialized RAM Option Performance Power (W) 4MB SRAM cache 1x 2.4 W 240 MB DRAM 1.89 x 0.53 W Brings 16 core system power down by 15% 38

39 Plug and Play Interfaces Self-configuring, self-testing, resilient, low-overhead, lowpower interfaces that can communicate between different clock-domains Face to Face Face to Back Cache/Memory... Processor Distributed Request Module #A Local Initiator #A ENB Local Target #X Distributed Request Module #B Distributed Request Module #C ENB ENB ENB ENB Tri-state Buffer ENB ENB ENB TSV Request channel #0-3 TSV Data channel #0-3 39

40 Outline 3DIC Motivation Performance and Memory Bandwidth Power Efficiency Power per unit of cost Miniaturization 3DIC Manufacturing Bulk TSV formation Wafer and chip assembly flows Interposers Relative costs 3DIC Design Power and power efficiency Memories and memory interfaces Electrical modeling & design ESD protection The potential for logic partitioning Heterogeneous Computing Design Support Thermal Design Test issues Potential Test Flows Conclusions and Future perspectives 40

41 CAD Thermal Pathfinding Early design and technology investigation NCSU Pathfinding flow: ESL model DOE SystemC Power Scoreboard Static & Dynamic Thermal Visualization & Model Fitting Physical & Technology Parameters Offmodule Power Delivery Partitioning 41

42 Thermal Mitigation: DVFS As L2 channel temperature on Tier B, reaches 385K, downscale the voltage and frequency As channel temperature reaches 370K, upscale the voltage and frequency Further decrease in temperature is due to changing (decrease) power profile Two (V,F) point: (1.1V, 1.66GHz), (0.9V, 1.36 GHz) 42

43 Thermal Management With conventional cooling technologies: Leverage low-power potential of 3DIC Use of thermal vias and power/ground system Dynamic in-situ thermal management With liquid cooling Potential reduction in cost of cooling, together with increase in performance Advanced liquid cooling demonstrated up to 3.5 kw/cm 2 43

44 Test Issues Want to minimize total cost of test and test-escape Extremes: Stack and Pray = accumulated yield loss 1 chip 2 chips 3 chips 4 chips 90% 81% 73% 64% 100% Test before assembly and after each assembly event = high test cost Do we test through the TSV/microbump interface or around it? Testing a 10,000 microbump array is difficult and potentially very expensive 44

45 Basic Test Flow Assumptions: TSV/interposer yield high enough not to need redundancy Might or might not test partial stacks Memories SOCs Wafer Test Burnin Repair Wafer Test to (close to) Known Good Die Standard Sort & Stack or Stack + test Stack + test 3D Integration Test & possibly Memory BIST Packaging and Final Test Complete stack 45

46 Concluding Remarks As off-chip bandwidth requirements and hunger for low power expands: 3D packaging Interposers 3DIC BUT Interposers are expensive and potential for cost reduction is modest 3DIC is expensive but there is potential for process learning AND great benefit harvesting Especially once D2W is solved Thermal and power delivery will remain challenges and bottlenecks with technology advances Test and resiliency are potential interesting research vectors 46

47 Acknowledgements Faculty: Rhett Davis, Michael B. Steer, Eric Rotenberg, James Tuck, Huiyang Zhou Professionals: Steven Lipa, Eric Wyers Current Students: Joonmu Hu, Brandon Dwiel, Zhou Wang, Marcus Tishibanqu, Ellliott Forbes, Randy Wilkiansano, Joshua Ledford, Jong Beom Park, Past Students: Hua Hao, Samson Melamed, Peter Gadfort, Akalu Lentiro, Shivam Priyadarshi, Christopher Mineo, Julie Oh, Won Ha Choi, Ambirish Sule, Gary Charles, Thor Thorolfsson, Department of Electrical and Computer Engineering NC State University

48 Removed 48

49 Bandwidth Density High off-chip bandwidth density required to close off-chip performance gap Determined by technology; crosstalk and signaling rate limits 1 mm x BW/wire Upper limits Technology Approximate limit High density laminate ~ 50 Gbps/mm Silicon interposer ~ 150 Gbps/mm 3DIC - microbumps > 10 Tbps/mm 2 3DIC - TSV > 1 Tbps/mm 2 49

50 Yield Improvement Example: Xilinx multi-chip Virtex 7 50

51 Simplified Process Flow 1. Etch TSV holes in substrate Max. aspect ratio 10:1 hole depth < 10x hole radius 2. Passivate side walls to isolate from bulk 51

52 Simplified Process Flow 3. Fill TSV with metal Copper plating, or Tungsten filling 4. Often the wafer is then attached to a carrier or another wafer before thinning 5. Back side grinding and etching to expose bottom of metal filled holes 6. Formation of backside microbumps Wafer Thinning 52

53 Simplified Process Flow 7. Wafer bonding and (sometimes) underfill distribution Underfill TSV enabled 3D stack 53

54 Substrate Alternatives Side-by-side mounting Silicon Interposer or thin film Multi-chip Module RAM ASIC ASIC RAM ASIC No TSVs TSV Enabled Top-to-bottom mounting Face-up-Silicon Interposer ASIC Memory Conventional Interposer e.g. High Density Laminate ASIC Memory TSV Enabled Silicon Interposer 54

55 Glass Interposers Leveraging large panel (TV) processing for cost reduction Still in development Coarser TSV pitch and line widths than Silicon 55

56 Detail Energy / Operation (pj) FPU-MAC RF 8kB cache TSV Node (nm) 56

57 Design Status 130 nm 2D Design in Fab 65 nm 3D design for May tapeout 57

58 Design and Verification CAD Flows All major vendors have extensions to the current flows for 3D integration purposes Electrical parasitics, including TSVs Full stack verification Full stack test insertion (in part) TSV/package stress management (coming) Likely approach: Post assembly transistor SPICE models Low/Zero commercial availability Pathfinding tools Tools to support aggressive 3D integration 58

59 Heterogeneous Integration - Computing Illustrates value of leveraging of 3D state of the art 10% - 30% logic { power savings { 8x power savings in L2-L3 { 2x interconnect power { savings High Performance CPU Low Power CPU Specialized RAM Specialized Interconnect 59

60 Extreme 3D Aggressive exploitation of 3DIC and high density photonics High density, vertical connections Ability to build systems that continue high density beyond a small range of chips High density, multi-wavelength low-power photonics connectors 60