Hi-ESD Pad Library TSMC CMOS (0.35µ) Process

Transcription

1 2650 East Foothill Blvd. Pasadena, CA USA Tel: (626) Fax: (626) Consulting & Engineering Services CE-LI-CC- IOmosis35 The MOSIS Service Hi- Pad Library TSMC CMOS (0.35µ) Process June 1999 Tanner Consulting & Engineering Services develops and delivers advanced ASIC and VLSI solutions for customers. We accomplish this through training programs, consulting services, field engineering and contracted design/development efforts. Copyright 1999 by Tanner Research, Inc. All rights reserved

2 Consulting & Engineering Services CE-LI-PR-CE TANNER CES GENERAL TERMS & CONDITIONS Liability All designs will be implemented under the Client s front-end specification. Our contracted engineering services are accomplished for the Client on a best effort basis. Quality assurance is achieved by arriving at a common understanding of the nature of the Project among the engineers and managers at the Client operation and at Tanner CES. Tanner Research is not liable for the functionality, quality, or performance of the Client s future Projects using components produced as part of the contracted work. Tanner Research is not liable if the Client chooses to use our recommended design or application methodologies. If prototype chips are delivered, the process vendors do not generally guarantee yield, quality, or performance of their products. Neither does Tanner Research extend any warrantee to the contracted design and its fabricated results. Non-Disclosure Agreement Non-disclosure agreements (NDAs) serve the following purposes. Signed between the Client and Tanner Research, the NDA protects Client s original concept, status, and intentions in current and future product development and manufacturing. Signed between the Client and Tanner Research, the NDA protects Tanner Research specific technologies, IC libraries, building blocks and methodologies that are developed prior to the Client Project, or developed specifically for the Client application. Specific non-disclosure or non-distribution conditions may be added to the Statement of Work for individual Client Projects. These conditions do not replace or supercede any previously signed NDA; rather they serve as additional constraints to the NDA. During or at the end of the Client Project, if we communicate with a process vendor or receive fabricated parts from a process vendor which will be forwarded to the Client, we assume that the Client is also a current customer of the vendor. We may request Client to provide a proof of its NDA with the vendor before any such communication or transaction. Ownership of Work Results The Client owns the delivered version and the fabricated version of the work results from a contracted Client Project. These results are subject to the following re-distribution conditions: The Client agrees to use the work results only in its own Projects or products, as developed by the Client and on the Client s own site. The Client will not distribute copies of the delivered data files and documents (such as design, libraries, process technology setups, design flows and methodologies, software utilities, etc.) to any third parties or to any other Client site, with the following two exceptions: Exception 1: If applicable, results can be delivered to the Government Agency sponsoring the Client Project, if such delivery is negotiated as part of the Client Project. During contract negotiations, the Client shall inform Tanner Research about such a delivery and receive advance agreement from us for the contents to be disclosed. Exception 2: If applicable, results can be incorporated into published academic research or presented for academic purposes. During contract negotiation, the Client shall inform Tanner Research about such a presentation and receive advanced agreement from us for the contents to be disclosed. Any other exceptions shall be specified in a written document signed by both the Client and Tanner Research. Tanner Research does not own the original design and application concepts from the Client. We agree not to disclose the Client s proprietary design and applications information. However, we shall distinguish the following items that remain the property of Tanner Research: The methodology used through the development of the Client Project, or that we planned for Client to apply the Project s results, are usually either common knowledge in the industry or specific methods invented by Tanner Research. Using or adopting these methodologies in the Client Project does not institute the Client s ownership to these methodologies. Client does not own Tanner Research s general-purpose building elements (such as cell libraries, building blocks, IO pad cells, etc.) that we utilize in a contracted Project. These building elements are Tanner Research s current design resources that are widely used internally and/or distributed as commercial products. Using these building elements does not institute the Client s ownership of them. Protect Tanner Research s Engineering Resources Through the entire Client Project cycle, starting from bid and proposal to the end of the Project, the Client will contact various engineering resources within Tanner Research. These resources may include Tanner Research s employees and its associates (subcontracting firms or individuals). The Client agrees not to recruit or hire any of these individuals or contract with any firms during the three years following Project completion.

3 A B C D E F G 1 1 pitch = 0.09 mm (450 lambda) MOSIS TSMC/HP 0.35um Hi- Minimum Pad Frame (1) lambda = 0.20um mm (4500 lambda) 1.5 mm (7500 lambda) mm (4500 lambda) mm (7500 lambda) Tel: (626) Fax: (626) East Foothill Blvd, Pasadena, CA Created:Nov 9, :15:18 Size: 5x7 Modified:Jun 15, :36:11 5 Info:MOSIS TSMC/HP 0.35um Hi- IO Pad Set Rev A 5 Designer:Victor Dinh Module:Pad_Frame :0 Path:O:\ces_prjct\mosis\Pad U\work_dir\layout_TSMC035\mlou\databook\Hi_Pad2 A B C D E F G

4 A B C D E F G 1 1 pitch = 90 micron (450 lambda) MOSIS TSMC/HP 0.35um Hi- Pad Dimensions 2 BONDING PAD 60 micron (300 lambda) BONDING PAD (1) lambda = 0.20um 2 60 micron (300 lambda) 300 micron (1500 lambda) 78 micron (390 lambda) TRANSISTOR TRANSISTOR micron (1155 lambda) PAD PAD 46 micron (230 lambda) 4 78 micron (390 lambda) TRANSISTOR TRANSISTOR 4 90 micron (300 lambda) Tel: (626) Fax: (626) East Foothill Blvd, Pasadena, CA Created:Nov 9, :20:00 Size: 5x7 Modified:Jun 15, :34:21 Info:MOSIS TSMC/HP 0.35um Hi- IO Pad Set Rev A 5 5 Designer:Victor Dinh Module:Pad_Dimension :0 Path:O:\ces_prjct\mosis\Pad U\work_dir\layout_TSMC035\mlou\databook\Hi_Pad2 A B C D E F G

5 Pad Library PADLIB Description: Pad Library Library: MOSIS TSMC 035P Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples Schematic: S-Edit File: TannerLb\scmos\mTSMs035P.sdb Module: Library Mask layout: L-Edit File: TannerLb\scmos\mTSMs035P.tdb Cell: Lib_Pads Mapping Macros: GateSim: TannerLb\nettran\scmos\scms2sim.mac L-Edit/SPR: TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table Capacitance Height Width Area Equivalent Gate Drive Logic Equation Delay Characteristics: Hi- Pad Cell Library PADLIB 1 of 4

6 Pad Library PADLIB This page is intentionally left blank. Hi- Pad Cell Library PADLIB 2 of 4

7 Pad Library Schematic PADLIB MOSIS TSMC 0.35um - Submicron Rules Hi- IO PAD SET Input Pad with Buffer Vdd Pad with Gnd Pad with PadOut_SCMOS PadVdd PadGnd Output Pad with Buffer Analog IO Pad with Analog Reference Pad with PadInC_SCMOS PadIO PadARef DI_UNBUF DI PAD DO PAD DIB IPadC OPad Hi- Pad Cell Library PADLIB 3 of 4

8 Pad Library Layout PADLIB Hi- Pad Cell Library PADLIB 4 of 4

9 Pad Frame PADFRAME Description: Pad Frame Library: MOSIS TSMC 035P Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples Schematic: S-Edit File: TannerLb\scmos\mTSMs035P.sdb Module: Mask layout: L-Edit File: TannerLb\scmos\mTSMs035.tdb Cell: FRAME Mapping Macros: GateSim: TannerLb\nettran\scmos\scms2sim.mac L-Edit/SPR: TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table Capacitance Height Width Area Equivalent Gate Drive 1.5 mm 1.5 mm 2.25 mm 2 Logic Equation Delay Characteristics: Hi- Pad Cell Library PADFRAME 1 of 4

10 Pad Frame PADFRAME This page is intentionally left blank. Hi- Pad Cell Library PADFRAME 2 of 4

11 Pad Frame Schematic PADFRAME Hi- Pad Cell Library PADFRAME 3 of 4

12 Pad Frame Layout PADFRAME Hi- Pad Cell Library PADFRAME 4 of 4

13 Analog Ref Pad PADAREF Description: Analog Reference Pad Library: MOSIS TSMC 035P Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples Schematic: S-Edit File: TannerLb\scmos\mTSMs035P.sdb Module: PADAREF Mask layout: L-Edit File: TannerLb\scmos\mTSMs035P.tdb Cell: PADAREF Mapping Macros: GateSim: TannerLb\nettran\scmos\scms2sim.mac L-Edit/SPR: TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table Capacitance PadARef Height Width Area Equivalent Gate Drive 300 µ 90 µ µ 2 Logic Equation Delay Characteristics: Hi- Pad Cell Library PADAREF 1 of 4

14 Analog Ref Pad PADAREF This page is intentionally left blank. Hi- Pad Cell Library PADAREF 2 of 4

15 Analog Ref Pad Schematic PADAREF PadARef TP W='175*l' L='3*l' M=16 SIGNAL BONDING PAD SIGNAL TN W='175*l' L='3*l' M=16 Hi- Pad Cell Library PADAREF 3 of 4

16 Analog Ref Pad Layout PADAREF Hi- Pad Cell Library PADAREF 4 of 4

17 Bi-Directional Pad PADBIDIR Description: Bi-Directional Pad with Buffer Library: MOSIS TSMC 035P Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples Schematic: S-Edit File: TannerLb\scmos\mTSMs035P.sdb Module: PADBIDIR Mask layout: L-Edit File: TannerLb\scmos\mTSMs035P.tdb Cell: PADBIDIR Mapping Macros: GateSim: TannerLb\nettran\scmos\scms2sim.mac L-Edit/SPR: TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table Capacitance PadBidirHE_SCMOS PAD OE DI DO X 1 X In X X Height Width Area Equivalent Gate Drive 300 µ 90 µ µ 2 Logic Equation See truth table Delay Characteristics: Hi- Pad Cell Library PADBIDIR 1 of 4

18 Bi-Directional Pad PADBIDIR This page is intentionally left blank. Hi- Pad Cell Library PADBIDIR 2 of 4

19 Bi-Directional Pad Schematic PADBIDIR DataIn T11 W='52*l' L='3*l' M=6 T12 W='35*l' L='3*l' M=6 DataInB T9 W='52*l' L='3*l' M=6 T10 W='35*l' L='3*l' M=6 100 R1 Pad EN DataOut OEB L='3*l' T13a W='52*l' L='3*l' T13b W='35*l' T1 W='52*l' L='3*l' M=5 TP2 W='175*l' L='3*l' M=12 T2 W='52*l' L='3*l' M=4 T3 W='35*l' L='3*l' M=5 L='3*l' T14a W='52*l' OEB OE L='2*l' T14b W='35*l' OE OE T5 W='35*l' L='2*l' M=4 OEB T6 W='35*l' L='3*l' M=5 TN2 W='175*l' L='3*l' M=14 T4 W='52*l' L='3*l' M=5 TP1 W='175*l' L='3*l' M=4 TN1 W='175*l' L='3*l' M=2 BONDING PAD Hi- Pad Cell Library PADBIDIR 3 of 4

20 Bi-Directional Pad Layout PADBIDIR Hi- Pad Cell Library PADBIDIR 4 of 4

21 Pad Frame Corner PADFC Description: Pad Frame Corner Library: MOSIS TSMC 035P Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples Schematic: S-Edit File: TannerLb\scmos\mTSMs035P.sdb Module: Mask layout: L-Edit File: TannerLb\scmos\mTSMs035P.tdb Cell: PADFC Mapping Macros: GateSim: TannerLb\nettran\scmos\scms2sim.mac L-Edit/SPR: TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table Capacitance Height Width Area Equivalent Gate Drive 300 µ 300 µ µ 2 Logic Equation Delay Characteristics: Hi- Pad Cell Library PADFC 1 of 4

22 Pad Frame Corner PADFC This page is intentionally left blank. Hi- Pad Cell Library PADFC 2 of 4

23 Pad Frame Corner Schematic PADFC Hi- Pad Cell Library PADFC 3 of 4

24 Pad Frame Corner Layout PADFC Hi- Pad Cell Library PADFC 4 of 4

25 Ground Pad PADGND Description: Ground Pad Library: MOSIS TSMC 035P Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples Schematic: S-Edit File: TannerLb\scmos\mTSMs035P.sdb Module: PADGND Mask layout: L-Edit File: TannerLb\scmos\mTSMs035P.tdb Cell: PADGND Mapping Macros: GateSim: TannerLb\nettran\scmos\scms2sim.mac L-Edit/SPR: TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table Capacitance PadGnd Height Width Area Equivalent Gate Drive 300 µ 90 µ µ 2 Logic Equation Delay Characteristics: Hi- Pad Cell Library PADGND 1 of 4

26 Ground Pad PADGND This page is intentionally left blank. Hi- Pad Cell Library PADGND 2 of 4

27 Ground Pad Schematic PADGND PadGnd TP W='175*l' L='3*l' M=16 BONDING PAD Pad Hi- Pad Cell Library PADGND 3 of 4

28 Ground Pad Layout PADGND Hi- Pad Cell Library PADGND 4 of 4

29 Input Pad Description: Buffered Input Pad with Complementary Signals PADINC Library: MOSIS TSMC 035P Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples Schematic: S-Edit File: TannerLb\scmos\mTSMs035P.sdb Module: PADINC Mask layout: L-Edit File: TannerLb\scmos\mTSMs035P.tdb Cell: PADINC Mapping Macros: GateSim: TannerLb\nettran\scmos\scms2sim.mac L-Edit/SPR: TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table Capacitance Pad PadInC_SCMOS Pad DataIn DataInB PAD DI DIB Height Width Area Equivalent Gate Drive 300 µ 90 µ µ 2 Logic Equation See truth table Delay Characteristics: T pd = 0.28ns T r = 0.24ns T f = 0.18ns Hi- Pad Cell Library PADINC 1 of 4

30 Input Pad PADINC This page is intentionally left blank. Hi- Pad Cell Library PADINC 2 of 4

31 Input Pad Schematic PADINC PadInC Pad DataIn DataInB PadBidirHE_SCMOS Pad Hi- Pad Cell Library PADINC 3 of 4

32 Input Pad Layout PADINC Hi- Pad Cell Library PADINC 4 of 4

33 Input/Output Pad PADIO Description: Input/Output Pad Library: MOSIS TSMC 035P Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples Schematic: S-Edit File: TannerLb\scmos\mTSMs035P.sdb Module: PADIO Mask layout: L-Edit File: TannerLb\scmos\mTSMs035P.tdb Cell: PADIO Mapping Macros: GateSim: TannerLb\nettran\scmos\scms2sim.mac L-Edit/SPR: TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table Capacitance PadIO Height Width Area Equivalent Gate Drive 300 µ 90 µ µ 2 Logic Equation Delay Characteristics: Hi- Pad Cell Library PADIO 1 of 4

34 Input/Output Pad PADIO This page is intentionally left blank. Hi- Pad Cell Library PADIO 2 of 4

35 Input/Output Pad Schematic PADIO PadIO TP W='175*l' L='3*l' M=16 SIGNAL BONDING PAD R1 100 DATA TN W='175*l' L='3*l' M=16 Hi- Pad Cell Library PADIO 3 of 4

36 Input/Output Pad Layout PADIO Hi- Pad Cell Library PADIO 4 of 4

37 Padless Spacer PADSPACE Description: Padless Spacer without Bonding Pad Library: MOSIS TSMC 035P Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples Schematic: S-Edit File: TannerLb\scmos\mTSMs035P.sdb Module: Mask layout: L-Edit File: TannerLb\scmos\mTSMs035P.tdb Cell: PADSPACE Mapping Macros: GateSim: TannerLb\nettran\scmos\scms2sim.mac L-Edit/SPR: TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table Capacitance Height Width Area Equivalent Gate Drive 300 µ 90 µ µ 2 Logic Equation Delay Characteristics: Hi- Pad Cell Library PADSPACE 1 of 4

38 Padless Spacer PADSPACE This page is intentionally left blank. Hi- Pad Cell Library PADSPACE 2 of 4

39 Padless Spacer Schematic PADSPACE Hi- Pad Cell Library PADSPACE 3 of 4

40 Padless Spacer Layout PADSPACE Hi- Pad Cell Library PADSPACE 4 of 4

41 Pad NoConnect PADNC Description: Pad Spacer with No Connection to Bonding Pad Library: MOSIS TSMC 035P Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples Schematic: S-Edit File: TannerLb\scmos\mTSMs035P.sdb Module: Mask layout: L-Edit File: TannerLb\scmos\mTSMs035P.tdb Cell: PADNC Mapping Macros: GateSim: TannerLb\nettran\scmos\scms2sim.mac L-Edit/SPR: TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table Capacitance Height Width Area Equivalent Gate Drive 300 µ 90 µ µ 2 Logic Equation Delay Characteristics: Hi- Pad Cell Library Copyright PADNC 1 of 4

42 Pad NoConnect PADNC This page is intentionally left blank. Hi- Pad Cell Library PADNC 2 of 4

43 Pad NoConnect Schematic PADNC Hi- Pad Cell Library PADNC 3 of 4

44 Pad NoConnect Layout PADNC Hi- Pad Cell Library PADNC 4 of 4

45 Output Pad PADOUT Description: Output Pad with Buffer Library: MOSIS TSMC 035P Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples Schematic: S-Edit File: TannerLb\scmos\mTSMs035P.sdb Module: PADOUT Mask layout: L-Edit File: TannerLb\scmos\mTSMs035P.tdb Cell: PADOUT Mapping Macros: GateSim: TannerLb\nettran\scmos\scms2sim.mac L-Edit/SPR: TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table Capacitance DataOut PadOut_SCMOS Pad PAD D Height Width Area Equivalent Gate Drive 300 µ 90 µ µ 2 Logic Equation Pad = DataOut Delay Characteristics: T pd = 1.92ns T r = 1.48ns T f = 1.23ns Hi- Pad Cell Library PADOUT 1 of 4

46 Output Pad PADOUT This page is intentionally left blank. Hi- Pad Cell Library PADOUT 2 of 4

47 Output Pad Schematic PADOUT PadOut DataOut Pad PadBidirHE_SCMOS Hi- Pad Cell Library PADOUT 3 of 4

48 Output Pad Layout PADOUT Hi- Pad Cell Library PADOUT 4 of 4

49 Power Pad PADVDD Description: Power Pad Library: MOSIS TSMC 035P Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples Schematic: S-Edit File: TannerLb\scmos\mTSMs035P.sdb Module: PADVDD Mask layout: L-Edit File: TannerLb\scmos\mTSMs035P.tdb Cell: PADVDD Mapping Macros: GateSim: TannerLb\nettran\scmos\scms2sim.mac L-Edit/SPR: TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table Capacitance PadVdd Height Width Area Equivalent Gate Drive 300 µ 90 µ µ 2 Logic Equation Delay Characteristics: Hi- Pad Cell Library PADVDD 1 of 4

50 Power Pad PADVDD This page is intentionally left blank. Hi- Pad Cell Library PADVDD 2 of 4

51 Power Pad Schematic PADVDD PadVdd BONDING PAD Pad TN W='175*l' L='3*l' M=16 Hi- Pad Cell Library PADVDD 3 of 4

52 Power Pad Layout PADVDD Hi- Pad Cell Library PADVDD 4 of 4