Getting Started with Cadence Draft #3. Dan Kelly The School of Electrical and Electronic Engineering The University of Adelaide December 2, 2005

Transcription

1 Getting Started with Cadence Draft #3 Dan Kelly The School of Electrical and Electronic Engineering The University of Adelaide December 2,

2 1 Introduction This guide is intended to help people start using Cadence. It is not intended to be a comprehensive guide to use the tools themselves, but rather an informative outline on which tools are available and for what purpose. This guide is meant to make the introduction for the newcomer easier, and is specific to the University of Adelaide Department of Electrical and Electronic Engineering. Please freely distribute this document, and suggest changes, updates or improvements. The latest version of this document can be found on my EEE website 1. People are welcome to suggest or make changes. You can make corrections/improvements, etc. directly to the source (also available on the website), or by writing another document (.doc,.tex,.txt). I will update the changes as quickly as I can. I would like someone to write a short section on the JAS/JAZZ (spelling? library, including how to get started, available documentation, anything that would be handy to know, etc

3 Contents 1 Introduction 2 2 Useful commands and setup Starting up Licences Opening the Cadence documentation University software and licences Tutorials Synthesis in BuildGates Other tools Libraries Artisan 0.18µ technology JAS/JAZZ library Appendices Appendix A - University licenced tools

4 2 Useful commands and setup 2.1 Starting up First ssh into contact. You will get some weird messages otherwise. In a terminal window, type > ssh contact Source the cadence files > source /home/vlsi6/cadence/cadence_setup NB: A handy tip. To find the installation directory, after sourcing the Cadence files, type > instdir (It should be /home/vlsi6/cadence/ic/tools/dfii or /home/vlsi6/cadence/ic5141base.sun4v/to I always find it handy to type > setenv CADENCE_INSTALL /home/vlsi6/cadence/ic/tools/dfii 2.2 Licences You can check the state of the licence server or the number of available licences if you run into trouble opening a program. > lmstat To view the number of available licences for each program, > lmstat -a 2.3 Opening the Cadence documentation There are a number of tutorials you can do to familiarise yourself with Cadence. An introductory guide is available at crete.cadence.com. The tutorials have been copied and zipped. They can be accessed form the public network drive Edison\Users\Hooman\cadence. This is probably your P:\ if you are a Windows XP user. Specific tutorials are outlined later. There is specific documentation located in /home/vlsi6/cadence/ic/doc/ If you need to add netscape to the path so that you may view.html files opened by the the help viewer (CDSDoc), use > setenv PATH usr/local/bin:$path 4

5 CDSDoc is the help document browser for Cadence. It opens.html files located in the install directories for each tool. I have not been very successful using CDSDoc over a remote X session. The view is often not refreshed, and documents often fail to launch. I reccommend locating the documentation path via CDSDoc, then opening the files in netscape. To start CDSDoc: > cdsdoc & By default, CDSDoc wants to only open all windows in an open browser window. Change this. Open Edit Preferences. Click the New browser window radio buttons in the General and Search tabs. Click OK. Exit and restart CDSDoc. 5

6 Table 1: A list of Cadence tools for common tasks Task Cadence Tool Command Reference schematic composer Virtuoso layoutplus VHDL analysis ncvhdl/nclaunch ncvhdl ncvhdltut.pdf generate simulation snapshot ncelab ncvhdltut.pdf snapshot simulation ncsim ncvhdltut.pdf expand this University software and licences A list of all the tools the University has licences for is listed in table 1. Similarly, a list of all the tools that the University has a licence for is shown in table 2. To view this list yourself within cadence, from the Command Interpreter Window (CIW), simply look in Options License... If you need a CIW from the prompt, type > layoutplus & 6

7 Program Virtuoso Dracula Diva Assorted Table 2: Available licences Component Virtuoso-XL Layout Editor Compactor Layout Editor Turbo Schematic Editor Layout Synthesiser Layout Migrate EDIF 200 Reader EDIF 200 Writer Graphical User Interface Design Rule Checker (DRC) Layout Versus Schematic (LVS) Verifier Parasitic Extractor Switched Capacitor Layout Generators Cell Optimisation Option for Layout Synthesis Modulemaker Structure Compiler 3 Tutorials Much of the documentation found with Cadence is in the form of tutorials rather than manuals. Furthermore, some of the better ones are not even authored by Cadence! The command line help that I have used in programs so far is not descriptive. 3.1 Synthesis in BuildGates There is a tutorial for BuildGates from the University of Cincinnati provided with Cadence. It is based on a tutorial provided by Cadence. This is just a simple tute to get your feet wet. You may conduct the tutorial, being carefull to replace all their local references. Instances of /opt/cad/cadence/spr-4.0/buildgates/v4.0-s008 should read /home/vlsi6/cadence/spr50.sun4v/buildgates/v05.00-p008 for the installation within the UofA EEE department. Also note that in step 9(a) of the tutorial, Cammands Timing should read Report Timing. The University has a licence for BuildGates Extreme, which is the same as BuildGates, with the addition of datapath synthesis and low power synthesis. It does not have the placement, clock tree and global routing tools found in PKS. Instead of starting BuildGates Extreme with the ac shell command, start it with: > bgx_shell -gui & It can take quite some time to load... 7

8 8 Table 3: Help documents Topic File Location Simulation NCLaunch nclaunch.pdf /home/vlsi6/cadence/ius/doc/nclaunch/ NC-Vhdl, NC-Elab ncvhdl.pdf /home/vlsi6/cadence/ius/doc/ncvhdl/ LDV, NC-Launch ncvhdltut.vhdl /home/vlsi6/cadence/ius/doc/ncvhdl/ NC-Verilog ncvlog.pdf /home/vlsi6/cadence/ius/doc/ncvlog/ SimVision simvision.pdf /home/vlsi6/cadence/ius/doc/simvision/ Simvision Command Language simviscmdref.pdf /home/vlsi6/cadence/ius54/doc/simviscmdref/ Synthesis, PKS User Guide espks.pdf /home/vlsi6/cadence/spr/doc/espks/ Synthesis Place-&-Route Flow Guide SPRflow.pdf /home/vlsi6/cadence/spr/doc/sprflow/ Command Reference for Cadence PKS syncomref.pdf /home/vlsi6/cadence/spr50/doc/syncomref/ Place and Route SimVision User Guide simvision.pdf /home/vlsi6/cadence/ius/doc/simvision/ SimVision Command Language Reference simviscmdref.pdf /home/vlsi6/cadence/ius/doc/simviscmdref/ Silicon Ensemble Place & Route Reference silref.pdf /home/vlsi6/cadence/dsmse/doc/silref/ Other Tcl documentation

9 There is also a more complex version of the tutorial, which covers a bit more of the same thing. I have converted the original tutorial supplied by Cadence from postscript to PDF. It can be found in some/location It uses the same source files as the other tutorial form the University of Cincinatti. The Cadence tutorial is nt so good. MAn y of the names don t correspond, it appears to be written for an earlier version. You can get PDF versions of the Cadence tutorials for BuildGates here: some$\backslash$location 3.2 Other tools Expand me... 9

10 4 Libraries This section describes the available libraries for use locally with Cadence. 4.1 Artisan 0.18µ technology There is a digital VLSI library for use with MOSIS. To gain access you will need to contact Dr. Said Al-Sarawi or Kiet To. The library is located in the /home/vlsi5/cad/synopsys/artisan directory. There are different versions available. The useful files for the latest version is located in the.../artisan/tsmc18 sc 2004q3v1/aci/sc directory. There is a tutorial called the Synthesis, Place & Route Flow Guide for use with Cadence. Copy the file or use: > cd /home/vlsi5/cad/synopsys/artisan/tsmc18_sc_2004q3v1/aci/sc/alf > acroread SPRflow.pdf &. 4.2 JAS/JAZZ library To get access to this library you will need to contact Dr. Derek Abbott. Can someone expand this section, please? 10

11 5 Appendices 5.1 Appendix A - University licenced tools 1. VirtuosoCustom Design Platform The Virtuoso custom design platform is a comprehensive system for fast, silicon-accurate design and is optimized to support meet-in-the-middle design methodologies such as ACD. The Virtuoso platform includes the industrys only specification-driven environment; multi-mode simulation with common syntax, models, and equations; vastly accelerated layout; advanced silicon analysis for 0.13 microns and below; and a full-chip, mixed-signal integration environment. The Virtuoso platform is available on the Cadence CDBA database and the industry-standard OpenAccess database. With this platform, design teams can quickly design silicon that is right and on time at process geometries from 1 micron to 90 nanometers and beyond. (a) Virtuoso r Schematic Editor Virtuoso Schematic Editor, which is the design composition environment for the Virtuoso custom design platform, delivers an extensive set of tools for custom IC design entry. From architectural definition using industry-standard language representations, such as Verilog, VHDL, and C, to final structural implementations at the transistor level, Virtuoso Schematic Editor helps you implement each stage in your design. Virtuoso Schematic Editor accepts input in the formats EDIF netlist, Circuit design language (CDL), SPICE, VHDL IEEE , Verilog IEE1364 and OpenAccess data objects. The design output can be in any of the formats, EDIF netlist, CDL, SPICE, Cadence CDBA database and OpenAccess data objects. Benefits i. Easy visualization of large, complex designs using the hierarchy editor. ii. Early detection of design problems with built-in design and languagerule checking. iii. Rapid command execution with user-configurable bindkeys and menus. iv. 3x design entry speed via automatic wire routing. v. 2x speed in schematic visualization, access, and control. Features i. Fast and accurate design entry. ii. Design with industry-standard languages. iii. Extensive design checking capabilities. iv. Tight integration into the Virtuoso custom design platform. 11

12 (b) Virtuoso r Analog Design Environment Virtuoso Analog Design Environment is the analog design and simulation environment for the Virtuoso custom design platform. It is the industry s standard task-based environment for simulating and analyzing full-custom, analog, and RF IC designs. Virtuoso Analog Design Environment features a graphic user interface, integrated waveform display and analysis, distributed processing, and interfaces to popular third-party simulators. Virtuoso Analog Design Environment accepts input in the formats OpenAccess data objects, Circuit design language (CDL), Cadence CDBA database and SPICE. The design output can be in any of the formats, SPICE, PSF waveform, SST2 waveform and Cadence SKILL. Benefits i. Reduced learning curve with a simulator-independent environment. ii. Maximum efficiency in the script-driven mode. iii. Accelerated debug process using a variety of built-in analog analysis tools. iv. Facilitated design correction via easy comparison of pre- and post-parasitic extracted designs. v. Quick detection of circuit problems via a clear visualization cockpit. Features i. Easy-to-use interactive simulation environment. For example, it has the unique capability of interfacing with other commerciallyavailable and in-house simulators through the OASIS integrators kit. ii. Built-in waveform display and signal analysis capabilities. iii. Integral part of the Virtuoso custom design platform. (c) Virtuoso r -XL Layout Editor Virtuoso XL Layout Editor is the high-end custom block authoring physical layout tool of the Virtuoso custom design platform. It supports the physical implementation of custom digital, mixed-signal, and analog designs at the device, cell, and block levels. Virtuoso XL Layout Editor accepts inputs in the formats Cadence CDBA database, SKILL, STREAM, OpenAccess database, Virtuoso Schematic Editor, CDL, SPICE and Virtuoso Chip Assembly Router database. The design outputs can be in any of the formats Cadence CDBA database, SKILL, STREAM, OpenAccess database and Virtuoso Chip Assembly Router database. Benefits i. Accelerated block authoring through connectivity-driven features and flow (schematic or netlist) promotes a correct-by-construction LVS-correct layout to reduce verification iterations. 12

13 ii. Increased productivity and design quality with constraint- and design rule-driven features automatically ensure real-time design and process correctness. iii. Simplified, optimized device generation with the new menu-driven QuickCell feature of the standard SKILL programmable parameterized cells. iv. Efficiently planned, placed, and routed large block designs with custom floorplanning, automatic placement, and accelerated interactive routing features. Features i. Connectivity-driven functions and flow. ii. Constraint- and design rule-driven functions. iii. Accelerated layout automation. (d) Virtuoso r Spectre r Circuit Simulator Virtuoso Spectre Circuit Simulator provides fast, accurate simulations for tough analog and mixed-signal circuits. Tightly integrated with the Virtuoso custom design platform, Virtuoso Spectre technology provides detailed transistor-level analysis in multiple domains. Virtuoso Spectre Circuit Simulator inputs/output can be in any of the formats Virtuoso Spectre, HSPICE, SPICE 2/3, S-parameter data files and PSF waveform. Benefits i. High-performance, high-capacity SPICE-level simulations (3x SPICE). ii. Higher design quality using silicon-accurate device models shared within Virtuoso Multi-mode Simulation. iii. Better design accuracy using silicon-accurate models from the industry-leading Virtuoso advanced modelling tools. iv. Minimal translation to move between design domains with all simulators sharing the same syntax. Features i. Advanced circuit simulation techniques. ii. Built-in Verilog-A 2.0 behavioural modelling. iii. Advanced device modelling and support. (e) Virtuoso r Spectre r RF Simulation Option Virtuoso Spectre RF Simulation Option for Virtuoso Spectre Circuit Simulator provides fast, accurate simulations for RF and highfrequency ICs. Virtuoso Spectre RF works with Virtuoso Analog Design Environment to provide detailed, high-capacity analyses of RF and high-frequency designs. Virtuoso Spectre RF Simulation Option inputs/output can be in any of the formats Virtuoso Spectre, HSPICE, SPICE 2/3, S-parameter data files and PSF waveform. Benefits 13

14 i. High-performance simulation of thousands of RF transistors. ii. Maximum design productivity with advanced algorithms and RF-oriented analyses that converges quickly on highly non-linear circuits. iii. Minimal design translation due to shared syntax across all Virtuoso multi-mode simulators. iv. Consistent silicon accuracy maintained within Virtuoso Multimode Simulation with shared device models among all the simulators. Features i. Advanced simulation techniques. ii. Physical component modelling. iii. RF package modelling. (f) Virtuoso r Spectre r RF Simulation Option Virtuoso AMS Designer Simulator is a mixed-signal simulation solution for the design and verification of the largest and most complex mixed-signal SoCs. It is integrated in and fully compatible with both the Virtuoso custom design platform and the Incisive functional verification platform. Virtuoso AMS Designer Simulator inputs are in the formats Cadence CDBA database (or OpenAccess database), Verilog-AMS 2.0, VHDL-AMS , Verilog (IEEE , majority of IEEE extensions), VHDL (IEEE , IEEE , IEEE (VITAL 2000)), Spectre, Spice2G6 and HSPICE. The outputs can be in any of the formats SST2 waveform (analog and digital), PSF waveform (analog) and Verilog-AMS netlist. Benefits i. Assured design quality using proven Virtuoso and Incisive simulation technology. ii. Easy adoption with supports for both top-down and bottom-up design styles. iii. Fast detection of design failures early in the design phase to make sure the design is ready for tapeout right on time. iv. Accelerated simulation with mixed-signal behavioral language support. Features i. Facilitates the meet-in-the-middle design methodology. ii. Incorporates proven Virtuoso and incisive simulation technology. (g) Diva r Physical Verification and Extraction Suit Diva Physical Verification is part of the design verification suite of tools within the Virtuoso custom design platform. It provides realtime physical verification of cells, blocks, and small IC designs. With 14

15 strong interactivity for identifying and correcting layout errors, Diva physical verification is ideal for hand-crafting custom designs. Diva Physical Verification design inputs are in the formats Cadence CDBA database (DFII) and Diva rules. The design outputs can be in any of the formats Cadence CDBA database (DFII) (layout and extracted), Error markers and Textual reports for debugging and archival purposes. Benefits i. Simplifies the design process with a common database for data transfer with the Virtuoso custom design platform. ii. Provides a robust interactive physical verification flow for custom designs. iii. Accelerates design-to-volume with a production-proven interactive physical verification tool suite. iv. Reduces re-spins by eliminating design layout errors before tapeout. Features i. Interactive verification. ii. Diva design rule checker (DRC). iii. Diva layout vs. schematic (LVS) verifier. iv. Diva parasitic extractor (RCX), which allows design teams to provide the layers, coefficients, bend factors, and other necessary criteria in equations that will perform parasitic resistance and capacitance calculations. An extracted resistance network containing associated distributed capacitance is formed. During the network reduction phase, the values of capacitance are consolidated and associated with each final resistor. This RC pair or group may be represented in a pi or T formation. All parasitic devices are graphically displayed including the values measured for each resistor and capacitor. This RC network is combined with the circuit netlist to form a final netlist containing designed and parasitic devices. The final netlist can then be simulated with SPICE, Virtuoso Spectre Circuit Simulator, or other similar simulators to determine the exact electrical performance of the layout. Diva RCX includes a threebody/twodimensional (charge-sharing) capacitance extraction capability, providing higher extraction accuracy. 2. Dracula r Verification Dracula Verification products are an established IC industry standard. You can trust Dracula to provide comprehensive and accurate sign-off verification results for all designs. This technology provides you with a complete set of verification tools suitable for small cells up to very large ICs. Dracula verification tools can be used no matter what your design 15

16 methodology is bottom-up, custom, standard-cell, structured gate array, or block-oriented. Dracula has produced industry-wide trusted results for over a decade. (a) Dracula r Graphical User Interface Dracula Graphical User Interface (GUI), an interactive error debugging and analysis tool, assists in the identification, analysis, and correction of layout errors by displaying the original design layers merged with the systems verification error data in a single window. Debugging and analyzing errors can account for up to 80% of the verification cycle time, but this debugging environment speeds the error correction process by providing online access to verification error information, along with node and device connectivity data. Benefits and Features i. Automatic step through feature graphically identifies and analyzes DRC and LVS errors from within the Virtuoso environment. ii. Error analysis and correction takes place in the original Cadence Design Framework II database when used with Virtuoso Schematic Composer and Virtuoso Layout Editor. iii. Interactive traversal of circuit netlist allows the display of multiple views of network hierarchy. iv. Parasitic viewing enables detailed graphical analysis of RC elements in the layout and specific to critical nets. v. Graphical cross-probing between netlist, schematic, and layout windows reduces time spent debugging LVS discrepancies. vi. Interactive short locator rapidly identifies and isolates short circuits in the layout. vii. Visual access to connectivity, device, and nodal information helps debug layout errors quickly. (b) Dracula r Physical Verification and Extraction Suit In addition to basic verification functionality, Dracula provides you with a complete set of verification tools suitable for all designs, from small cells to very large ICs. Dracula Design Rule Checker (DRC) is an integral component of this physical verification system. It performs checks on layout geometries, gives confidence that the layout can be manufactured, and offers high yields for a given IC process technology. Dracula Electrical Rule Checker (ERC) checks your layout for electrical rule violations such as open circuits, short circuits, and floating nodes. This tool also detects invalid devices and improper implant types, substrate bias, power connections, and ground connections. It eliminates the time consuming process of finding shorts between global signals by isolating the location at which a short occurs. This checker catches gross electrical mistakes on the layout and gives the 16

17 designer the confidence that the chip will work the first time. Parasitic elements have a significant impact on performance in todays high speed IC designs. With the smaller geometries of leading-edge processes, delays caused by interconnect are becoming increasingly dominant over gate propagation delays. Dracula Layout versus Schematic (LVS) is used to identify device or network discrepancies between the layout and schematic. Use of this verifier during the IC design process guarantees that the circuit in the mask layout matches the schematic description. It can also be used to identify discrepancies between two similar representations layout vs. layout (LVL) or schematic vs. schematic (SVS). This tool isolates discrepancies between the two representations of the design and clearly reports the differences for analysis. Using this verifier has resulted in tens of thousands of working semiconductors on the first iteration with considerable savings in processing costs. Dracula Parasitic Extraction (RCX) extracts parasitic devices from the integrated circuit layout for input to any circuit simulation. It can dramatically increase the probability of delivering first pass silicon that meets performance criteria. 3. IncisiveFunctional Verification Platform The challenges facing verification teams have grown in parallel with the size and complexity of chips and embedded software. Dealing with today s multimillion-gate designsand the inefficiencies of multiple, unrelated toolsetsyou struggle to squeeze in enough cycles to provide reasonable assurance that functional bugs will not surface in silicon. To effectively verify highly complex digital, SoC, and mixed-signal ICs requires replacing the current fragmented process with a new-generation approach that unifies tools, standards, and methodologies. And, to avoid putting your design schedules at risk, you need an approach you can phase in over time. The Incisive platform employs a single-kernel architecture that overcomes fragmentation by unifying multiple verification techniques around a single engine. It natively supports Verilog, VHDL, SystemC, PSL/OVL, SystemVerilog and analog/mixed-signal verification. The same platform delivers Acceleration-on-Demand, transaction-level support, HDL analysis (linting), coverage, debug and analysis, and test generation. Not only is Incisive designed so you can adopt these technologies incrementally, but it can also deliver the speed and efficiency required to compress overall verification time by as much as 50 percent. (a) Incisive Unified Simulator The Cadence Incisive Unified Simulator, part of the Incisive platform, provides everything you need to verify today s toughest designs. Its single-kernel architecture natively supports Verilog, VHDL, SystemC, SystemC Verification library (SCV), and PSL/Sugar assertions. Incisive includes a comprehensive verification environment including full transaction-level sup- 17

18 port and unified test generation. You can extend Incisive with other elements of the Incisive platform including Acceleration-on-Demand with Incisive XLD, analog/mixed signal/rf verification using Incisive AMS, and algorithm development and verification using Incisive SPW. Benefits i. Offers the ultimate simulation-based speed and efficiency. ii. Provides 100x RTL performance through native transaction-level simulation. iii. Reduces testbench development up to 50% with transactionlevel support, unified test generation, and verification component reuse. iv. Decreases debug time up to 25% through unified transaction/signal viewing, native assertion support, and unified debug environment for all languages. v. Increases RTL performance by 100x with optional Accelerationon-Demand. Features i. Heterogeneous single-kernel architecture. ii. Unified simulation and debug environments. iii. Integrated transaction environment. iv. Dynamic assertion support. v. Native PSL/Sugar assertion and OVL support. vi. Optional acceleration-on-demand. vii. HDL analysis. viii. Comprehensive coverage. ix. Optional mixed-signal and algorithm design. Simulation i. Verilog (IEEE , majority of IEEE extensions). ii. VHDL (IEEE , IEEE , IEEE (VITAL 2000)). iii. SystemC (OSCI SystemC v2.01). iv. SystemC verification library (OSCI SCV 1.0). 4. BuildGates r Synthesis The Cadence BuildGates synthesis tool delivers dramatic performance and productivity benefits over conventional synthesis tools, yielding superior quality of results with less manual intervention. This is why leading IC design companies and silicon vendors have rapidly adopted it as their synthesis tool of choice for fully exploiting silicon process technology advances. The high-capacity BuildGates database allows synthesis of more of 18

19 the design at once, while its fast runtime assures rapid turnaround, making chip-level synthesis practical. Generally, quality of results improve when more of the design is synthesized at once. The tool has a larger solution space and fulldesign visibility to freely propagate constants and trade off timing across multiple blocks. The result is improved quality of results over bottom-up synthesis, enabled through high capacity and performance. Benefits and Features (a) RTL block synthesis capacity in excess of 1 million gates. (b) Integrated sign-off static timing analysis (STA). (c) STA capacity in excess of 20 million gates. (d) Automatic time budgeting. (e) Integrated scan insertion and design for test (DFT) rule checking. (f) Built-in distributed synthesis capability. (g) Full interface capability to Cadence and other place-and-route tools. (h) Support for new Verilog 2001constructs. (i) TCL scripting; TCL/Tk GUI. 19