Cadence/EURORPACTICE 2011/2012 Release. IC Package. Cadence Advanced Encryption Standard-64bit
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1 Cadence/EURORPACTICE 2011/2012 Release IC Package Encryption Cadence Advanced Encryption Standard-64bit ALTOS 3.1 ALTOS 3.1 Liberate Server Liberate Client ASSURA 4.1 ASSURA 4.1 ASSURA 4.1 Assura(TM) Design Rule Checker Assura(TM) Layout Vs. Schematic Verifier Assura(TM) Multiprocessor Option CCD 10.1 CCD 10.1 Encounter (R) Conformal Constraint Designer - XL CCD Multi-Constraint Check Option CONFRML 10.1 CONFRML 10.1 Encounter Conformal Low Power - GXL Encounter Conformal ECO Designer - GXL CTOS 11.1 C-to-Silicon Compiler - L EDI 10.1 Encounter Low Power GXL Option Licence only EDI 10.1 Encounter Mixed Signal GXL Option Licence only EDI 10.1 Encounter Digital Implementation System XL EDI 10.1 Encounter Advanced Node GXL Option Licence only ET 10.1 Encounter Diagnostics Basic licence only ET 10.1 Option to RC - DFT Architect Advanced ET 10.1 Encounter True Time ATPG Advanced ETS 10.1 Encounter Library Characterizer - GXL
2 ETS 10.1 Encounter Power System XL ETS 10.1 EPS Advanced Analysis GXL Option Licence only ETS 10.1 Encounter Timing System-XL ETS 10.1 ETS Advanced Analysis GXL Option Licence only EXT 10.1 EXT 10.1 EXT 10.1 Cadence QRC Extraction - XL Cadence QRC Advanced Analysis GXL Option Cadence QRC Advanced Modeling GXL Option MVS 10.1 RC 10.1 RC 10.1 Encounter DFM GXL Option Encounter RTL Compiler - GXL option Encounter RTL Compiler with physical Virtuoso(R)-XL Layout Editor Virtuoso(R) Electronic Design for Manufacturability Option Virtuoso(R) Schematic Editor Virtuoso(R) Analog Design Environment Virtuoso(R) Analog VoltageStorm Option Virtuoso(R) Analog ElectronStorm Option Cadence(R) Design Framework II Cadence(R) Design Framework Integrator's Toolkit +64-bit Virtuoso(R) Simulation Environment Virtuoso(R) Schematic VHDL Interface Virtuoso(R) Schematic Editor Verilog(R) Interface Virtuoso(R) Schematic Editor HSPICE Interface Virtuoso(R) Analog Oasis Run-Time Option Cadence(R) OASIS for RFDE Virtuoso(R) Analog HSPICE Interface Option
3 Virtuoso(R) Chip Assembly Router Virtuoso(R) Layout Migrate Virtuoso(R) AMS Designer Environment Dracula(R) Design Rule Checker +64-bit Dracula(R) Layout Vs. Schematic Verifier +64-bit Dracula(R) Parasitic Extractor +64-bit Diva(R) Design Rule Checker +64-bit Diva(R) Layout Vs. Schematic Verifier +64-bit Diva(R) Parasitic Extractor Cadence(R) SKILL Development Environment Virtuoso(R) EDIF 200 Reader Virtuoso(R) EDIF 200 Writer Virtuoso(R) Schematic Editor XL Virtuoso(R) Analog Design Environment - GXL Virtuoso(R) Visualization & Analysis XL Virtuoso(R) Layout Suite XL +64-bit Layout Suite L Virtuoso(R) Layout Suite - GXL 2 per seat Virtuoso Constraint API Run-Time Option Virtuoso(R) Power System XL INCISIV10.2 Incisive Formal Verifier INCISIV10.2 Verifault(R)-XL simulator INCISIV10.2 Cadence(R) Export Model Packager Licence only INCISIV10.2 Incisive Enterprise Simulator - XL INCISIV10.2 Digital Mixed Signal Option to IES Licence only INCISIV10.2 Incisive Advanced Option Licence only INCISIV10.2 AMS Designer with Flexible Analog Simulation INCISIV10.2 Virtuoso AMS Designer Verification Option Licence only INCISIV10.2 Incisive Enterprise Manager INCISIV10.2 Incisive Enterprise Verifier - XL
4 INCISIV10.2 Incisive Software Extensions Licence only KQV 5.1 Cadence(R) QuickView Layout and Mask Data Viewer MMSIM 10.1 Virtuoso(R) Spectre Model Interface Option MMSIM 10.1 Virtuoso(R) RelXpert MMSIM 10.1 Virtuoso Multi-mode Simulation with AP Simulator 2 per seat Cadence(R) Physical Verification System Design Rule Checker XL Cadence(R) Physical Verification System Layout vs. Schematic Checker XL Cadence(R) Physical Verification System Programmable Electrical Rules Checker Cadence(R) Physical Verification System Graphic LVS Debugger Cadence(R) Physical Verification System Interactive Short Locator Option VIPCAT 11.3 SOC Portfolio VIPCAT 11.3 Memory Model Portfolio VIPCAT 11.3 VIP OCP 3.0 UVC VIPCAT 11.3 VIP MIPI SLIMbus UVC VIPCAT 11.3 VIP SATA 6G (Gen3) PureSpec VIPCAT 11.3 VIP PCI Express 3.0 PureSpec VIPCAT 11.3 VIP USB 3.0 PureSpec VIPCAT 11.3 VIP HDMI 1.4 UVC VIPCAT 11.3 VIP MR-IOV PureSpec VIPCAT 11.3 Memory Model for Flash ONFi 3 VIPCAT 11.3 Memory Model for Flash PPN DDR VIPCAT 11.3 Memory Model for Flash Toggle NAND 2 VIPCAT 11.3 Memory Model for GDDR5 VIPCAT 11.3 Memory Model for LRDIMM VIPCAT 11.3 PureView VIPCAT 11.3 VIP PCI Express 1.1 & 2.0 PureSuite
5 Systems Package INCISIV10.2 Incisive Formal Verifier INCISIV10.2 Verifault(R)-XL simulator INCISIV10.2 Cadence(R) Export Model Packager Licence only INCISIV10.2 Incisive Enterprise Simulator - XL INCISIV10.2 Digital Mixed Signal Option to IES Licence only INCISIV10.2 Incisive Advanced Option Licence only INCISIV10.2 AMS Designer with Flexible Analog Simulation INCISIV10.2 Virtuoso AMS Designer Verification Option Licence only INCISIV10.2 Incisive Enterprise Manager INCISIV10.2 Incisive Enterprise Verifier - XL INCISIV10.2 Incisive Software Extensions Licence only Cadence(R) SKILL Development Environment Allegro Design Authoring High-Speed Option Allegro Design Authoring Multi-Style Option Allegro(R) Design Authoring Team Design Option Allegro PCB Designer Allegro PCB High-Speed Option Allegro PCB Miniaturization Option Allegro(R) PCB Team Design Option Allegro(R) PCB Analog/RF Option Allegro PCB Interconnect Feasibility Option - XL Allegro PCB Global Route Environment Option - XL Allegro PCB Power Delivery Network Analysis Allegro PCB SI Multi-Gigabit Option Cadence 3D Design Viewer Allegro(R) ASIC Prototyping with FPGA's Allegro(R) Design Authoring Allegro(R) AMS Simulator
6 Allegro(R) Router Auto/Interactive option - L Allegro(R) PCB SI - XL Allegro(R) PCB Librarian Allegro(R) Physical Viewer Cadence SiP Digital SI XL Cadence SiP Layout - XL VIPCAT 11.3 SOC Portfolio VIPCAT 11.3 Memory Model Portfolio VIPCAT 11.3 VIP OCP 3.0 UVC VIPCAT 11.3 VIP MIPI SLIMbus UVC VIPCAT 11.3 VIP SATA 6G (Gen3) PureSpec VIPCAT 11.3 VIP PCI Express 3.0 PureSpec VIPCAT 11.3 VIP USB 3.0 PureSpec VIPCAT 11.3 VIP HDMI 1.4 UVC VIPCAT 11.3 VIP MR-IOV PureSpec VIPCAT 11.3 Memory Model for Flash ONFi 3 VIPCAT 11.3 Memory Model for Flash PPN DDR VIPCAT 11.3 Memory Model for Flash Toggle NAND 2 VIPCAT 11.3 Memory Model for GDDR5 VIPCAT 11.3 Memory Model for LRDIMM VIPCAT 11.3 PureView VIPCAT 11.3 VIP PCI Express 1.1 & 2.0 PureSuite Combined IC & Systems Package Encryption Cadence Advanced Encryption Standard-64bit ALTOS 3.1 ALTOS 3.1 Liberate Server Liberate Client
7 ASSURA 4.1 ASSURA 4.1 ASSURA 4.1 Assura(TM) Design Rule Checker Assura(TM) Layout Vs. Schematic Verifier Assura(TM) Multiprocessor Option CCD 10.1 CCD 10.1 Encounter (R) Conformal Constraint Designer - XL CCD Multi-Constraint Check Option CONFRML 10.1 CONFRML 10.1 Encounter Conformal Low Power - GXL Encounter Conformal ECO Designer - GXL CTOS 11.1 C-to-Silicon Compiler - L EDI 10.1 Encounter Low Power GXL Option Licence only EDI 10.1 Encounter Mixed Signal GXL Option Licence only EDI 10.1 Encounter Digital Implementation System XL EDI 10.1 Encounter Advanced Node GXL Option Licence only ET 10.1 Encounter Diagnostics Basic licence only ET 10.1 Option to RC - DFT Architect Advanced ET 10.1 Encounter True Time ATPG Advanced ETS 10.1 Encounter Library Characterizer - GXL ETS 10.1 Encounter Power System XL ETS 10.1 EPS Advanced Analysis GXL Option Licence only ETS 10.1 Encounter Timing System-XL ETS 10.1 ETS Advanced Analysis GXL Option Licence only EXT 10.1 EXT 10.1 Cadence QRC Extraction - XL Cadence QRC Advanced Analysis GXL Option
8 EXT 10.1 Cadence QRC Advanced Modeling GXL Option MVS 10.1 RC 10.1 RC 10.1 Encounter DFM GXL Option Encounter RTL Compiler - GXL option Encounter RTL Compiler with physical Virtuoso(R)-XL Layout Editor Virtuoso(R) Electronic Design for Manufacturability Option Virtuoso(R) Schematic Editor Virtuoso(R) Analog Design Environment Virtuoso(R) Analog VoltageStorm Option Virtuoso(R) Analog ElectronStorm Option Cadence(R) Design Framework II Cadence(R) Design Framework Integrator's Toolkit +64-bit Virtuoso(R) Simulation Environment Virtuoso(R) Schematic VHDL Interface Virtuoso(R) Schematic Editor Verilog(R) Interface Virtuoso(R) Schematic Editor HSPICE Interface Virtuoso(R) Analog Oasis Run-Time Option Cadence(R) OASIS for RFDE Virtuoso(R) Analog HSPICE Interface Option Virtuoso(R) Chip Assembly Router Virtuoso(R) Layout Migrate Virtuoso(R) AMS Designer Environment Dracula(R) Design Rule Checker +64-bit Dracula(R) Layout Vs. Schematic Verifier +64-bit Dracula(R) Parasitic Extractor +64-bit Diva(R) Design Rule Checker +64-bit
9 Diva(R) Layout Vs. Schematic Verifier +64-bit Diva(R) Parasitic Extractor Cadence(R) SKILL Development Environment Virtuoso(R) EDIF 200 Reader Virtuoso(R) EDIF 200 Writer Virtuoso(R) Schematic Editor XL Virtuoso(R) Analog Design Environment - GXL Virtuoso(R) Visualization & Analysis XL Virtuoso(R) Layout Suite XL +64-bit Layout Suite L Virtuoso(R) Layout Suite - GXL 2 per seat Virtuoso Constraint API Run-Time Option Virtuoso(R) Power System XL INCISIV10.2 Incisive Formal Verifier INCISIV10.2 Verifault(R)-XL simulator INCISIV10.2 Cadence(R) Export Model Packager Licence only INCISIV10.2 Incisive Enterprise Simulator - XL INCISIV10.2 Digital Mixed Signal Option to IES Licence only INCISIV10.2 Incisive Advanced Option Licence only INCISIV10.2 AMS Designer with Flexible Analog Simulation INCISIV10.2 Virtuoso AMS Designer Verification Option Licence only INCISIV10.2 Incisive Enterprise Manager INCISIV10.2 Incisive Enterprise Verifier - XL INCISIV10.2 Incisive Software Extensions Licence only KQV 5.1 Cadence(R) QuickView Layout and Mask Data Viewer MMSIM 10.1 Virtuoso(R) Spectre Model Interface Option MMSIM 10.1 Virtuoso(R) RelXpert MMSIM 10.1 Virtuoso Multi-mode Simulation with AP Simulator 2 per seat
10 Cadence(R) Physical Verification System Design Rule Checker XL Cadence(R) Physical Verification System Layout vs. Schematic Checker XL Cadence(R) Physical Verification System Programmable Electrical Rules Checker Cadence(R) Physical Verification System Graphic LVS Debugger Cadence(R) Physical Verification System Interactive Short Locator Option VIPCAT 11.3 SOC Portfolio VIPCAT 11.3 Memory Model Portfolio VIPCAT 11.3 VIP OCP 3.0 UVC VIPCAT 11.3 VIP MIPI SLIMbus UVC VIPCAT 11.3 VIP SATA 6G (Gen3) PureSpec VIPCAT 11.3 VIP PCI Express 3.0 PureSpec VIPCAT 11.3 VIP USB 3.0 PureSpec VIPCAT 11.3 VIP HDMI 1.4 UVC VIPCAT 11.3 VIP MR-IOV PureSpec VIPCAT 11.3 Memory Model for Flash ONFi 3 VIPCAT 11.3 Memory Model for Flash PPN DDR VIPCAT 11.3 Memory Model for Flash Toggle NAND 2 VIPCAT 11.3 Memory Model for GDDR5 VIPCAT 11.3 Memory Model for LRDIMM VIPCAT 11.3 PureView VIPCAT 11.3 VIP PCI Express 1.1 & 2.0 PureSuite Cadence(R) SKILL Development Environment Allegro Design Authoring High-Speed Option Allegro Design Authoring Multi-Style Option Allegro(R) Design Authoring Team Design Option Allegro PCB Designer Allegro PCB High-Speed Option
11 Allegro PCB Miniaturization Option Allegro(R) PCB Team Design Option Allegro(R) PCB Analog/RF Option Allegro PCB Interconnect Feasibility Option - XL Allegro PCB Global Route Environment Option - XL Allegro PCB Power Delivery Network Analysis Allegro PCB SI Multi-Gigabit Option Cadence 3D Design Viewer Allegro(R) ASIC Prototyping with FPGA's Allegro(R) Design Authoring Allegro(R) AMS Simulator Allegro(R) Router Auto/Interactive option - L Allegro(R) PCB SI - XL Allegro(R) PCB Librarian Allegro(R) Physical Viewer Cadence SiP Digital SI XL Cadence SiP Layout - XL PCB Studio Package Allegro(R) Design Entry CIS Allegro(R) AMS Simulator Allegro PCB Designer Allegro(R) PCB SI - XL Allegro 2 FPGA System Planner Option TLM Package Encryption Cadence Advanced Encryption Standard-64bit
12 CCD 10.1 CCD 10.1 Encounter (R) Conformal Constraint Designer - XL CCD Multi-Constraint Check Option CONFRML 10.1 Encounter Conformal Low Power - GXL CTOS 11.1 C-to-Silicon Compiler - L INCISIV10.2 Incisive Formal Verifier INCISIV10.2 Verifault(R)-XL simulator INCISIV10.2 Cadence(R) Export Model Packager Licence only INCISIV10.2 Incisive Enterprise Simulator - XL INCISIV10.2 Incisive Advanced Option Licence only INCISIV10.2 Incisive Enterprise Manager INCISIV10.2 Incisive Enterprise Verifier - XL INCISIV10.2 Incisive Software Extensions Licence only INCISIV10.2 Cadence System Creator - L INCISIV10.2 Cadence Software Developer RC 10.1 Encounter RTL Compiler - GXL option VIPCAT 11.3 SOC Portfolio VIPCAT 11.3 Memory Model Portfolio VIPCAT 11.3 VIP OCP 3.0 UVC VIPCAT 11.3 VIP MIPI SLIMbus UVC VIPCAT 11.3 VIP SATA 6G (Gen3) PureSpec VIPCAT 11.3 VIP PCI Express 3.0 PureSpec VIPCAT 11.3 VIP USB 3.0 PureSpec VIPCAT 11.3 VIP HDMI 1.4 UVC VIPCAT 11.3 VIP MR-IOV PureSpec VIPCAT 11.3 Memory Model for Flash ONFi 3
13 VIPCAT 11.3 Memory Model for Flash PPN DDR VIPCAT 11.3 Memory Model for Flash Toggle NAND 2 VIPCAT 11.3 Memory Model for GDDR5 VIPCAT 11.3 Memory Model for LRDIMM VIPCAT 11.3 PureView VIPCAT 11.3 VIP PCI Express 1.1 & 2.0 PureSuite System in Package Option Cadence SiP Digital Architect - GXL Virtuoso SiP Architect XL Cadence Chip Integration Option InCyte Chip Estimator Option CICE 4.2 Cadence InCyte Chip Estimator XL (Bundle of 5 Logins - no license) Manufacturability Verification System Option MVS 10.1 Litho Physical Analyzer MVS 10.1 Distributed Process for 8 CPUs 3 per seat
Europractice Cadence release. IC Package ASSURA 4.1 ASSURA 4.1 ASSURA 4.1
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