POWR IP PZ1/17
|
|
- Nathan Fisher
- 5 years ago
- Views:
Transcription
1 Silesian University of Technology as Centre of Modern Education Based on Research and Innovations POWR IP PZ1/17 Project co-financed by the European Union under the European Social Fund Course title: Digital Circuits Theory (DCT) Faculty of Automatic Control, Electronics and Computer Science, Institute of Informatics Field of study: Informatics Stationary first degree studies
2 Functions for auxiliary input combinational circuit Comparison of functions depending on the variables selected as root (base) Functions for input combinational circuit when the variables driving MUX are Functions for input combinational circuit when the variables driving MUX are 45
3 Functions for auxiliary input combinational circuit Matrix method allows to obtain functions for inputs addressed by any selected variables (selection does not have to be optimal) Selection of variables regardless of numbers of don t care conditions 46
4 Functions for auxiliary input combinational circuit Matrix method expansion of rows with don t care conditions For all don t care conditions on selected variables we repeat the row in the matrix, substituting don t cares with all possible combinations of values of variables 47
5 Functions for auxiliary input combinational circuit Matrix method ordering and reduction of rows leading to don t care conditions Ordering and grouping Covering Reduction of rows 48
6 Functions for auxiliary input combinational circuit Matrix method resulting functions The same as previously obtained by algebraic transformations 49
7 Properties of commutators Commutators and hazards Definitions and structures by canonical forms MUX DDMUX All minterms (or maxterms) implemented independently Consequences for all transitions between logically adjacent states there are static hazards 50
8 Implementations with Demultiplexers Multi-output functions enabled by added gates Example: Translator from Gray code into natural binary code on 4 bits Logic diagram Definitions of functions corresponding to this implementation Z 3 =x 3 Z 2 =Σ(4,5,6,7,8,9,10,11)x 3 x 2 x 1 x 0 Z 1 =Σ(2,3,4,5,8,9,14,15)x 3 x 2 x 1 x 0 Z 0 =Σ(1,2,4,7,8,11,13,14)x 3 x 2 x 1 x 0 51
9 Implementations with Demultiplexers Choice of the implemented form of a function For balanced functions can be dictated by available gates For imbalanced functions this form is chosen that requires smaller gate (with fewer inputs) Example Function to implement yz x Fewer zeros than ones, so PoS form is selected over SoP form Logic diagram Definition corresponding to this implementation F=Π(0,3,7)xyz 52
10 Implementations with Demultiplexers Implementation of incompletely specified functions Once the circuit is constructed, it is not possible to recognise combinations for which the output is specified from those unspecified Example Function to implement yz x Logic diagram Fewer ones than zeros, so SoP form is selected over PoS form Definition of the function corresponding to this implementation F=Σ(0,3,6)xyz 53
11 Implementations with Multiplexers Each MUX can implemented only one function Example: Translator from Gray code into natural binary code on 4 bits Logic diagram Definitions of functions corresponding to this implementation Z 3 =x 3 Z 2 =Σ(1,2)Z 3 x 2 Z 1 =Σ(1,2)Z 2 x 1 Z 0 =Σ(1,2)Z 1 x 0 54
12 Implementations with Multiplexers Implementation of incompletely specified functions Information inputs corresponding to combinations for which the output is unspecified can be left unconnected (then the answer depends on implementation technology) Example Function to implement yz x Logic diagram Definition of the function corresponding to this implementation F=Σ(0,3,6(5))xyz 55
13 Specific implementations Example yz wx Function to implement is of 4 variables, so in regular implementation would require 16-bit commutators, and then the definition would be given as F=Σ(1,4,8,13)wxyz 10 1 On the other hand, we can decompose the function = = =,, =,, =+(,,) G=Σ(1,2,4,7)wxz 56
14 Specific implementations Example (cont.) Decomposed function =+(,,) G=Σ(1,2,4,7)wxz Logic diagrams With addition of gates, 8-bit commutators are sufficient for implementation of the function 57
15 LECTURE10 58
16 Iterative circuits Problems to be solved by building structures that consist of repetitively, iterativelyused blocks In the structure there can be distinguished some number of identical sub-circuits, cells The number of inputs (cells) is either unspecified, or likely to change Design of an iterative or cascade circuit Cascade can work in one direction or in both 59
17 General structure of a single direction iterative circuit 60
18 A typical cell of an iterative circuit The specific number of variables used to carry messages between cells depends on the number of these messages A typical cell that is designed, works as a general template, adapted to requirements of each cell in a cascade. Boundary cells are often degenerate. 61
19 Standard design procedure 1. Identify inputs and outputs of a typical cell 2. Define clearly messages to be passed between cells (by carry) 3. Define symbolic maps for outputs from the typical cell 4. Encode listed messages with sufficient number of binary variables 5. Obtain binary maps for outputs from the typical cell 6. Set boundary conditions in their symbolic and binary forms 7. Obtain appropriate implementation-dependent forms for switching functions describing the typical cell 8. Implement the typical cell (or boundary cells, or the complete circuit) 62
20 Example Design a circuit which on the output Y sets 1 when on its four inputs there is a single 1 or two 1 s Standard processing for a combinational circuit 1. Construct a truth table since a circuit is relatively simple we can directly construct Karnaugh map 63
21 Example 2. Find such form of description that corresponds to intended implementation for implementation with gates we need minimal either SoP or PoS form If we need to change the number of inputs to the circuits, we start designing all over again! 64
22 Approach of iterative circuits Re-formulate circuit description Design a circuit which on the output Y i sets 1 when on inputs from 0 to i there is a single 1 or two 1 s Start designing an iterative circuit 1. A typical cell For this specific circuit, if constructed in the complete structure, there is needed only one output, from the last cell 65
23 Approach of iterative circuits 2. Definition of messages passed with carry on inputs there are no 1 s on inputs there is one 1 on inputs there are two 1 s on inputs there are more than two 1 s The number of messages is problem-dependent. We need as many as are necessary and sufficient to pass on relevant information. They need to exhaust all logically possible situations, and always only one choice of message is possible basing on current circuit knowledge. Messages are based on knowledge about preceding cells, and references to inputs of i-th cell would be wrong. 66
24 Approach of iterative circuits 3. Symbolic maps for output and carry 4. Encoding of symbolic messages Can be natural binary, by Gray code, or more optimisation-oriented. In this example, natural binary encoding is applied. 67
25 Approach of iterative circuits 5. Binary Karnaugh maps for output and carry 6. Boundary conditions 68
26 Approach of iterative circuits 7. Expressions for output and carry The form of obtained equations reminds recursive procedures or functions in programming. Without boundary conditions (or with wrong conditions) the whole circuit cannot work correctly. 69
27 Approach of iterative circuits 8. Implementation For Cell 0 we have: Inputs: Outputs: For Cell 1 we have: Inputs: Outputs: For Cell 2 we have: Inputs: Outputs: For Cell 3 we have: Inputs: Outputs: If we perform calculations for all cells, substituting correct inputs, transforming accordingly with laws of Boolean algebra, as a result the final formula for the output from the circuit corresponds to the one obtained before, for the circuit designed as a regular combinational circuit 70
Combinational Logic Circuits
Chapter 3 Combinational Logic Circuits 12 Hours 24 Marks 3.1 Standard representation for logical functions Boolean expressions / logic expressions / logical functions are expressed in terms of logical
More informationDKT 122/3 DIGITAL SYSTEM 1
Company LOGO DKT 122/3 DIGITAL SYSTEM 1 BOOLEAN ALGEBRA (PART 2) Boolean Algebra Contents Boolean Operations & Expression Laws & Rules of Boolean algebra DeMorgan s Theorems Boolean analysis of logic circuits
More informationChapter 2. Boolean Expressions:
Chapter 2 Boolean Expressions: A Boolean expression or a function is an expression which consists of binary variables joined by the Boolean connectives AND and OR along with NOT operation. Any Boolean
More informationCprE 281: Digital Logic
CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Minimization CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev Administrative
More informationKarnaugh Map (K-Map) Karnaugh Map. Karnaugh Map Examples. Ch. 2.4 Ch. 2.5 Simplification using K-map
Karnaugh Map (K-Map) Ch. 2.4 Ch. 2.5 Simplification using K-map A graphical map method to simplify Boolean function up to 6 variables A diagram made up of squares Each square represents one minterm (or
More informationDigital Logic Lecture 7 Gate Level Minimization
Digital Logic Lecture 7 Gate Level Minimization By Ghada Al-Mashaqbeh The Hashemite University Computer Engineering Department Outline Introduction. K-map principles. Simplification using K-maps. Don t-care
More informationCS8803: Advanced Digital Design for Embedded Hardware
CS883: Advanced Digital Design for Embedded Hardware Lecture 2: Boolean Algebra, Gate Network, and Combinational Blocks Instructor: Sung Kyu Lim (limsk@ece.gatech.edu) Website: http://users.ece.gatech.edu/limsk/course/cs883
More informationSpecifying logic functions
CSE4: Components and Design Techniques for Digital Systems Specifying logic functions Instructor: Mohsen Imani Slides from: Prof.Tajana Simunic and Dr.Pietro Mercati We have seen various concepts: Last
More informationQUESTION BANK FOR TEST
CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice
More informationBawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University
Logic Design First Stage Lecture No.6 Boolean Algebra Bawar Abid Abdalla Assistant Lecturer Software Engineering Department Koya University Outlines Boolean Operations Laws of Boolean Algebra Rules of
More information1. Mark the correct statement(s)
1. Mark the correct statement(s) 1.1 A theorem in Boolean algebra: a) Can easily be proved by e.g. logic induction b) Is a logical statement that is assumed to be true, c) Can be contradicted by another
More informationModule -7. Karnaugh Maps
1 Module -7 Karnaugh Maps 1. Introduction 2. Canonical and Standard forms 2.1 Minterms 2.2 Maxterms 2.3 Canonical Sum of Product or Sum-of-Minterms (SOM) 2.4 Canonical product of sum or Product-of-Maxterms(POM)
More informationExperiment 4 Boolean Functions Implementation
Experiment 4 Boolean Functions Implementation Introduction: Generally you will find that the basic logic functions AND, OR, NAND, NOR, and NOT are not sufficient to implement complex digital logic functions.
More informationPoints Addressed in this Lecture. Standard form of Boolean Expressions. Lecture 4: Logic Simplication & Karnaugh Map
Points Addressed in this Lecture Lecture 4: Logic Simplication & Karnaugh Map Professor Peter Cheung Department of EEE, Imperial College London Standard form of Boolean Expressions Sum-of-Products (SOP),
More informationGet Free notes at Module-I One s Complement: Complement all the bits.i.e. makes all 1s as 0s and all 0s as 1s Two s Complement: One s complement+1 SIGNED BINARY NUMBERS Positive integers (including zero)
More informationDate Performed: Marks Obtained: /10. Group Members (ID):. Experiment # 04. Boolean Expression Simplification and Implementation
Name: Instructor: Engr. Date Performed: Marks Obtained: /10 Group Members (ID):. Checked By: Date: Experiment # 04 Boolean Expression Simplification and Implementation OBJECTIVES: To understand the utilization
More informationCombinational Circuits Digital Logic (Materials taken primarily from:
Combinational Circuits Digital Logic (Materials taken primarily from: http://www.facstaff.bucknell.edu/mastascu/elessonshtml/eeindex.html http://www.cs.princeton.edu/~cos126 ) Digital Systems What is a
More informationAssignment (3-6) Boolean Algebra and Logic Simplification - General Questions
Assignment (3-6) Boolean Algebra and Logic Simplification - General Questions 1. Convert the following SOP expression to an equivalent POS expression. 2. Determine the values of A, B, C, and D that make
More informationIncompletely Specified Functions with Don t Cares 2-Level Transformation Review Boolean Cube Karnaugh-Map Representation and Methods Examples
Lecture B: Logic Minimization Incompletely Specified Functions with Don t Cares 2-Level Transformation Review Boolean Cube Karnaugh-Map Representation and Methods Examples Incompletely specified functions
More informationStandard Forms of Expression. Minterms and Maxterms
Standard Forms of Expression Minterms and Maxterms Standard forms of expressions We can write expressions in many ways, but some ways are more useful than others A sum of products (SOP) expression contains:
More informationCode No: 07A3EC03 Set No. 1
Code No: 07A3EC03 Set No. 1 II B.Tech I Semester Regular Examinations, November 2008 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering,
More informationCHAPTER-2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, K-Map and Quine-McCluskey
CHAPTER-2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, K-Map and Quine-McCluskey 2. Introduction Logic gates are connected together to produce a specified output for certain specified combinations of input
More informationPhiladelphia University Faculty of Information Technology Department of Computer Science. Computer Logic Design. By Dareen Hamoudeh.
Philadelphia University Faculty of Information Technology Department of Computer Science Computer Logic Design By Dareen Hamoudeh Dareen Hamoudeh 1 Canonical Forms (Standard Forms of Expression) Minterms
More informationCombinational Logic Circuits Part III -Theoretical Foundations
Combinational Logic Circuits Part III -Theoretical Foundations Overview Simplifying Boolean Functions Algebraic Manipulation Karnaugh Map Manipulation (simplifying functions of 2, 3, 4 variables) Systematic
More informationDigital logic fundamentals. Question Bank. Unit I
Digital logic fundamentals Question Bank Subject Name : Digital Logic Fundamentals Subject code: CA102T Staff Name: R.Roseline Unit I 1. What is Number system? 2. Define binary logic. 3. Show how negative
More informationChapter 2 Combinational
Computer Engineering 1 (ECE290) Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization HOANG Trang 2008 Pearson Education, Inc. Overview Part 1 Gate Circuits and Boolean Equations Binary Logic
More informationSummary. Boolean Addition
Summary Boolean Addition In Boolean algebra, a variable is a symbol used to represent an action, a condition, or data. A single variable can only have a value of or 0. The complement represents the inverse
More informationChapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Overview Part Gate Circuits and Boolean Equations Binary Logic and Gates Boolean Algebra Standard
More informationExperiment 3: Logic Simplification
Module: Logic Design Name:... University no:.. Group no:. Lab Partner Name: Mr. Mohamed El-Saied Experiment : Logic Simplification Objective: How to implement and verify the operation of the logical functions
More information10EC33: DIGITAL ELECTRONICS QUESTION BANK
10EC33: DIGITAL ELECTRONICS Faculty: Dr.Bajarangbali E Examination QuestionS QUESTION BANK 1. Discuss canonical & standard forms of Boolean functions with an example. 2. Convert the following Boolean function
More informationENGIN 112 Intro to Electrical and Computer Engineering
ENGIN 2 Intro to Electrical and Computer Engineering Lecture 8 Minimization with Karnaugh Maps Overview K-maps: an alternate approach to representing oolean functions K-map representation can be used to
More informationENGIN 112. Intro to Electrical and Computer Engineering
ENIN 2 Intro to Electrical and Computer Engineering Lecture 6 More Boolean Algebra ENIN2 L6: More Boolean Algebra September 5, 23 A B Overview Epressing Boolean functions Relationships between algebraic
More informationGate-Level Minimization. BME208 Logic Circuits Yalçın İŞLER
Gate-Level Minimization BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com Complexity of Digital Circuits Directly related to the complexity of the algebraic expression we use to
More informationGate Level Minimization Map Method
Gate Level Minimization Map Method Complexity of hardware implementation is directly related to the complexity of the algebraic expression Truth table representation of a function is unique Algebraically
More informationKarnaugh Maps. Kiril Solovey. Tel-Aviv University, Israel. April 8, Kiril Solovey (TAU) Karnaugh Maps April 8, / 22
Karnaugh Maps Kiril Solovey Tel-Aviv University, Israel April 8, 2013 Kiril Solovey (TAU) Karnaugh Maps April 8, 2013 1 / 22 Reminder: Canonical Representation Sum of Products Function described for the
More informationChapter 3 Simplification of Boolean functions
3.1 Introduction Chapter 3 Simplification of Boolean functions In this chapter, we are going to discuss several methods for simplifying the Boolean function. What is the need for simplifying the Boolean
More informationOutcomes. Unit 9. Logic Function Synthesis KARNAUGH MAPS. Implementing Combinational Functions with Karnaugh Maps
.. Outcomes Unit I can use Karnaugh maps to synthesize combinational functions with several outputs I can determine the appropriate size and contents of a memory to implement any logic function (i.e. truth
More informationSUBJECT CODE: IT T35 DIGITAL SYSTEM DESIGN YEAR / SEM : 2 / 3
UNIT - I PART A (2 Marks) 1. Using Demorgan s theorem convert the following Boolean expression to an equivalent expression that has only OR and complement operations. Show the function can be implemented
More informationChapter 6. Logic Design Optimization Chapter 6
Chapter 6 Logic Design Optimization Chapter 6 Optimization The second part of our design process. Optimization criteria: Performance Size Power Two-level Optimization Manipulating a function until it is
More informationTo write Boolean functions in their standard Min and Max terms format. To simplify Boolean expressions using Karnaugh Map.
3.1 Objectives To write Boolean functions in their standard Min and Max terms format. To simplify Boolean expressions using. 3.2 Sum of Products & Product of Sums Any Boolean expression can be simplified
More informationMidterm Exam Review. CS 2420 :: Fall 2016 Molly O'Neil
Midterm Exam Review CS 2420 :: Fall 2016 Molly O'Neil Midterm Exam Thursday, October 20 In class, pencil & paper exam Closed book, closed notes, no cell phones or calculators, clean desk 20% of your final
More informationLSN 4 Boolean Algebra & Logic Simplification. ECT 224 Digital Computer Fundamentals. Department of Engineering Technology
LSN 4 Boolean Algebra & Logic Simplification Department of Engineering Technology LSN 4 Key Terms Variable: a symbol used to represent a logic quantity Compliment: the inverse of a variable Literal: a
More informationUnit-IV Boolean Algebra
Unit-IV Boolean Algebra Boolean Algebra Chapter: 08 Truth table: Truth table is a table, which represents all the possible values of logical variables/statements along with all the possible results of
More information2.6 BOOLEAN FUNCTIONS
2.6 BOOLEAN FUNCTIONS Binary variables have two values, either 0 or 1. A Boolean function is an expression formed with binary variables, the two binary operators AND and OR, one unary operator NOT, parentheses
More informationS1 Teknik Telekomunikasi Fakultas Teknik Elektro FEH2H3 2016/2017
S1 Teknik Telekomunikasi Fakultas Teknik Elektro FEH2H3 2016/2017 Karnaugh Map Karnaugh maps Last time we saw applications of Boolean logic to circuit design. The basic Boolean operations are AND, OR and
More information2008 The McGraw-Hill Companies, Inc. All rights reserved.
28 The McGraw-Hill Companies, Inc. All rights reserved. 28 The McGraw-Hill Companies, Inc. All rights reserved. All or Nothing Gate Boolean Expression: A B = Y Truth Table (ee next slide) or AB = Y 28
More informationCombinational Logic Circuits
Chapter 2 Combinational Logic Circuits J.J. Shann (Slightly trimmed by C.P. Chung) Chapter Overview 2-1 Binary Logic and Gates 2-2 Boolean Algebra 2-3 Standard Forms 2-4 Two-Level Circuit Optimization
More informationFinal Examination (Open Katz, asynchronous & test notes only, Calculators OK, 3 hours)
Your Name: UNIVERSITY OF CALIFORNIA AT BERKELEY BERKELEY DAVIS IRVINE LOS ANGELES RIVERSIDE SAN DIEGO SAN FRANCISCO Department of Electrical Engineering and Computer Sciences SANTA BARBARA SANTA CRUZ CS
More informationReview. EECS Components and Design Techniques for Digital Systems. Lec 05 Boolean Logic 9/4-04. Seq. Circuit Behavior. Outline.
Review EECS 150 - Components and Design Techniques for Digital Systems Lec 05 Boolean Logic 94-04 David Culler Electrical Engineering and Computer Sciences University of California, Berkeley Design flow
More informationCOLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS UNIT I
KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS YEAR / SEM: III / V UNIT I NUMBER SYSTEM & BOOLEAN ALGEBRA
More informationCOPYRIGHTED MATERIAL INDEX
INDEX Absorption law, 31, 38 Acyclic graph, 35 tree, 36 Addition operators, in VHDL (VHSIC hardware description language), 192 Algebraic division, 105 AND gate, 48 49 Antisymmetric, 34 Applicable input
More informationwww.vidyarthiplus.com Question Paper Code : 31298 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2013. Third Semester Computer Science and Engineering CS 2202/CS 34/EC 1206 A/10144 CS 303/080230012--DIGITAL
More informationSEE1223: Digital Electronics
SEE223: Digital Electronics 3 Combinational Logic Design Zulkifil Md Yusof Dept. of Microelectronics and Computer Engineering The aculty of Electrical Engineering Universiti Teknologi Malaysia Karnaugh
More informationUNIT-4 BOOLEAN LOGIC. NOT Operator Operates on single variable. It gives the complement value of variable.
UNIT-4 BOOLEAN LOGIC Boolean algebra is an algebra that deals with Boolean values((true and FALSE). Everyday we have to make logic decisions: Should I carry the book or not?, Should I watch TV or not?
More informationChap-2 Boolean Algebra
Chap-2 Boolean Algebra Contents: My name Outline: My position, contact Basic information theorem and postulate of Boolean Algebra. or project description Boolean Algebra. Canonical and Standard form. Digital
More informationAnnouncements. Chapter 2 - Part 1 1
Announcements If you haven t shown the grader your proof of prerequisite, please do so by 11:59 pm on 09/05/2018 (Wednesday). I will drop students that do not show us the prerequisite proof after this
More informationChapter 4. Combinational Logic
Chapter 4. Combinational Logic Tong In Oh 1 4.1 Introduction Combinational logic: Logic gates Output determined from only the present combination of inputs Specified by a set of Boolean functions Sequential
More informationL3: Representations of functions
L3: Representations of functions Representations of Boolean functions Boolean expression Two level sum of product form, factorized form Truth tables Karnaugh maps Cubes (MIN,MAX) notation positional cube
More informationBoolean Analysis of Logic Circuits
Course: B.Sc. Applied Physical Science (Computer Science) Year & Sem.: IInd Year, Sem - IIIrd Subject: Computer Science Paper No.: IX Paper Title: Computer System Architecture Lecture No.: 7 Lecture Title:
More informationContents. Chapter 3 Combinational Circuits Page 1 of 34
Chapter 3 Combinational Circuits Page of 34 Contents Contents... 3 Combinational Circuits... 2 3. Analysis of Combinational Circuits... 2 3.. Using a Truth Table... 2 3..2 Using a Boolean unction... 4
More informationCOMBINATIONAL LOGIC CIRCUITS
COMBINATIONAL LOGIC CIRCUITS 4.1 INTRODUCTION The digital system consists of two types of circuits, namely: (i) Combinational circuits and (ii) Sequential circuits A combinational circuit consists of logic
More informationMenu. Algebraic Simplification - Boolean Algebra EEL3701 EEL3701. MSOP, MPOS, Simplification
Menu Minterms & Maxterms SOP & POS MSOP & MPOS Simplification using the theorems/laws/axioms Look into my... 1 Definitions (Review) Algebraic Simplification - Boolean Algebra Minterms (written as m i ):
More informationBoolean Reasoning. The Logic of Boolean Equations. Frank Markham Brown Air Force Institute of Technology
Boolean Reasoning The Logic of Boolean Equations by Frank Markham Brown Air Force Institute of Technology ff Kluwer Academic Publishers Boston/Dordrecht/London Contents Preface Two Logical Languages Boolean
More informationCS470: Computer Architecture. AMD Quad Core
CS470: Computer Architecture Yashwant K. Malaiya, Professor malaiya@cs.colostate.edu AMD Quad Core 1 Architecture Layers Building blocks Gates, flip-flops Functional bocks: Combinational, Sequential Instruction
More informationOptimized Implementation of Logic Functions
June 25, 22 9:7 vra235_ch4 Sheet number Page number 49 black chapter 4 Optimized Implementation of Logic Functions 4. Nc3xe4, Nb8 d7 49 June 25, 22 9:7 vra235_ch4 Sheet number 2 Page number 5 black 5 CHAPTER
More informationBOOLEAN ALGEBRA. Logic circuit: 1. From logic circuit to Boolean expression. Derive the Boolean expression for the following circuits.
COURSE / CODE DIGITAL SYSTEMS FUNDAMENTAL (ECE 421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE 422) BOOLEAN ALGEBRA Boolean Logic Boolean logic is a complete system for logical operations. It is used in countless
More informationReview: Standard forms of expressions
Karnaugh maps Last time we saw applications of Boolean logic to circuit design. The basic Boolean operations are AND, OR and NOT. These operations can be combined to form complex expressions, which can
More informationSimplification of Boolean Functions
Simplification of Boolean Functions Contents: Why simplification? The Map Method Two, Three, Four and Five variable Maps. Simplification of two, three, four and five variable Boolean function by Map method.
More informationLecture (05) Boolean Algebra and Logic Gates
Lecture (05) Boolean Algebra and Logic Gates By: Dr. Ahmed ElShafee ١ Minterms and Maxterms consider two binary variables x and y combined with an AND operation. Since eachv ariable may appear in either
More informationNH 67, Karur Trichy Highways, Puliyur C.F, Karur District UNIT-II COMBINATIONAL CIRCUITS
NH 67, Karur Trichy Highways, Puliyur C.F, 639 114 Karur District DEPARTMENT OF ELETRONICS AND COMMUNICATION ENGINEERING COURSE NOTES SUBJECT: DIGITAL ELECTRONICS CLASS: II YEAR ECE SUBJECT CODE: EC2203
More informationCombinational Logic & Circuits
Week-I Combinational Logic & Circuits Spring' 232 - Logic Design Page Overview Binary logic operations and gates Switching algebra Algebraic Minimization Standard forms Karnaugh Map Minimization Other
More informationSwitching Circuits & Logic Design
Switching Circuits & Logic Design Jie-Hong Roland Jiang 江介宏 Department of Electrical Engineering National Taiwan University Fall 23 5 Karnaugh Maps K-map Walks and Gray Codes http://asicdigitaldesign.wordpress.com/28/9/26/k-maps-walks-and-gray-codes/
More informationDIGITAL CIRCUIT LOGIC UNIT 5: KARNAUGH MAPS (K-MAPS)
DIGITAL CIRCUIT LOGIC UNIT 5: KARNAUGH MAPS (K-MAPS) 1 Learning Objectives 1. Given a function (completely or incompletely specified) of three to five variables, plot it on a Karnaugh map. The function
More informationUNIT I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS PART-A (2 MARKS)
SUBJECT NAME: DIGITAL LOGIC CIRCUITS YEAR / SEM : II / III DEPARTMENT : EEE UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS 1. What is variable mapping? 2. Name the two canonical forms for Boolean algebra.
More informationHomework. Update on website issue Reading: Chapter 7 Homework: All exercises at end of Chapter 7 Due 9/26
Homework Update on website issue Reading: hapter 7 Homework: All exercises at end of hapter 7 Due 9/26 opyright c 22 28 UMaine omputer Science Department / 2 OS 4: Foundations of omputer Science Karnaugh
More informationDigital Logic Design (CEN-120) (3+1)
Digital Logic Design (CEN-120) (3+1) ASSISTANT PROFESSOR Engr. Syed Rizwan Ali, MS(CAAD)UK, PDG(CS)UK, PGD(PM)IR, BS(CE)PK HEC Certified Master Trainer (MT-FPDP) PEC Certified Professional Engineer (COM/2531)
More informationEECS 270 Midterm Exam
EECS 270 Midterm Exam Fall 2009 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: NOTES: Problem # Points 1 /11 2 /4
More informationUNIT II. Circuit minimization
UNIT II Circuit minimization The complexity of the digital logic gates that implement a Boolean function is directly related to the complexity of the algebraic expression from which the function is implemented.
More informationA B AB CD Objectives:
Objectives:. Four variables maps. 2. Simplification using prime implicants. 3. "on t care" conditions. 4. Summary.. Four variables Karnaugh maps Minterms A A m m m3 m2 A B C m4 C A B C m2 m8 C C m5 C m3
More informationIT 201 Digital System Design Module II Notes
IT 201 Digital System Design Module II Notes BOOLEAN OPERATIONS AND EXPRESSIONS Variable, complement, and literal are terms used in Boolean algebra. A variable is a symbol used to represent a logical quantity.
More informationVALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur-603 203 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS YEAR / SEMESTER: II / III ACADEMIC YEAR: 2015-2016 (ODD
More informationLecture 22: Implementing Combinational Logic
8 Lecture 22: Implementing ombinational Logic S 5 L22 James. Hoe Dept of EE, MU April 9, 25 Today s Goal: Design some combinational logic circuits Announcements: Read Rizzoni 2.4 and 2.5 HW 8 due today
More informationECE380 Digital Logic
ECE38 Digital Logic Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum Product-of-Sums Forms, Incompletely Specified Functions Dr. D. J. Jackson Lecture 8- Terminology For
More informationLecture Summary Module 2 Combinational Logic Circuits
Lecture Summary Module 2 Combinational Logic Circuits Learning Outcome: an ability to analyze and design combinational logic circuits Learning Objectives: 2-1. identify minterms (product terms) and maxterms
More informationComputer Organization
Computer Organization (Logic circuits design and minimization) KR Chowdhary Professor & Head Email: kr.chowdhary@gmail.com webpage: krchowdhary.com Department of Computer Science and Engineering MBM Engineering
More informationDepartment of Electrical Engineering McGill University ECSE 221 Introduction to Computer Engineering Assignment 2 Combinational Logic
Department of Electrical Engineering McGill University ECSE 221 Introduction to Computer Engineering Assignment 2 Combinational Logic Question 1: Due October 19 th, 2009 A convenient shorthand for specifying
More information1. What is y-chart? ans: The y- chart consists of three domains:- behavioral, structural and geometrical.
SECTION- A Short questions: (each 2 marks) 1. What is y-chart? ans: The y- chart consists of three domains:- behavioral, structural and geometrical. 2. What is fabrication? ans: It is the process used
More informationSlide Set 5. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary
Slide Set 5 for ENEL 353 Fall 207 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Fall Term, 207 SN s ENEL 353 Fall 207 Slide Set 5 slide
More informationEECS150, Fall 2004, Midterm 1, Prof. Culler. Problem 1 (15 points) 1.a. Circle the gate-level circuits that DO NOT implement a Boolean AND function.
Problem 1 (15 points) 1.a. Circle the gate-level circuits that DO NOT implement a Boolean AND function. 1.b. Show that a 2-to-1 MUX is universal (i.e. that any Boolean expression can be implemented with
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science
More informationReference Sheet for C112 Hardware
Reference Sheet for C112 Hardware 1 Boolean Algebra, Gates and Circuits Autumn 2016 Basic Operators Precedence : (strongest),, + (weakest). AND A B R 0 0 0 0 1 0 1 0 0 1 1 1 OR + A B R 0 0 0 0 1 1 1 0
More informationSimplification of Boolean Functions
COM111 Introduction to Computer Engineering (Fall 2006-2007) NOTES 5 -- page 1 of 5 Introduction Simplification of Boolean Functions You already know one method for simplifying Boolean expressions: Boolean
More informationChapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active in View Show
More informationADAPTIVE MAP FOR SIMPLIFYING BOOLEAN EXPRESSIONS
ABSTRACT ADAPTIVE MAP FOR SIMPLIFYING BOOLEAN EXPRESSIONS Dr. Mohammed H. AL-Jammas Department of Computer and Information Engineering, College of Electronics Engineering, University of Mosul, Mosul -
More informationVLSI System Design Part II : Logic Synthesis (1) Oct Feb.2007
VLSI System Design Part II : Logic Synthesis (1) Oct.2006 - Feb.2007 Lecturer : Tsuyoshi Isshiki Dept. Communications and Integrated Systems, Tokyo Institute of Technology isshiki@vlsi.ss.titech.ac.jp
More informationDefinitions. 03 Logic networks Boolean algebra. Boolean set: B 0,
3. Boolean algebra 3 Logic networks 3. Boolean algebra Definitions Boolean functions Properties Canonical forms Synthesis and minimization alessandro bogliolo isti information science and technology institute
More informationUniversity of Technology
University of Technology Lecturer: Dr. Sinan Majid Course Title: microprocessors 4 th year Lecture 5 & 6 Minimization with Karnaugh Maps Karnaugh maps lternate way of representing oolean function ll rows
More informationMODULE 5 - COMBINATIONAL LOGIC
Introduction to Digital Electronics Module 5: Combinational Logic 1 MODULE 5 - COMBINATIONAL LOGIC OVERVIEW: For any given combination of input binary bits or variables, the logic will have a specific
More informationDigital Circuits ECS 371
Digital Circuits ECS 37 Dr. Prapun Suksompong prapun@siit.tu.ac.th Lecture 7 Office Hours: KD 36-7 Monday 9:-:3, :3-3:3 Tuesday :3-:3 Announcement HW2 posted on the course web site Chapter 4: Write down
More informationBoolean Logic CS.352.F12
Boolean Logic CS.352.F12 Boolean Algebra Boolean Algebra Mathematical system used to manipulate logic equations. Boolean: deals with binary values (True/False, yes/no, on/off, 1/0) Algebra: set of operations
More information