National Exams May Digital Systems & Computers. 3 hours duration

Transcription

1 07-Elec-A4, May 2016 Page 1 of 6 National Exams May Elec-A4 1 Digital Systems & Computers 3 ours duration NOTES: 1. It doubt exists as to te interpretation of any question, te candidate is urged to submit wit te answer paper, a clear statement of any assumptions made. 2. Tis is a Closed Book exam. Candidates may use one of two calculators, te Casio or Sarp approved models. 3. FIVE (5) questions constitute a complete exam. Clearly indicate your coice of any five of te six questions given.oterwise te first five answers found will be considered your pick. 4. All questions are wort 12 points. See below for a detailed breakdown of te marking. lviarking Sceme 1. (a) 2, (b) 5, (c) 2, (d) 3, total = (a) 3, (b) 6, (c) 3, total= (a) 2, (b) 4, (c) 2, (d) 4, total= (a) 4, (b) 5, (c) 3, total = (a) 4, (b) 4, (c) 4, total= l2 6. (a) 4, (b) 8, total= 12 Te number beside eac part above indicates te points tat part is wort

2 07-Elec-A4, May 2016 Page 2 of Given te following function in sums-of-product (SoP) form: f(a, B, C, D) = L mi(0,1,2,4,5,6,7,8,10) were mi represent te mintcrms involved in te Sol' canonical form of j. (a) Prepare its trut table. (b) Map te function f in a K-map and identify: i. One implicant tat is not a prime implicant, ii. One prime implicant tat is not essential, and iii. All essential prime implicants. In identifying eac implicant above list all te min terms in eac of tem. (c) Write te minimized SoP form for f (d) ts te minimized SoP expression found azard-free? Explain and if it is not provide te azard-free SoP form for f 2.- Te following circuit contains two JK flip-flops. (a) Write te logic expressions for JA, KA, JB and KB. (b) Obtain te state transition table for te circuit (c) Sketc te state transition diagram for te circuit. (3 pts] [6 pts] [3 pts] x A {ii---a_ Nute: Consult te flip-flop excitation table attaced at te end as needed.

3 07-Elec-A4, May 2016 Page 3 of (a) Provide te state transition table for an asyncronous binary up-counter tat will go troug te sequence 0000, 0001, 0010,..., 111 l, 0000,... (b) Build te asyncronous binary up-counter in (a) using T nip-flops. (c) Provide te state transition table for a decade counter. (d) Build an asyncronous decade binary up-counter using T Oip-flops. Hint: Try modifying te counter in (b) suc tat it turns into a decade counter. 4.- Te figure below sows a memory cell A built using two cascaded inverte~ Data input D contains te value to be wtitten to te memory cell. Control input W (write) determines wen te value of te memory cell is to be updated wit te value in D. Two tri-state gates (buffers) are used for tis purpose. -w J. <J I D ~ CX> T, A A A (a) Is te control input W (write) active-low or active-ig? Explain by dcsciibing ow te value of te cell is (i) eld and (ii) updated. (b) Provide a trut table aving A, D and Was inputs, and sowing te values of te 2 tri-state gate outputs T1 and T2 for eac input combination. (c) How long does W ave to be active for te memory update to be successful? Explain.

4 07-Elec-A4, May 2016 Page 4 of (a) Identify by marking wit a X wic of te following are te 4 essential components of a computer system. Mouse _Processor (CPU) Printer Hard drive _Memory _ Busscs (address, data, control) _Keyboard _Display monitor _ IIO ports (b) Identify te main differences between a general purpose microprocessor and a microconrroller. (c) Identify wic CPU register(s) is( are) typically associated wit eac of te following - te address of te next instruction to be executed : - te next available location at te top of te stack : - pointing to an array or list of data values in memory : - containing te information an assembly program uses at decision making point~ (conditional branc statements):

5 Page 5 of Figure 6.1 below sows a circuit used to display six DCD digits in six common-catode seven-segmenl displays. Te LED :.mangcment for eac seven-segment display is sown in parts 6.2 and 6.3 of te figure. A buffer cip is used to provide te current required to ligt up te LEDs as determined by Port B pin values, i.e. it provides all six displays wit a logic 'O' or a logic 'l' as dictated by PB1-PB0, wile adding te required driving capacily. (a) Using a CPU accumulator register A wit 'fdaa' (load accumulator A) and 'staa' (store accumulator A) instructions available, write a sequence of assembly instructions to display te number '6' on te seven-segment display #0. Port Band Port Dare memory mapped wit addresses $1004 and $1008, respectively. () Describe a way troug wic we can observe not just one digit lit as in part (a) above but all digits simultaneously sowing ' ' on te display mrnngement sown in Figure 6.1. Include te sequence of steps to accomplis tis as well as te bit patterns needed for Port B. No need to include assembly instructions in part (b) just te algoritmic sequence. Buffer Cip Micro Controller PD vv'v #5 #4 #0 a - I l j I I I 1=1. I =1. 1=1. ~common common common catode i catode ca(ode i Fig 6.1. Port B and Port D togeter drive six seven-segment displays a g Fig 6.2. Seven-segment display common catode Fig 6.3. Common-catode seven-segment display

6 07-Elec-A4, May 2016 Page 6 of 6 Excitation Table Q O+ R s J K T D 0 0 x 0 0 x I I x 1 1 I x I 0 -X x Basic Boolean Identiti Identity l. A+O=A 2. A+l=l 3. A+A=A 4. A+A =I 5. A-0=0 6. A l=a 7. A A :;:;A 8. A A;:;:;O 9. -A=A 10. A+B=B+A l l. A B= B A 12. A+(B+C)= (A+ B)+ C=A+B+C 13. A (B C)={A B) C=A B C 14. A (B+C);:;:; (A B) +(A C) 15. A+(B C) =(A+ B) (A+ C) 16. A+(A B) = A 17. A (A+B) =A 18. (A B)+(A C)+(B C) =(A B)+ (A C) 19. A+B+C+... =A B C A B C... =A+B+C (A+ B) B= A B 22. (A B)+B =A+B Comments Operations wit. 0 and 1 Operatioris wit 0 and 1. Idompotent Complementarity Operations wit 0 and 1 Operations wit 0 and 1, Idempotent' Complementarity Involution Com.mu tati vc Commutative Associative Associative Distributive Distributive Absorption Absorption Consensus De Morgan DeMorgan Simplification Simplification