Programmable Logic Devices. PAL & Jedec Programming

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Dominick Simpson
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1 Programmable Logic Devices PAL & Jedec Programming

2 PAL Devices: PAL = Programmable Array Logic The PAL naming is trademark of the AMD Firm, but Lattice also use these circuits. The PAL device is a PLD with a fixed OR array and a programmable AND array. As only AND gates are programmable, the PAL device is easier to program but it is not as flexible as the PLA. The Type marking of PAL circuits: PAL aa b cc aa: nr. Of INPUTS of AND matrix b: the OUTPUT type definitions: H active high L active low P programmable output polarity C complement In case of PALs with registered output: R registered RP registered with programmable polarity V flexible, programmable with macrocells cc: nr. of dedicated or programmable outputs

3 Some PAL Devices Features AMD, PAL Circuit s Features Type Technology Tpd (ns) Icc (ma) f max (MHz) PAL 16L8-4 TTL 4, PAL 22P10B TTL 15, PAL CE 16V8H EECMOS 5, PAL CE 26V12H EECMOS 7,

4 A simplified PAL Circuit: The device shown in the figure has 4 inputs and 4 outputs. Each input has a bufferinverter gate, and each output is generated by a fixed OR gate. The device has 4 sections, each composed of a 3-wide AND-OR array, meaning that there are 3 programmable AND gates in each section. Each AND gate has 10 programmable input connections indicating by 10 vertical lines intersecting each horizontal line. The horizontal line symbolizes the multiple input configuration of an AND gate. One of the outputs F1 is connected to a buffer-inverter gate and is fed back into the inputs of the AND gates through programmed connections. Designing using a PAL device, the Boolean functions must be simplified to fit into each section. The number of product terms in each section is fixed and if the number of terms in the function is too large, it may be necessary to use two or more sections to implement one Boolean function.

5 A simplified Example for realization: W(A, B, C, D) = m(2, 12, 13) X(A, B, C, D) = m(7, 8, 9, 10, 11, 12, 13, 14, 15) Y(A, B, C, D) = m(0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15) Z(A, B, C, D) = m(1, 2, 8, 12, 13) After the simplification: Note! The function for Z has four product terms. The logical sum of twoofthesetermsisequaltow. Thus, by using W, it is possible to reduce the number of terms for Z from four to three, so that the function can fit into the given PAL device. Since both W and X have two product terms, third AND gate is not used (see x in Gate). If all the inputs to this AND gate left intact, then its output will always be 0, because it receives both the true and complement of each input variable (i.e., A.A =0)

6 The PAL 16L8 Device: Dedicated inputs: Dedicated outputs: 12, 19 Outputs: Programmable I/Os: OR gates: Output programming: The Functional Block Diagram of Circuit

7 The PAL 16L8 Device: These programmable array logic devices feature high speed and a choice of either standard or halfpower devices. They combine Advanced Low-Power Schottky technology with proven titanium-tungsten fuses. These devices will provide reliable, highperformance substitutes for conventional TTL logic. Their easy programmability allow for quick design of custom functions and typically results in a more compact circuit board. In addition, chip carriers are available for further reduction in board space. The Half-Power versions offer a choice of operating frequency, switching speeds, and power dissipation. In many cases, these Half-Power devices can result in significant power reduction from an overall system level.

8 A PAL 16L8 Programming Example: Combinatorial Circuit: I/O assigning: Fuse realization:

9 The JEDEC Format, (Code91,92) The JEDEC (Joint Electron Device Engineering Council) format is used to transfer fuse and test vector data between the programmer and a host computer. Code 91 is full format and includes all the data fields (such as note and test fields) described on the following pages. Code 92 is the Kernel, or shorter, format. The JEDEC Kernel format includes only the minimum information needed for the programming; it does not, for example, include information fields or test vector fields. Prior to transferring a JEDEC file, the appropriate Logic device must be selected. JEDEC s legal character set consists of all the printable ASCII characters and four control characters. The four allowable control characters are STX, ETX, CR (RETURN), and LF (line feed). Other control characters, such as ESC or BREAK, should not be used. The Backus-Naur Form (BNF) is used in the description here to define the syntax of the JEDEC format. BNF is a shorthand notation that follows these rules: :: = denotes is defined as. Characters enclosed by single quotes are literals (required). Angle brackets enclose identifiers. Square brackets enclose optional items. Braces {} enclose a repeated item. The item may appear zero or more times. Vertical bars indicate a choice between items. Repeat counts are given by a :n suffix. For example, a 6-digit number would be defined as: <number> :: = <digit>:6

10 The JEDEC full Format, (Code91,92) The full JEDEC format consists of a start-of-text character <STX>, various fields, an end-oftext character <ETX>, and a transmission checksum. Test vector code representation 0 Input, During testing L level 1 Input, During testing H level C K L H Z N X Input, Positive. impuls L-H-L Input, Negative. impuls H-L-H Output, During proper operation giving L level Output, During proper operation giving H level Output, During proper operation giving High impedance level Vcc, GND Untested output, Unidentified input

11 The JEDEC Field Identifiers A Access time N Note field B * O * C Checksum field P Pin sequence D Device type Q Value field E * R Resulting vector field F Default fuse state field S Starting vector G Security fuse field T Test cycles H * U * I * V Test vector field J * W * K Fuse list field (hex format) X Default test condition L Fuse list field Y * M * Z * The * are Reserved for future use D- Not supported, replaced by: QF/QP Fuse information fields: L,K,F,C

12 The JEDEC Field Identifier s description Each fuse of a device is assigned a decimal number and has two possible states: zero, specifying a low-resistance link, or one, specifying a high resistance link. The state of each fuse in the device is given by three fields: the fuse list (L field or K field), the default state (F field), and the fuse checksum (C field). Fuse states are explicitly defined by either the L field or the K (hexa) field. The character L begins the L field and is followed by the decimal number (address) of the first fuse for which this field defines a state. The first fuse number is followed by a list of binary values indicating the fuse states (program). (The information in the K field is the same as that of the L field except that the information is represented by hex characters instead of binary values.) This allows more compact representation of the fusemap data. The character K begins the K field and is followed by the decimal number of the first fuse. The fuse data follow the fuse number and are represented by hex characters. Each bit of each hex character represents the state of one fuse, so each hex character represents four fuses. The most significant bit of the first hex character following the fuse number corresponds to the state of that fuse number. The next most significant bit corresponds to the state of the next fuse number, etc. The least significant bit of the first hex character corresponds to the state of the fuse at the location specified by the fuse number plus three. The K field supports download operations only. The K field is not part of the JEDEC standard, but is supported by Data I/O for fast data transfer. The L and K fields can be any length desired, and any number of L or K fields can be specified. If the state of a fuse is specified more than once, the last state specified replaces all previous ones for that fuse. The F field defines the states of fuses that are not explicitly defined in the L or K fields. If no F field is specified, all fuse states must be defined by L or K fields.

13 The C Field Calculation: The C field, the fuse information checksum field, is used to detect transmitting and receiving errors. The field contains a 16-bit sum (modulus 65535) computed by adding 8- bit words containing the fuse states for the entire device. The 8-bit words are formed as shown in the following figure. Unused bits in the final 8-bit word are set to zero before the checksum is calculated We are reversing the bit order in the given bytes: ADh FBh 73h ECh The SUM of: ADh+FBh+73h+ECh = 0307h, The C Checksum is: C 0307

14 Example: Create the fuse map and JEDEC Code for PAL 16L8 for case of realizing 4 XOR gates XOR : Y AB AB EQ : Y AB AB Attention! XOR EQ It is enough to create the EQ functions, because the circuit, at the end will negotiate the function. PAL 16L8

15 The JEDEC Code & Map Fuse I/O Assignments:

16 GAL devices-1: GAL = General Array Logic An innovation of the PAL was the generic array logic device, or GAL, invented by Lattice Semiconductor in This device has the same logical properties as the PAL but can be erased and reprogrammed. The GAL is very useful in the prototyping stage of a design, when any bugs in the logic can be corrected by reprogramming. GALs are programmed and reprogrammed using a PAL programmer, or by using the in-circuit programming technique on supporting chips. Lattice GALs combine CMOS and electrically erasable (E 2 ) floating gate technology for a high-speed, low-power logic device. The GAL was an improvement on the PAL because one device was able to take the place of many PAL devices or could even have functionality not covered by the original range. Further we will consider one of the plenty GAL circuits: GALCELLV10 The architecture will be introduced due this IC. See next slide. This circuit has a very characteristic feature, as the Macro-Cells. This device has 12 inputs, which are connected to the AND matrix of the circuit. The I 0 input Can be used as clock for the macro-cells, too. Moreover this device has 10 outputs e.g. macro-cells, with different numbers of products at the differnet macro-cells. The egzact number of products at the different macro cells can be seen in table bellow. Macro-Cell order Nr. Of products

17 A GALCELLV10 architecture: Clock signal Inputs: (11 input) Programmable AND field (44 x 132) matrix Macro-Cells inputs with different Nr. of products Macro-Cells feedbacks

18 Calculation of the matrix s rows and culomns: Sum of different products : 120. Feedbacks from Macro-Cells: 10 Input s enabling control: 10 Dedicated inputs: Reset/Preset of Macro-Cells : 2 Potent/Neg. Inputs: 2x(10+12) Total: 132 Total: 44 The total Nr. Of cross-points in the AND array: 44x132 The Macro-Cells, based on programming, can be used as: Inputs, Combinatorial outputs, Registered outputs. The Macro-Cells (multiplexers) are programmed with S0/S1 Control lines (address). See table bellow: S 0 S 1 Interpretation 0 0 Registered, Active Low 0 1 Registered, Active High 1 0 Combinatorial, Active Low 1 1 Combinatorial, Active High

19 The Macro-Cell Architecture: The different statuses of Macro-Cell, based on programming: S0/S1 0/0 S0/S1 0/1 S0/S1 1/0 S0/S1 1/1

20 AS a relaxation, lets recall the operation of MUXs / DEMUXs X0 U3 1 U1 U3 U2 1 U1 X1 X2 X3 1 U4 U3 1 U1 U1 U2 U2 Y X U3 1 U3 U1 Y0 1 A0 A1 1 U4 U1 Y1 U3 U1 1 Y2 U1 Y3 A0 A1

PEEL 18CV8-5/-7/-10/-15/-25 CMOS Programmable Electrically Erasable Logic Device Features

PEEL 18CV8-5/-7/-10/-15/-25 CMOS Programmable Electrically Erasable Logic Device Features Multiple Speed Power, Temperature Options - VCC = 5 Volts ±10% - Speeds ranging from 5ns to 25 ns - Power as low