MARCH/2008, V 1.0 Alliance Memory Inc. Page 1 of 12

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1 January MAR AS K 16 BIT SUPER 512K OW POWER 8BITMOS OW SRAM POWER MOS SRAM FEATURES Fast access time : 55ns ow power consumption: Operating current :30mA (TYP.) Standby current : 4 A (TYP.) -version Single 2.7V ~ 5.5V power supply All inputs and outputs TT compatible Fully static operation Tri-state output Data byte control : B# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15) Data retention voltage :1.5V(MIN.) ead free and green package available Package : 44-pin 400 mil TSOP-II 48-ball 6mm x 8mm TFBGA GENERA DESRIPTION The is a 4,194,304-bit low power MOS static random access memory organized as 262,144 words by 16 bits. It is fabricated using very high performance, high reliability MOS technology. Its standby current is stable within the range of operating temperature. The is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. The operates fromasingle power supply of 2.7V ~ 5.5V and all inputs and outputs are fully TT compatible PRODUT FAMIY Product Operating Power Dissipation Vcc Range Speed Family Temperature Standby(ISB1,TYP.) Operating(Icc,TYP.) (I) -40 ~ ~ 5.5V 55ns 4µA() 30mA FUNTIONA BOK DIAGRAM PIN DESRIPTION WW AA M7 2 c/2 R YY2 c/2 O T O R T V OU OO U R SYMBO A0 - A17 DQ0 DQ15 E# WE# OE# B# UB# V VSS DESRIPTION Address Inputs Data Inputs/Outputs hip Enable Input Write Enable Input Output Enable Input ower Byte ontrol Upper Byte ontrol Power Supply Ground I TO O R T R MAR/2008, V 1.0 Alliance Memory Inc. Page 1 of 12

2 January MAR AS K 16 BIT SUPER 512K OW POWER 8 BIT MOS OWSRAM POWER MOS SRAM PIN ONFIGURATION A4 A5 A3 A6 A2 A7 A1 OE# A0 UB# E# B# DQ0 DQ15 DQ1 DQ14 DQ2 DQ13 DQ3 DQ12 Vcc Vss Vss Vcc DQ4 DQ5 DQ6 DQ11 DQ10 DQ9 R DQ7 DQ8 AA WW WE# A17 A16 N A8 A9 WW AA A15 A10 A14 A11 A13 A12 TSOP II T ABSOUTE MAIMUN RATINGS* PARAMETER SYMBO RATING UNIT Voltage on V relative to VSS VT1-0.5 to 6.5 V Voltage on any other pin relative to VSS VT2-0.5 to V+0.5 V Operating Temperature TA -40 to 85(I grade) Storage Temperature TSTG -65 to 150 Power Dissipation PD 1 W D Output urrent IOUT 50 ma Soldering Temperature (under 10 sec) TSODER 260 *Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. MAR/2008, V 1.0 Alliance Memory Inc. Page 2 of 12

3 January MAR AS K 16 BIT SUPER 512K OW POWER 8BITMOS OW SRAM POWER MOS SRAM TRUT TABE Standby MODE E# OE# WE# B# UB# Output Disable Read Write Note: = VI, = VI, = Don't care. D EETRIA ARATERISTIS I/O OPERATION DQ0-DQ7 DQ8-DQ15 igh Z igh Z igh Z igh Z igh Z igh Z igh Z igh Z D OUT igh Z igh Z D OUT D OUT D IN igh Z D IN D OUT igh Z D IN D IN SUPPY URRENT ISB1 I,I1 I,I1 I,I1 PARAMETER SYMBO TEST ONDITION MIN. TYP. *3 MA. UNIT Supply Voltage V V Input igh Voltage VI * V+0.3 V Input ow Voltage VI * V Input eakage urrent II V VIN VSS µa Output eakage V VOUT VSS IO urrent Output Disabled µa Output igh Voltage VO IO = -1mA V Output ow Voltage VO IO = 2mA V Average Operating Power supply urrent Standby Power Supply urrent I I1 ISB1 ycle time = Min. E# = VI, II/O = 0mA Other pins at VI or VI ycle time = 1µs E# 0.2V, II/O = 0mA Other pins at 0.2V or V-0.2V E# V-0.2V Others at 0.2V or V-0.2V ma ma I *4 µa Notes: 1. VI(max) = V + 3.0V for pulse width less than 10ns. VI(min) = VSS - 3.0V for pulse width less than 10ns. 2. Over/Undershoot specifications are characterized, not 100% tested. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V(TYP.) and TA = µA for special request APAITANE (TA = 25, f = 1.0Mz) PARAMETER SYMBO MIN. MA UNIT Input apacitance IN - 6 pf Input/Output apacitance I/O - 8 pf Note : These parameters are guaranteed by device characterization, but not production tested. MAR/2008, V 1.0 Alliance Memory Inc. Page 3 of 12

4 January MAR AS K 16 BIT SUPER 512K OW POWER 8 BIT MOS OWSRAM POWER MOS SRAM A TEST ONDITIONS Input Pulse evels 0.2V to V - 0.2V Input Rise and Fall Times 3ns Input and Output Timing Reference evels 1.5V Output oad = 30pF + 1TT, IO/IO = -1mA/2mA A EETRIA ARATERISTIS (1) READ YE PARAMETER SYM. AS UNIT MIN. MA. Read ycle Time tr 55 - ns Address Access Time taa - 55 ns hip Enable Access Time tae - 55 ns Output Enable Access Time toe - 30 ns hip Enable to Output in ow-z tz* 10 - ns Output Enable to Output in ow-z toz* 5 - ns hip Disable to Output in igh-z tz* - 20 ns Output Disable to Output in igh-z toz* - 20 ns Output old from Address hange to 10 - ns B#, UB# Access Time tba - 55 ns B#, UB# to igh-z Output tbz* - 25 ns B#, UB# to ow-z Output tbz* 10 - ns (2) WRITE YE PARAMETER SYM. AS UNIT MIN. MA. Write ycle Time tw 55 - ns Address Valid to End of Write taw 50 - ns hip Enable to End of Write tw 50 - ns Address Set-up Time tas 0 - ns Write Pulse Width twp 45 - ns Write Recovery Time twr 0 - ns Data to Write Time Overlap tdw 25 - ns Data old from End of Write Time td 0 - ns Output Active from End of Write tow* 5 - ns Write to Output in igh-z twz* - 20 ns B#, UB# Valid to End of Write tbw 45 - ns *These parameters are guaranteed by device characterization, but not production tested. MAR/2008, V 1.0 Alliance Memory Inc. Page 4 of 12

5 January MAR AS K 16 BIT SUPER 512K OW POWER 8 BIT MOS OWSRAM POWER MOS SRAM TIMING WAVEFORMS READ YE 1 (Address ontrolled) (1,2) READ YE 2 (E# and OE# ontrolled) (1,3,4,5) Address tr E# taa B#,UB# tae OE# tba tbz tz toz toe to toz tbz tz Dout igh-z Data Valid igh-z Notes : 1.WE#is high for read cycle. 2.Device is continuously selected OE# = low, E# = low, B# or UB# = low. 3.Address must be valid prior to or coincident with E# = low, B# or UB# = low transition; otherwise taa is the limiting parameter. 4.tZ, tbz, toz, tz, tbz and toz are specified with = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tz is less than tz, tbz is less than tbz, toz is less than toz. MAR/2008, V 1.0 Alliance Memory Inc. Page 5 of 12

6 January MAR AS K 16 BIT SUPER 512K OW POWER 8 BIT MOS OWSRAM POWER MOS SRAM WRITE YE 1 (WE# ontrolled) (1,2,3,5,6) WRITE YE 2 (E# ontrolled) (1,2,5,6) MAR/2008, V 1.0 Alliance Memory Inc. Page 6 of 12

7 January MAR AS K 16 BIT SUPER 512K OW POWER 8 BIT MOS OWSRAM POWER MOS SRAM WRITE YE 3 (B#,UB# ontrolled) (1,2,5,6) Notes : 1.WE#,E#, B#, UB# must be high during all address transitions. 2.A write occurs during the overlap of a low E#, low WE#, B# or UB# = low. 3.During a WE# controlled write cycle with OE# low, twp must be greater than twz + tdw to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the E#, B#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and twz are specified with = 5pF. Transition is measured ±500mV from steady state. MAR/2008, V 1.0 Alliance Memory Inc. Page 7 of 12

8 January MAR AS K 16 BIT SUPER 512K OW POWER 8BITMOS OW SRAM POWER MOS SRAM DATA RETENTION ARATERISTIS PARAMETER SYMBO TEST ONDITION MIN. TYP. MA. UNIT V for Data Retention VDR E# V - 0.2V V Data Retention urrent IDR V = 1.5V, E# V-0.2V Others at 0.2V or V-0.2V I µa hip Disable to Data See Data Retention tdr Retention Time Waveforms (below) ns Recovery Time tr tr * - - ns tr * = Read ycle Time DATA RETENTION WAVEFORM ow Vcc Data Retention Waveform (1) (E# controlled) VDR 1.5V Vcc Vcc(min.) Vcc(min.) tdr tr E# VI E# Vcc-0.2V VI ow Vcc Data Retention Waveform (2) (B#, UB# controlled) VDR 1.5V Vcc Vcc(min.) Vcc(min.) tdr tr B#,UB# VI B#,UB# Vcc-0.2V VI MAR/2008, V 1.0 Alliance Memory Inc. Page 8 of 12

9 January MAR AS K 16 BIT SUPER 512K OW POWER 8 BIT MOS OWSRAM POWER MOS SRAM PAKAGE OUTINE DIMENSION 44-pin 400mil TSOP- Package Outline Dimension SYMBOS DIMENSIONS IN MIMETERS DIMENSIONS IN MIS MIN. NOM. MA. MIN. NOM. MA. A A A b c D E E e ZD y o 3 o 6 o 0 o 3 o 6 o MAR/2008, V 1.0 Alliance Memory Inc. Page 9 of 12

January MAR 2008 2007 AS64016 256K 16 BIT SUPER 512K OW POWER 8 BIT MOS OWSRAM POWER MOS SRAM

10 January MAR AS K 16 BIT SUPER 512K OW POWER 8 BIT MOS OWSRAM POWER MOS SRAM 48-ball 6mm 8mm TFBGA Package Outline Dimension MAR/2008, V 1.0 Alliance Memory Inc. Page 10 of 12

11 January MAR AS K 16 BIT SUPER 512K OW POWER 8 BIT MOS OWSRAM POWER MOS SRAM Alliance Organization V Range Package Operating Temp Speed ns AS ZIN 256K x V 44pin TSOP II Industrial ~ AS BIN 256K x V 48ball TFBGA Industrial ~ Part Numbering System AS N Device Number Package Option Temperature Range low power 40 = 4M Access 44pin TSOP II I = Industrial S RAM prefix 16 =x16 Time 48ball TFBGA (-40 to + 85 ) N = ead Free RoS compliant part MAR/2008, V 1.0 Alliance Memory Inc. Page 11 of 12

12 January MAR AS K 16 BIT SUPER 512K OW POWER 8 BIT MOS OWSRAM POWER MOS SRAM Alliance Memory, Inc 511 Taylor Way, San arlos, A 94070, USA Phone: Fax: opyright Alliance Memory All Rights Reserved opyright 2008 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks ofalliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to thisdocument and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The datacontained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at anytime, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information inthis product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide,any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of anyproduct described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability orwarranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to inalliance's Terms and onditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance'sTerms and onditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights,trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components inlife-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion ofalliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against allclaims arising from such use. MAR/2008, V 1.0 Alliance Memory Inc. Page 12 of 12

FEBRUARY/2008, V 1.c Alliance Memory Inc. Page 1 of 13

FEBRUARY/2008, V 1.c Alliance Memory Inc. Page 1 of 13 128K 16 BIT OW 512K POWER 8CMOS BIT OW SRAMPOWER CMOS SRAM FEATURES Fast access time : 55ns ow power consumption: Operating current : 20/18mA (TYP.) Standby current : 2µA (TYP.) Single 2.7V ~ 5.5V power