3D SoC Design Program. Paul Marchal on behalf of the 3D SoC design initiative

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1 3D SoC Design Program on behalf of the 3D SoC design initiative

2 Evolution in 3D Technologies Current Future Source: ChipPAC Limitations Peripheral bonds only Limited rerouting capabilities in laminate substrate Long wire bonds (high inductance, high crosstalk, low speed interconnect) For applications with lowdensity interconnects and with specific I/O pad routing Benefits Excellent electrical characteristics High densities For applications with high interconnects densities imec confidential

3 3D Integration Many System Opportunities Battery MEMS DNA Chip Image Sensor RF Chip Processor Memory Maintaining Moore s momentum increase functionality with number of additional layers 3D resolves the interconnect performance limitations the on-chip interconnect length and related repeater cost Heterogeneous integration build an integrated system with dedicated logic, SRAM, DRAM, FLASH, RF technologies add new sensors, batteries, etc. More modular & scalable design add new standardized components, replace existing ones with better performing ones Courtesy: Samsung Sleek form factor 1mm^3 corresponds to >100Mbit SRAM cells imec confidential

4 Industry buzz centers around 3D First products by our Fabless partners Design start As a reference, TSMC produced wafers in 2007 imec confidential

5 Essential questions for 3D adaptation need answer within next 2 years Where to apply 3D technology first? How to maximize value with 3D technology? How to design for 3D technology? What 3D technology to use? (pitch, via size, etc.) Where and how to get 3D technology as cheap as possible? How to guarantee reliability? How to test 3D technologies? How to package? imec confidential

6 Answers mostly should be analyzed from design/technology perspective Option A Option B scaled TSV on thinned wafers technology TSV Process and its cost implications? E.g., filling of TSVs Reliability due to strain TSV Thin wafer handling and related yield loss? Impact of wafer thinning on front-end? design Area impact of large TSVs? Capacitance of TSVs acceptable for the targeted application? Area benefits of smaller TSVs? Additional area for mitigating thermal issues? Multiple TSVs required for power/gnd distribution due to EM? Additional opportunities for system redesign Comparing cost of two technology options imec confidential

7 3D Program at IMEC to reduce time-2-market for 3D technologies Inputs: Design options Process options Track 4: Demonstrators Killer applications for 3D to validate all design assumptions IP Models IP Exploration (e.g. 3D NoC) System Design Architecture RTL to GDSII Track 3: Architecture Exploration for 3D Introduction into products requires an early matching of 3D technology performance and design options to meet product requirements Design Rules & Models Technology Assessment GDSII Manufacturing & Test Track 2: Design rules and models Reference design flow and early/predictive design rules and models enable technology/design co-optimization Process Modules Technology Research Outputs: Stack cost Performance Power SI Track 1: 3D Process Technology R&D 3D technologies for reliable stacking and interconnection of heterogeneous components, outperforming existing 2D technologies in cost, power, performance and time-2-market imec confidential

8 3D Integration Technologies at IMEC 3D Interconnect Technology 3D-WLP 3D-SIC UTCS VIA-2 Cu nail Embedded Thin die Cu-TSV Via Last Cu-TSV Via First Interconnect around die Through Si Through Si Peripheral /mm /mm 100 /mm Area-array k/mm k/mm 2 10k/mm 2 3D-TSV pitch µm 10 µm 3D-Interconnect pitch µm - - 3D-TSV diameter 15-35µm 1-5 µm Die thickness µm µm µm imec confidential

9 UTCS: Successful embedding of 17µm thin die; 100µm pitch daisy chain demonstrated Die Face up BCB Substrate Die BCB Substrate imec confidential

10 3D WLP Via Phase 2 No litho over topography Scalable via concept imec confidential

11 3D WLP Via Phase II Results Proof of concept demonstrated Isolation Si DRIE Polymer Fill Via Si DRIE 15 um 40 um 5 um PVD Cu seed Cu Bottom up fill imec confidential

12 3D-SIC Key technologies Via processing Extreme thinning Pick-and-place and bonding Through die Cu via Thinned and stacked die: 16.9 µm Stand-off gap: 722nm ~ 1 um TTV Full thickness bonding substrate imec confidential

13 First electrically yielding collective hybrid bonding Test results measured on 20 daisy chains CU06137 D06 CU06137 D03 working chains (%) Landing wafer after collective hybrid bonding of 10 dies number of vias Test results obtained for both experiments on 20 daisy chains Reproducible Electrical Yield, at least up to 1000 vias Yield loss attributed to particle inclusions: being investigated imec confidential

14 3D Program at IMEC to reduce time-2-market for 3D technologies Inputs: Design options Process options Track 4: Demonstrators Killer applications for 3D to validate all design assumptions IP Models IP Exploration (e.g. 3D NoC) System Design Architecture RTL to GDSII Track 3: Architecture Exploration for 3D Introduction into products requires an early matching of 3D technology performance and design options to meet product requirements Design Rules & Models Technology Assessment GDSII Manufacturing & Test Track 2: Design rules and models Reference design flow and early/predictive design rules and models enable technology/design co-optimization Process Modules Technology Research Outputs: Stack cost Performance Power SI Track 1: 3D Process Technology R&D 3D technologies for reliable stacking and interconnection of heterogeneous components, outperforming existing 2D technologies in cost, power, performance and time-2-market imec confidential

15 3D Design: Reference design flow and models Vision reference design flow and early/predictive design rules and models enable technology/design co-optimization Predictive Design rule assessment & Modeling Test-chip Design & Measurement Basic design kit Basic building blocks imec confidential

16 (Predictive) design rules and models bridging technology & design TSV characteristics: Electrical: capacitance, resistance Others: yield, stack alignment, Damage of TSV process to std CMOS E.g. mismatch due to crystal defects Impact of TSV and of relative process on transistors Impact of TSV and of relative process on wires Temperature distribution in a 3D chip Reliability rules Rules for mixed signal design (e.g., EMI, inductive and capacitive coupling) imec confidential

17 TCAD modeling of TSV Electrical Characteristics for Various Technology Options Upper IMD Layer Upper Metal Layer PMD Layer Basic process modules knowhow Lower Metal Layer TSV bcb layer Lower IMD Layer Angled 3D stack except Si-substrate C dep Copper IMD C ox M 1 PMD TSV P-Si Substrate BCB M IMD N Top Die Bottom Die Predictive design rules & models % Dielectric Thickness Capacitance Variation(fF) with Via Diameter and Dielectric Thickness Via Diameter (um) Design Kit & Path Finding Flow Copper Diagram Not To Scale imec confidential

18 Thermo-mechanical Design Rules for 3D TSVs Strain hardening model for Cu in TSV validated by comparing calculated vs measured strain in Si Peak shift (cm -1 ) ºC 250ºC ºC ºC Cu nail Cu nail via (110) (110) -0.2 Carrier Mobility Change (%) µm Position (µm) 5µm pmos Distance from Via (µm) Parallel Direction Perpend. Direction Stress by Narrow TSV = Little impact on carrier mobility 28 Keep-Away-Zone (µm) nm Copper Via Diameter (µm) imec confidential

19 Test-chip for calibrating design rules and models For 200mm wafers (2 metal layers - 130nm platform technology) TSV: Via diameter: 5um/Via pitch: 10um Compatible with both D2W and W2W bonding imec confidential

20 3D Test Structures TSV alignment EM + Yield chains TSV impact on BEOL TSV impact on FEOL TSV RF test imec confidential

21 TSV conduction centered+perimeter TSV array DVM T+B DIE DVM T+B DIE DVM T+B DIE DVM T+B DIE DVM T+B DIE DVM T+B DIE DVM T+B DIE DVM T+B DIE DVM T+B DIE DVM T+B DIE General characteristics: Array of TSVs over heater, diode aside on top and bottom die Replica without TSV Parameters to vary: Density of TSV array: 11x11 (13.64%), 9x9 (8.73%), 7x7 (4.91%), 5x5 (2.18%) imec confidential

22 Full circuit demonstrator: Ring Oscillator TSV T T T TSV B B B Hybrid RO with 2 TSVs, 21 inverter stages on top & 20 inverter stage on bottom (RO_HYB_HalfBotHalfTop) Measured: After Stacking Single Cascaded Inverter stage Frequency Divider imec confidential

23 Full circuit demonstrator: 3D Network-on-chip Memory Top Layer Pads Switch Via Control/Readout Switch TSV bundle Traffic Generator Bottom Layer imec confidential

24 Full circuit demonstrator: 3D Network-on-Chip Array of TSVs Logic Chip characteristics: 1mmx1mm, 50 Mhz, IMEC 130nm, 30 cell standard lib, 2 metal layers Independent JTAG for bottom/top 96 TSVs: 6 VDD/GND, 86 signals imec confidential

25 Insight to Be Gained Demonstrator: 3D NoC If functional tests are passed Electrical performance of 2D vs. 3D interconnects By injecting 2D-only or 3D traffic, and pushing frequency until still operational Yield analysis / redundancy policies for 3D vias By querying via status by JTAG Skew analysis for 3D clock distribution By skewing layer clocks on purpose and checking max achievable operating frequency Power analysis of 3D vias / NoCs By monitoring power in continuous operation mode Validate 3D design flow & the path finding flow By comparing measurement results with estimations Feasibility of Logic on logic stacking imec confidential

26 3D Design Kit for Test-chip Design Rule_0 indicate Error on Bottom Tier Rule_1 indicates Error on Top Tier Design Rule Checks Layout in 3D Layout vs. schematics Parasitic extraction & Simulation imec confidential

27 3D Program at IMEC to reduce time-2-market for 3D technologies Inputs: Design options Process options Track 4: Demonstrators Killer applications for 3D to validate all design assumptions IP Models IP Exploration (e.g. 3D NoC) System Design Architecture RTL to GDSII Track 3: Architecture Exploration for 3D Introduction into products requires an early matching of 3D technology performance and design options to meet product requirements Design Rules & Models Technology Assessment GDSII Manufacturing & Test Track 2: Design rules and models Reference design flow and early/predictive design rules and models enable technology/design co-optimization Process Modules Technology Research Outputs: Stack cost Performance Power SI Track 1: 3D Process Technology R&D 3D technologies for reliable stacking and interconnection of heterogeneous components, outperforming existing 2D technologies in cost, power, performance and time-2-market imec confidential

28 Typical Path Finding Questions What s the killer application? How to adapt the system architecture for the killer app? How to partition the design across multiple layers? What technology to use for each layer? Any idea about cost? Could you perform a physical design due-diligence? Can the targeted power/performance be achieved after P&R? What s the best 3D technology option for this design? E.g., TSS of different geometries on area/cost/performance of the system What s the best way for integrating TSVs? E.g., farm of TSS vs distributed TSS E.g., TSS inside the core area vs. TSS as alternative for IO-pad E.g., how much ESD to foresee What about TSV overhead for non-data signals? E.g., TSS required for power distribution Is this design feasible from a reliability view point? How do I need to adapt my design E.g., thermal analysis Can this design be packaged? Could you estimate cost? Need for a systematic way to explore the above questions at design start imec confidential

29 Architecture exploration including physical design due-diligence RTL Product specs C/C++ Spreadsheets TLM models System-design = using system-level simulation environment (CoWare?) Component-level Modeling Cost Modeling Tech. libs DRM43D 3D stack design = method to enter a multi-later stack design in Javelin = early estimation of area of each layer Pseudo-manual floorplanning = constraining floorplan with of TSSs = visualizing 3D floorplan $/performance/power Estimated P&R = P&R in each layer constraint to TSS = Performance/power analysis of the design as 1 system constraints DesignDB Thermal Analysis Hotspot [Later Apache Gradient] imec confidential

30 Component-level modeling essential link for physical design due-diligence RTL Data-mining? C/C++/systemC Arteris Auto-ESL Atomium? Component-level model: Area of the block Longest delay of any combinational path Input-to-clock time: the maximum delay from input pins to any flip-flop inside the block Clock-to-output time: max. delay between output pins and flip-flop inside the block Too low-level Most designs are available at RTL-level RTL is too detailed for physical design due-diligence of large SoC designs Method to extract just enough physical design information from RTL Too high-level At start of system design, no physical design is available Writing low-level RTL is too labor intensive for physical design duediligence Method to generate just enough physical design information starting from h imec confidential

31 3D Physical Design Exploration with Javelin DA Objective: Designers to explore the physical design impact of alternative design/technology options Outputs: Outputs power, area and performance estimates Interfaces to cost model, to thermal analysis tools, to design authoring EDA Implementation due Q3/Q In collaboration with Javelin DA to enable easy adoptation by industry About Javelin DA: US start-up Fast 2D silicon virtual prototyping engine Supports multiple layers with different technologies Courtesy Javelin-DA imec confidential

32 Overview cost model of 3D stack Process defect density in each layer [defects /cm^2] Design data (from pathfinding flow): e.g., # chip area p. layer [ mm^2] Wafer cost for both layers [$] Info on manufacturing flow: Which steps, what tools, what through put, what tool cost Cost Model outputs cost of chip stack 2D silicon cost To compute silicon cost of each tier 2D silicon cost model 2D silicon cost [$] Additional design data: e.g., # TSVs + Chip stack cost before yield loss [$] 3D yield loss Chip stack cost after Yield loss [$] 3D manufacturing cost 3D integration Cost Yield of the 3D Integration process [%] Test coverage before bonding [%] Inputs are size of each tier, and wafer cost 3D manufacturing cost Cost of the 3D integration based on fab model All data is available model for 3D SIC/WLP on the 200mm platform 300 mm data will follow next year 3D yield loss Estimates yield loss, and adjusts cost accordingly Accounts for 2D and 3D yield. imec confidential

33 Cost is put in function of manufacturing volume Total cost/wafer 600 Infrastructure (tools and clean room area) Personnel Material New tool purchase When Tool utilization over 80% Total cost per wafer ($) Wafer production volume (k wafers/year) imec confidential

34 Adding the yield model allows to assess cost of D2W or W2W bonding strategy D2W cost W2 W2W cost W2 3D-SIC cost p.u.a. of a yielding 3 tier die stack (a.u.)/mm 2 ) D2W cost W1 SIC process cost W2 SIC process cost W1 Die yield loss cost Die cost W3 Die cost W2 Die cost W1 D2W 3D-SIC cost p.u.a. of a yielding 3 tier die stack (a.u.)/mm 2 ) W2W cost W1 SIC process cost W2 SIC process cost W1 Die yield loss cost Die cost W3 Die cost W2 Die cost W1 W2W 60% 65% 70% 75% 80% 85% 2D Die Yield (%) 90% 95% 100% Assumptions: fixed 1cm 2 die size, Fault coverage KGD test=90%, W2W and D2W process yield = 95%, Production volume 30 k wafer stacks. 3D-SIC Cost p.u.a. = Stacked Wafer cost/(number of good 3D stacks x die area) 60% 65% 70% 75% 80% 85% 2D Die Yield (%) 90% 95% 100% imec confidential

35 Thermal Analysis 5x5 mm package 1 mm^2 hotspot Lots of work on thermal analysis Our job is to identify if thermal issues occur in our technology and how much area it will cost to mitigate them. imec confidential

36 3D Integration Program Partners Memory IDM STMicroelectronics Logic IDM Equipment & Materials Suppliers Lam RESEARCH Fabless 3D Program SAT EDA Foundries imec confidential

37 Summary 3D Technology provides many opportunities for design Adapting 3D technologies involves holistic rethinking of design, technology and business strategies IMEC has as objective to facilitate the adaption of 3D technologies R&D on 3D Process Technologies Supporting companies and their designers in evaluating 3D technology options Facilitate the transfer of the developed technologies to industry by creating a co-opetitive research environment imec confidential

38 3D Killer applications? Marco Facchini, Stephane Bronckers, Geert Van Der Plas,

39 Outline 3D & Memory Memory requirements Integration XRAMs 3D DRAM integration challenges 3D & RF applications Substrate noise in VCOs 3D simulation and results Summary imec confidential

40 Peeking into the (near) future - mobile HD1080TV based on AVC H.264 Focus on smart phone market 8 billion $ market <177m smart phones sold in 2007 CAGR exceeds 40% Cost and power are key in this market Next generation smart phones will have HD1080 integrated Required for peer-to-peer entertainment Liveleak.com/Youtube.com This application puts stringent power requirements on the memory subsystem imec confidential

41 Off-chip memory: large, high bandwidth, low power, low cost! 10s of MB Up to 4GB/s MBs cannot be cost-efficiently implemented with SRAMs in classical CMOS Going off-chip puts stringent requirements on memory bandwidth Power consumption becomes excessively high using existing DDR2 DRAMs Read/write ~ 800mW Background energy: >17mW-150mW imec confidential

42 Providing low-power/high performance offchip memory: 3D DRAMs CKE CLK CS# WE# CAS# RAS# Control Logic 3. Less complex protocol. No DDR, QDR or XDR needed 2. More IOs Lower I/F frequency 1024x20MHz<-> 32x800MHz A0-A12 BA0-B1 ADDRESS Counter Refresh Counter Row Address MUX x x Bank Control Logic Column Address Counter/ Latch Row Row Row Address Row Address Address Latch & Address Latch & Latch Decoder & Latch Decoder & Decoder Decoder Banks Sense Amplifiers I/O gating DQM MASK Logic READ DATA LATCH WRITE DRIVERS Column Decoder Data Ouput Register Data Input Register DRAM 15 DQs 1. TSVs Capacitance < 50x No bond paths No ESD? PCB Logic imec confidential

43 Re-engineering power-hungry I/O circuits controller DRAM Reflected signals DRAM DRAMs = high frequency signaling => transmission line Termination circuits to avoid reflection Historically, DRAM circuits have been made to drive PCB lines Standard solution = stub series terminated logic to avoid reflections Extremely difficult to design and integrate Circuit complexity PLLs Voltage reference circuits On die termination logic High power cost Static: DC current on the bus > 15mA when data is forced valid Dynamic Line capacitance ~ 2pF Packaging ~ pF On-chip termination circuitry ~ 2pF Transceiver capacitance ~ 0.6pF imec confidential

44 Low power scenarios for 3D I/O circuits Stripline TSVs (Cline changes, Cpack disappears) No terminations but high transceiver capacitance Simple CMOS coupling imec confidential

45 Initial I/O power estimations Configuration DQ power (mw) DDR DDR 2 DDR 3 SSTL/PCB SSTL/TSV SSTL/TSV no termination CMOS/TS V TSV capacitance: 287fF Operating frequency: 200Mhz imec confidential

46 Re-engineering the I/O width. Example from literature (1) K. Kumagai, C. Yang, et al., System-in-Silicon Architecture and its Application to H.264/AVC Motion Estimation for 1080HDTV, ISSCC imec confidential

47 Re-engineering the I/O width. Example from literature (2) Further optimizations are possible IO drivers as discussed before Re-fine architecture of I/F: Wide data IO is difficult to utilize. Slow operation frequency (25MHz vs. 200MHz) Inflexibility (can not customize the IO width & data height) imec confidential

48 On-chip memory requirements: an alternative for badly scaling SRAMs needed as well 40% of die area are SRAMs Scale badly below 45nm High leakage, Read/write energy Low area efficiency IMEC s AVC.H264 Possible Alternatives Don t scale 6T cell ->adds area, cost Use 8T cell ->adds area, leakage Use fully depleted device ->risk, cost Increase Vdd on memory ->power, power grid complexity Use EDRAM -> increased cost, refresh for distributed memories imec confidential

49 Small 3D DRAMs as an alternative: an extrapolation experiment (1) Goal: To evaluate SRAM-like DRAM memory performances: From SRAM world: peripherals, IO, typical size and speed Use of assumed DRAM technology 2 evaluation steps: Design level : design of a planar capacitance based memory in mixed mode 90 nm process CMOS based planar capacitances based on existing SRAM topology, added refresh Currently under test, but we have simulations Estimation level : evaluation of the changes due to DRAM process vertical Capacitance access transistors imec confidential

50 Small 3D DRAMs as an alternative: an extrapolation experiment (2) SRAM vs. DRAM area for 128kb/500Mhz 90nm UMC memory Global perifs local perifs array DRAM cells are 10x smaller compared to SRAM More than 2x area reduction by just changing the cell on a SRAM matrix Further reduction is possible, by optimizing the peripherals imec confidential

51 Small 3D DRAMs as an alternative: an extrapolation experiment (3) PSRAM / PDRAM Kbits More savings for infrequently used memories (e.g., L2s) f= 500MHz Similar read/write power for same performance Less power to retain data ( pw/bits), because refresh power is less compared to SRAM cell leakage TSV power cost can be contained if TSV capacitance is below 100fF imec confidential

52 More opportunities with resistive switching RAM technologies (1) Spin torque transfer ram Many different concepts & materials: Phase Change RAM Oxide Resistive RAM Conductive Bridging RAM Polymer RAM New STS MRAM Good scaling not limited by minimum charge (# electrons) Flash is depending on CHARGE DENSITY on Floating Gate With Flash scaling, # electrons becomes (too) small 2-terminal device dense arrays possible 2-terminal device high write current scales with technology Outperform NAND/NOR FLASH in read/write access time New system design opportunities Y. Xie, DAC2008, 4MB Cache (extrapolated with Cacti) imec confidential

53 More opportunities with resistive switching RAM technologies (2) 4Mb L2 memory IPC Y. Xie, DAC2008, 4MB Cache (extrapolated with Cacti) Many NVM options/design to explore to limit power Great opportunities for memory architecture design imec confidential

54 Integration schemes for (X)RAMs in 3D 10000s TSVs CKE CLK CS# WE# CAS# RAS# 12 -B1 Control Logic ADDRESS Counter Refresh Counter Row Address MUX x x Bank Control Logic Column Address Counter/ Latch Row Row Row Address Row Address Address Latch & Address Latch & Latch Decoder & Latch Decoder & Decoder Decoder Banks Sense Amplifiers I/O gating DQM MASK Logic READ DATA LATCH WRITE DRIVERS Column Decoder Data Ouput Register Data Input Register DRAM 15 DQs 1000s TSVs Higher aspects ratios (>1:10) Higher overlay accuracy (below 1um) => Requires a completely different process technology all together (e.g., W2W or silicon layer growth) Benefits of Aggressive partitioning vs. 3D Technology complexity/cost should be examined 100s TSVs imec confidential

55 Main challenges Short term: off-chip 3D DRAMs Re-designing the memory interface for lower power, while increasing the bandwidth between the logic die and the DRAM banks. Evaluating alternative 3D technology stacking options for performance, power and cost Resolve thermo-mechanical challenges such that they do not degrade the DRAM performance. Develop a test and repair strategy Support standardization for low cost and acceptance of product on market Longer term: memory architecture re-design with 3D XRAMs Predictive IP models for aggressively scaled NVM memories, including various 3D integration schemes Identify system opportunities for improving memory architectures with 3D XRAMs Develop appropriate 3D technology and NVM technology imec confidential

56 Outline 3D & Memory Memory requirements Opportunity for low power 3D DRAM integration challenges Beyond the next generation DRAM 3D & RF applications Substrate noise in VCOs 3D simulation and results Summary imec confidential

57 Substrate noise can severely harm the VCO performance in Mixed-Signal SoCs Digital Analog/RF Output Power (dbc) Frequency Leakage to adjacent channels Phase Noise degradation imec confidential

58 Can 3D-integration solve the signal integrity issues? An experiment can be setup to measure the isolation improvement in the case of 3D-stacking Test case: very sensitive 60GHz VCO Preliminary feasibility study in HFSS is performed imec confidential

59 3D stacked 60GHz VCO experiment Dicing the substrate contact from one VCO Glue on top of another VCO IBIAS G P G G G Output VCO (Die 2) S S P P VDD VTUNE G G G S G Substrate noise (Die 1) imec confidential

60 3D stacked 60GHz VCO experiment Output VCO (Die 2) Substrate noise Substrate noise (Die 1) How good is the substrate noise isolation? imec confidential

61 After using10gb HDD and 8Gb Ram, and 8 hours later... imec confidential

62 Summary DRAM & RF seem killer applications for 3D 3D & heterogeneous memory integration Starting with DRAM with improved I/F Going for more advanced NVM memories System-level requirements for 3D memories need to be set Determine internal memory design Set requirements for 3D technology roadmap RF applications Substrate noise reduction and X-coupling seem low in simulation, but need to be validated experimentally Implications on RF circuit design need to be further explored imec confidential