Layout Analysis I/O. Analysis from an HD Video/Audio SoC

Transcription

1 Sample Report Analysis from an HD Video/Audio SoC For any additional technical needs concerning semiconductor and electronics technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: Fax:

2 Table of Contents 1 Overview List of Figures 1.3 List of Tables 2 Device Overview 2.1 Introduction 2.2 Device Summary 3 Device Identification 3.1 Package 3.2 Die 4 I/O Analysis 4.1 I/O Block Analysis 4.2 I/O Block Measurements 4.3 Plan-View and Functional Analysis 5 Statement of Measurement Uncertainty and Scope Variation About Chipworks

3 Overview Overview 1.1 An overview of an IC s I/O circuits. A lower level metal or poly die photo is annotated showing the I/O blocks on the die. I/O cell type and size have a large impact on die size, and hence on product cost. This report contains: Package photographs Package X-ray Depot (bare die) die photograph Die size measurements Annotated metal 1 or poly die photograph showing I/O groups (e.g., memory, host processor) Zoomed-in views of each I/O block on the metal 1 or polysilicon layer I/O measurements Zoomed-in views of each type of I/O on the metal 1 or polysilicon layer Zoomed-in view of die corner Zoomed-in view and measurements of pad size and pitch Discussion of possible functionality, bus type, and bus width of each I/O Table summarizing the L, W, Area, and the percentage die area of each I/O block

4 Overview List of Figures 3 Device Identification Package X-Ray Die Photograph Die Markings A Die Markings B 4 I/O Analysis Annotated Die Photograph I/O Blocks I/O Block Type I/O 1 Metal I/O Block Type I/O 2 Metal I/O Block Type I/O 3 Metal I/O Block Type I/O 4 Metal I/O Block Type I/O 6 Metal I/O Block Type I/O 7 Metal I/O Block Type I/O 8 Metal I/O Block Type I/O 8 Metal List of Tables 2 Device Overview Device Identification Device Summary 4 I/O Analysis I/O Block Measurements

5 Device Overview Device Overview 2.1 Introduction Manufacturer and device profile with key findings summarized. This report contains the following detailed information: Package photographs, package X-ray, die markings, die photograph, and die photographs with annotated functional blocks and memories Measurements of horizontal dimensions of major microstructural features Identification of major I/O blocks All of the analysis for this report was performed on two parts, with the following markings: Table Device Identification Device Package markings Die markings Date code Device Identification Table Device Identification

6 Device Overview Device Summary Table Device Summary Manufacturer Foundry Part number Type Date code Package markings Package type Package dimensions Die markings Die size (die edge seal) Device Summary Table Device Summary

7 Device Identification Device Identification 3.1 Package A plan-view X-ray photograph is shown in Figure The die was flipchip mounted on the PCB of the package. Figure 3.1.1Package X-Ray Figure Package X-Ray Figure Package X-Ray

8 Device Identification Die Figure shows a photograph of the die. The die is 9.02 mm x 7.84 mm as measured from the die seals, or 9.07 mm x 7.89 mm for the whole die. This yields a die area of 70.7 mm 2 within the die seals. Bond pads are arranged in a grid across the surface of the die. Figure 3.2.1Die Photograph Figure Die Photograph flip-chip bond pads Figure Die Photograph

9 Device Identification 3-3 The die markings are shown in Figure 3.2.2and Figure These include: Figure 3.2.2Die Markings A Figure Die Markings A Figure Die Markings A Figure 3.2.3Die Markings B Figure Die Markings B Figure Die Markings B

10 I/O Analysis I/O Analysis 4.1 I/O Block Analysis The device contains a number of different I/O structures. These structures have been grouped into many distinct I/O block types. Figure shows the I/O blocks annotated on a photograph of the die, delayered to the metal 1 layer. The blocks are divided according to the observation of the layout features of the device, not through reverse engineering. There are eleven distinct I/O block types on the device, containing 17 different I/O structures in total. I/O block type I/O 1 contains three different I/O structures. They are located on the top left of the die. These IOs are adjacent to BLK 1 and BLK 2 (video DACs). I/O block type I/O 2 contains two different I/O structures. They are located at the top of the die. These IOs are adjacent to BLK 3 (DACs). I/O block type I/O 3 contains three different I/O structures. They are located at the top of the die. These I/Os are adjacent to BLK 4 (HDMI controller). I/O block type I/O 4 contains three different I/O structures. They are located at the top of the die. These I/Os are adjacent to BLK 5. I/O block type I/O 5 contains the same type of I/O structures similar to I/O block type IO 3. They are located at the top of the die. These I/Os are adjacent to BLK 5 (USB controller). I/O block type I/O 6 contains two different I/O structures. They are located at the top right of the die. I/O block type I/O 7 contains three different I/O structures. The first I/O structure is the DDR2 I/Os for the DRAM controller. The next two I/O structures may be the DDR2 I/O power supplies. They are located at the rightmost part of the die. I/O block type I/O 8 contains four different I/O structures. They are located at the bottom of the die. I/O block type I/O 9 contains the same I/O structures as that of I/O 8. They are located at the bottom left of the die. I/O block type I/O 10 contains the same I/O structures as that of I/O 1. They are located at the leftmost part of the die. These are adjacent to BLK 15, BLK 16, BLK 17, and BLK 18. These I/Os are presumed to be used in the RF modulator block, transport controller, and PLLs. I/O block type I/O 11 contains the same I/O structures as that of I/O 8. They are located at the top left of the die. Further discussions of the functionality of I/O blocks can be found in the following sections.

11 I/O Analysis 4-2 Figure 4.1.1Annotated Die Photograph I/O Blocks Figure Annotated Die Photograph I/O Blocks I/O 6 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 11 I/O 10 I/O 7 I/O 9 I/O 8 Figure Annotated Die Photograph I/O Blocks

12 I/O Analysis I/O Block Measurements Table shows the measurements of each I/O block, as analyzed in the last section and shown in Figure The "Possible Function" column indicates the possible function of the I/O block or the related functional/analog block. Together, all I/O blocks occupy 9.62 mm 2 of the die, which is about 13.44% of the die area. All measurements in this section are measured from the optical microscope planview images. Table I/O Block Type I/O 1 (1) I/O 1 (2) I/O 1 (3) I/O 2 (1) I/O 2 (2) I/O 3 (1) I/O 3 (2) I/O 3 (3) I/O Block Measurements Possible Function Analog input/output Analog input/output Analog input/output Analog input/output Analog input/output Analog input/output Analog input/output Analog input/output I/O Block Measurements Length (mm) Width (mm) Area (mm 2 ) Percentage of Die (%) I/O 4 (1) I/O 4 (2) ESD Protection I/O 4 (3) ESD Protection I/O 5 Same structure as that of I/O 3 I/O 6 (1) Input/output I/O 6 (2) Input/output I/O 7 (1) DDR2 I/O I/O 7 (2) DDR2 supply input I/O 7 (3) DDR2 supply input I/O 8 (1) General purpose input/output I/O 8 (2) General purpose input/output

13 I/O Analysis 4-4 I/O 8 (3) General purpose input/output I/O 8 (4) General purpose input/output I/O 9 Same structures as that of I/O 8 I/O 10 Same structures as that of I/O 1 I/O 11 Same structures as that of I/O 8 Table I/O Block Measurements

14 I/O Analysis Plan-View and Functional Analysis This section contains close-up optical microscope images of the different I/O structures present in the I/O block types. The images were captured from a die, delayered to the metal 1 layer. However, due to delayering difficulties at the periphery of the die, the quality of the I/O areas vary significantly from being under-etched with artifacts from metal 2 and metal 3 layers to being over-etched down to the polysilicon layer. A ruler is placed on each image. Figure is a close-up image of the I/O structures of block type I/O 1. It contains three different I/O structures. These IOs are adjacent to BLK 1 and BLK 2 (video DACs). Therefore, we believe these I/O structures are used for analog input/output. Figure 4.3.1I/O Block Type I/O 1 Metal 1 Figure I/O Block Type I/O 1 Metal 1 I/O1 (1) I/O1 (2) I/O1 (3) 40 µm Figure I/O Block Type I/O 1 Metal 1

15 I/O Analysis 4-6 Figure is a close-up optical microscope plan-view image, at the metal 1 layer, of the I/O block type I/O 2. It contains two different I/O structures. These I/Os are adjacent to BLK 3 (DACs). These I/O structures are used for analog input/output. Figure 4.3.2I/O Block Type I/O 2 Metal 1 Figure I/O Block Type I/O 2 Metal 1 I/O2 (1) I/O2 (2) 40 µm Figure I/O Block Type I/O 2 Metal 1

16 I/O Analysis 4-7 Figure is a close-up optical microscope plan-view image, at the metal 1 layer, of the I/O block type I/O 3. It contains three different I/O structures. Also, block type I/O 5 contains the same type of I/O structures similar to the I/O block type I/O 3. These I/Os are adjacent to BLK 4 (HDMI controller) and are believe to be I/O structures for analog input/output purposes. BLK 5 (USB) on the other hand, are I/O structures for USB input/output purposes. Figure 4.3.3I/O Block Type I/O 3 Metal 1 Figure I/O Block Type I/O 3 Metal 1 I/O3 (1) I/O3 (2) I/O3 (3) 40 µm Figure I/O Block Type I/O 3 Metal 1

17 I/O Analysis 4-8 Figure is a close-up optical microscope plan-view image, at the metal 1 layer, of the I/O block type I/O 4. It contains three different I/O or ESD structures. These I/Os or ESDs are adjacent to BLK 5 and are believed to be I/Os with ESD structures for analog input/output purposes. Figure 4.3.4I/O Block Type I/O 4 Metal 1 Figure I/O Block Type I/O 4 Metal 1 I/O4 (1) I/O4 (2) I/O4 (3) 40 µm Figure I/O Block Type I/O 4 Metal 1

18 I/O Analysis 4-9 Figure is a close-up optical microscope plan-view image, at the metal 1 layer, of the I/O block type I/O 6. It contains two different I/O structures. Figure 4.3.5I/O Block Type I/O 6 Metal 1 Figure I/O Block Type I/O 6 Metal 1 I/O6 (1) I/O6 (2) 30 µm Figure I/O Block Type I/O 6 Metal 1

19 I/O Analysis 4-10 Figure is a close-up optical microscope plan-view image, at the metal 1 layer, of the I/O block type I/O 7. It contains three different I/O structures. These I/Os are adjacent to the DRAM controller. The first I/O structure is the DDR2 I/Os for the DRAM controller. The next two I/O structures may be the DDR2 I/O power supplies. Figure 4.3.6I/O Block Type I/O 7 Metal 1 Figure I/O Block Type I/O 7 Metal 1 50 µm I/O7(1) I/O7(2) I/O7(3) Figure I/O Block Type I/O 7 Metal 1

20 I/O Analysis 4-11 Figure is a close-up optical microscope plan-view image, at the metal 1 layer, of the I/O block type I/O 8. I/O 6 contains four different I/O structures. Also, block types I/O 9 and I/O 11 contain the same type of I/O structures similar to the I/O block type I/O 8. Figure 4.3.7I/O Block Type I/O 8 Metal 1 Figure I/O Block Type I/O 8 Metal 1 I/O8 (1) I/O8 (2) I/O8 (3) I/O8 (4) 30 µm Figure I/O Block Type I/O 8 Metal 1

21 I/O Analysis 4-12 Figure is a close-up optical microscope plan-view image, at the metal 1 layer, of the I/O block type I/O 10. I/O 10 contains the same I/O structures as that of I/O 1. They are located at the leftmost part of the die. These I/Os are adjacent to BLK 15, BLK 16, BLK 17, and BLK 18. These I/Os are presumed to be used in the RF modulator block, transport controller, and PLLs. Figure 4.3.8I/O Block Type I/O 8 Metal 1 Figure I/O Block Type I/O 8 Metal 1 Figure I/O Block Type I/O 8 Metal 1

22 Statement of Measurement Uncertainty and Scope Variation Statement of Measurement Uncertainty and Scope Variation Statement of Measurement Uncertainty Chipworks calibrates length measurements on its scanning electron microscopes (SEM), transmission electron microscope (TEM), and optical microscopes, using measurement standards that are traceable to the International System of Units (SI). Our SEM/TEM cross-calibration standard was calibrated at the National Physical Laboratory (NPL) in the UK (Report Reference LR0304/E /SEM4/190). This standard has a 146 ± 2 nm (± 1.4%) pitch, as certified by NPL. Chipworks regularly verifies that its SEM and TEM are calibrated to within ± 2% of this standard, over the full magnification ranges used. Fluctuations in the tool performance, coupled with variability in sample preparation, and random errors introduced during analyses of the micrographs, yield an expanded uncertainty of about ± 5%. The materials analysis reported in Chipworks reports is normally limited to approximate elemental composition, rather than stoichiometry, since calibration of our SEM and TEM based methods is not feasible. Chipworks will typically abbreviate, using only the elemental symbols, rather than full chemical formulae, usually starting with silicon or the metallic element, then in approximate order of decreasing atomic % (when known). Elemental labels on energy dispersive X-ray spectra (EDS) will be colored red for spurious peaks (elements not originally in sample). Elemental labels in blue correspond to interference from adjacent layers. Secondary ion mass spectrometry (SIMS) data may be calibrated for certain dopant elements, provided suitable standards were available. A stage micrometer, calibrated at the National Research Council of Canada (CNRC) (Report Reference LS ), is used to calibrate Chipworks optical microscopes. This standard has an expanded uncertainty of 0.3 µm for the stage micrometer s 100 µm pitch lines. Random errors, during analyses of optical micrographs, yield an expanded uncertainty of approximately ± 5% to the measurements. Statement of Scope Variation Due to the nature of reverse engineering, there is a possibility of minor content variation in Chipworks standard reports. Chipworks has a defined table of contents for each standard report type. At a minimum, the defined content will be included in the report. However, depending on the nature of the analysis, additional information may be provided in a report, as value-added material for our customers.

23 About Chipworks About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at: Chipworks 3685 Richmond Rd. Suite 500 Ottawa, Ontario K2H 5B7 Canada T: F: Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com