25 nm Omega FinFET: Three-dimensional Process and Device Simulations

Transcription

1 25 nm Omega FinFET: Three-dimensional Process and Device Simulations Abstract This Sentaurus simulation project provides a template setup for three-dimensional process simulation and device simulations of Omega FinFETs. The threedimensional process simulation is based on a particularly robust approach in which geometry-altering and dopant-related processing steps are executed sequentially in two separate groups. The Sentaurus Workbench template project also performs 3D quantum transport I d V gs simulations using the density gradient model. The influence of the complex dopant redistribution during the short annealing (RTA) on the electrical characteristics of the final FinFET is discussed. In addition, the influence of quantum effects on this nanoscale device is investigated. Version Information This application note has been designed and verified using TCAD Sentaurus Version Running it with previous or future versions may possibly require minor adjustments.

2 Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. Copyright 2007 Synopsys, Inc. All rights reserved.

3 Introduction Shrinking feature sizes and novel device designs increase the need for three-dimensional process and device simulations. TCAD Sentaurus offers a unique approach to robust 3D process simulation, which is relevant to many modern applications. This approach is based on the observation that the optimal structure representation for the simulation of geometryaltering processing steps (patterning, etching, deposition, fill, chemical-mechanical polishing (CMP)) and dopantrelated processing steps (implantation, annealing) is very different. While for geometry-altering steps, it is sufficient to represent the structure as a set of boundaries, for dopantrelated steps, the entire volume of the structure must be represented by a finite-element mesh. For many modern technologies, it is advantageous to separate these two kinds of processing step. The advantages of this approach is considerable gain in simulation speed as well as an improvement in robustness. This approach requires the (time-consuming) generation of a finite-element mesh only once, after all geometry-altering processing steps are modeled, instead of after each geometry-altering processing step. This approach to 3D process simulation is illustrated here for the example of a 25 nm NMOS Omega FinFET. FinFETs are interesting candidates for scaling CMOS devices into the nanoscale regime. However, these nonplanar devices are inherently three-dimensional in nature. Therefore, for FinFETs, any meaningful TCAD process or device simulation must be performed in three dimensions. Inspect. For an introduction and tutorials, refer to the Sentaurus training material. The focus of this project is to provide a setup that can be used as is or adapted to specific needs. The documentation focuses on aspects of the setups. For details about tool uses and specific tool syntax, refer to the respective manuals. Process flow The process flow used here is similar to the flow presented by F.-L. ang et al. [2][3]. Figure 1 to Figure 9 show the device structure at various stages of the process flow. Exploiting the symmetry of the structure, only the drain-half of the FinFET is modeled. The process flow consists of the following steps. The starting material is an SOI wafer with a top silicon layer thickness of 50 nm. The top silicon layer has initially a uniform boron concentration of 5 x cm 3. All lithographic patterning is based on a line width of 45 nm. 1. Fin Mask Definition 1.1 Deposit a protective hard mask 1.2 Define an intermediate mask 1.3 Isotropic deposition of nitride (25 nm) 1.4 Anisotropic etching of nitride 1.5 Strip intermediate mask This sequence of processing steps results in a 25 nm wide mask, which is well below the assumed lithographic capabilities (45 nm). Within this approach, first the geometric process modeling tool (here, Sentaurus Structure Editor in process emulation mode) executes all geometry-altering processing steps and saves all intermediate device structures before dopantrelated processing steps. In a second pass, Sentaurus Process automatically recreates the intermediate device structures and performs all implant and anneal steps [1]. A Sentaurus Workbench split has been added that allows users to select between using Sentaurus Process to simulate the implantation and annealing steps, or to skip this step and use analytic profiles. This split can be used for quick tests. After the process simulation, the I d V gs curves for a lowdrain bias and high-drain bias are simulated and relevant electrical parameters, such as threshold voltages and drain current levels, are extracted. It is assumed that the user is familiar with the Sentaurus tool suite, in particular, with Sentaurus Workbench, Sentaurus Process, Sentaurus Structure Editor, Sentaurus Device, and Figure 1 Device structure after Step 1.3. Region colors correspond to materials as follows: pink=silicon, magenta=polysilicon, brown=oxide, gold=nitride, green=hard mask. Copyright 2007 Synopsys, Inc. All rights reserved. 3

4 2. Source/ Mask Definition 2.1 Define an intermediate source/drain mask 2.2 Anisotropic deposition of a new nitride layer 2.3 Etch source/drain mask, lift-off of nitride layer 5. Gate Definition 5.1 Deposit gate oxide (2 nm) 5.2 Fill with polysilicon and CMP 5.3 Define gate mask 5.4 Etch polysilicon using isotropic underetch (gate trim) 5.5 Strip gate mask Fin Box Omega Underetch Figure 3 Device structure after Step 5.1. The view focuses on the underetch buried oxide, which allows the polysilicon gate to penetrate under the fin. Figure 2 Device structure after Step 2.3. To define the mask for the source/drain area, the lift-off technique is used. First, a mask in defined, which covers the channel fin. Then, another nitride layer is deposited anisotropically, such that the part of the newly created nitride layer, which covers the source/drain, is not in contact with the part that is on top of the resist layer. Next, the resist is removed by an isotropic (wet) etch process. Then, the unsupported nitride layer, which used to be on top of the resist, is flushed way with the solvent. This process is modeled with Sentaurus Structure Editor by deleting the resist region as well as the part of the nitride that was on top of the resist. 3. Fin and Source/ Area Creation 3.1 Etch protective hard mask and silicon layer 3.2 Strip intermediate nitride mask After depositing the gate oxide, the entire structure is filled with polysilicon. The gate mask is created using the lithographic line width of 45 nm. However, during the polysilicon etch, a mix of anisotropic (95%) and isotropic (5%) etching is applied, resulting is a gate length of 25 nm, that is, much shorter than the lithographic line width. 6. Extension Spacer Formation 6.1 Isotropic oxide deposition (2 nm) 6.2 Isotropic nitride deposition (5 nm) 6.3 Anisotropic nitride etching This sequence of processing steps cuts out the dog bone shaped silicon patch, which will form the channel fin as well as the source and drain areas. 4. Omega Creation 4.1 Isotropic etching of buried oxide (7 nm) 4.2 Strip protective hard mask To obtain an even better control of the gate over the channel, the buried oxide is etched isotropically and, therefore, is slightly undercut. This makes room for the gate material to wrap around the channel fin. Figure 4 Device structure after Step Copyright 2007 Synopsys, Inc. All rights reserved.

5 8. Source/ Spacer Formation 8.1 Isotropic nitride deposition (40 nm) 8.2 Anisotropic nitride etching Figure 5 Device structure after Step 6.3. An extension spacer is defined to prevent the penetration of the extension implants under the gate due to the inherent lateral straggle. 7. Extension Implantation (Dose=2.5 x cm 3, Energy=7.5 kev) 7.1 First arsenic implantation (Tilt=45 o, Rotation=270 o ) 7.2 Second arsenic implantation (Tilt=45 o, Rotation=90 o ) The extension implantation is performed by Sentaurus Process. To obtain a more uniform doping profile at the left and right sides of the fin, the implantation is performed in two steps. The implantation directions are shown in Figure 6, which also shows the as-implanted profile after the first implantation. Figure 7 Device structure after Step 8.2. The source and drain spacer is created using the same technique as used for the extension implant, but this spacer is much thicker. 9. Source/ Implantation 9.1 Phosphorus (Dose=4x10 14 cm 3, Energy=15 kev) To ensure a relatively uniform doping in the source/drain area, phosphorus is used. It penetrates deeper than arsenic and diffuses faster during activation/annealing. Figure 8 shows the as-implanted phosphorus profile. As-Implanted Phosphorus [cm-3] 6.0e e e e+18 Figure 6 As-Implanted Arsenic [cm -3 ] 2.0e e e+18 As-implanted arsenic profile after Step 7.1. Arrows indicate the direction of the implantation ion beams for the first (solid) and second (dashed) extension implant. For better viewing, only the (transparent) silicon layer as well as three arsenic isosurfaces are shown. Figure 8 As-implanted phosphorus profile after Step 9. Arrow indicates the direction of the implantation ion beam. For better viewing, only the (transparent) silicon layer and four phosphorus isosurfaces are shown. 10. Rapid Thermal Anneal (1 s at 1025 K, with a 3 s ramp-up and a 2 s rampdown) Copyright 2007 Synopsys, Inc. All rights reserved. 5

6 Final Doping [cm -3 ] a corresponding depletion of boron in the center of the channel fin in the extension area. 4.0e e e e e+19 Near the p-n junction, the electric field from the arsenic ions slightly depletes the boron concentration on the p-side and, further at the channel gate interface, boron segregation increases the surface concentration by approximately 7%. 1.5e e e e e Right Gate Final Arsenic [cm -3 ] 7.2e e e e+14 Figure 9 Fin Final net dopant distribution after Step 10. For better viewing, only the silicon layer is shown. 0 Fin The activation/annealing is simulated by Sentaurus Process using the pair diffusion model. The silicon layer is assumed to have initially a uniform boron concentration of 5x10 18 cm 3. However, due to the complex interaction of all dopants (arsenic, phosphorus, and boron) with point defects as well as among themselves via the electric field of the charge impurities, the boron distribution is nonuniform after the activation/annealing Top Gate Fin Final Phosphorus [cm -3 ] 1.0e e e e Box Figure 10 Final phosphorus distribution along the xz plane at the center of the device structure (y=0). Figure 10 shows the final phosphorus distribution along the xz plane at the center of the device structure (y=0). Figure 11 shows the final arsenic distribution along the xy plane at a z-coordinate, which corresponds to 75% of the silicon layer height. Figure 12 shows the final boron distribution along the same plane as in Figure 11. It can be seen clearly that during the annealing process, boron is redistributed in a complex fashion: The arsenic extension implant introduces a large amount of interstitials, which during the annealing diffuse quickly to the surface where they recombine. As boron diffuses only as boron interstitial pairs, boron is transferred to the surface in this process. Due to a small volume in the channel fin, a limited amount of boron is available and, therefore, the boron pileup at the surface in the extension area is accompanied by 0.02 Left Gate Figure 11 Final arsenic distribution along the xy plane at a z-coordinate, which corresponds to 75% of the silicon layer height Figure 12 Final boron distribution along the same plane as in Figure Contact Formation 0 Right Gate Fin Left Gate Final Boron [cm -3 ] Extension 4.0e e+18 Finally, the contact areas are etched free from the screening oxide (deposited in Steps 5.1 and 6.1) and electrical contacts are defined for use in the device simulation. General simulation setup This section describes the tool flow of the Sentaurus Workbench project. For each tool, the associated Sentaurus Workbench input parameters and the extracted parameters are discussed. Sentaurus Structure Editor 8.0e e e e e e e+18 The tool sequence for this project starts with Sentaurus Structure Editor (in process emulation mode), which generates the geometry of the Omega FinFET devices. 6 Copyright 2007 Synopsys, Inc. All rights reserved.

7 During the process flow execution, intermediate structures are saved for subsequent use by Sentaurus Process. Sentaurus Process Sentaurus Process loads the intermediate geometries generated by Sentaurus Structure Editor and performs the implantation and diffusion steps associated with each intermediate structure. Alternatively, all process simulations can be omitted by setting the following Sentaurus Workbench parameter: Implant_Diffuse = simulated analytic defines whether implantation and diffusion steps are simulated with Sentaurus Process or if analytic profiles are defined in Sentaurus Process. Sentaurus Structure Editor The subsequent instance of Sentaurus Structure Editor finalizes the device structure for simulation with Sentaurus Device. Contacts are assigned and the structure is remeshed with Noffset3D. Sentaurus Device Sentaurus Device simulates I d V gs curves for a low-drain bias and high-drain bias. The simulation can be performed using quantum or classical transport. The specific simulation is selected by setting the following Sentaurus Workbench parameters: Models = Quantum Classic selects if quantum or classical transport simulations are performed. Vdd [V] defines the supply voltage. Here, it is set to 1.0. Vds [V] defines the drain bias for the I d V gs sweep. Here, it is set to 0.05 and 1.0. IdVg = 0 1 is a logical flag. The I d V gs sweep is performed only if the flag is 1. Inspect Inspect plots the I d V gs characteristics and extracts: Vtgm [V]: Threshold voltage defined as the intersection of the tangent at the maximum g m with the V gs axis. Vti [V]: Threshold voltage defined as V gs at which I d = 100 na. Imax [A]: I d at V ds = Vds and V gs = Vdd. I0 [A]: I d at V ds = Vds and V gs =10mV. SS [mv/decade]: Subthreshold swing. gm [S]: Maximum transconductance. Ion [A/μm]: Imax/50 nm. Ioff [A/μm]: I0/50 nm. Tool-specific setups Sentaurus Structure Editor Process emulation mode All geometry-altering process steps (that is, Steps 1 6, 8, and 10) are modeled by Sentaurus Structure Editor in process emulation mode. In this mode, the input commands are given in a process-oriented language. For example, the command that executes the gate oxide deposition (Step 5.1) is: (sdepe:depo "material" "Oxide" "thickness" (* 2 nm)) and the commands that execute the gate definition (Steps 5.3 and 5.5) are: (sdepe:generate-mask "POL" (list (list 0 (* -72 nm) (* 22.5 nm) (* 120 nm)))) (sdepe:pattern "mask" "POL" "polarity" "light" "material" "Resist" "thickness" (* 50 nm)) (sdepe:etch-material "material" "PolySi" "depth" (* 66 nm) "overetch" (* 10 nm) "type" "iso" "algorithm" "lopx") Sentaurus Structure Editor is built around the powerful ACIS solid geometry modeling kernel, which is used in many professional CAD applications for various industries. The tremendous advantage in using ACIS solid modeling to model geometry-altering processing steps in 3D is that ACIS provides an optimized data structure for representing complex geometries. For example, curved boundaries are described as continuous analytic surfaces rather than discretized polyhedral surfaces. Sentaurus Structure Editor also allows users to take very detailed control of the geometry. For example, the rounding of the fin edges can be set explicitly. The motivation for this is: During real processing, shape corners tend to be rounded off (see, for example, the TEM graphs in the literature [2][3]). These rounding effects have a considerable influence on the electrical characteristics of the final device, because they alter the electrical field distribution and strength in the corner regions, which form parasitic edge transistors (see Results and discussion on page 10). The influence of these rounded edges can be studied precisely by explicitly selecting the rounding radius of the channel fin edges and using the fillet-edges operation of Sentaurus Structure Editor. Here, a radius of 20% of the channel width is used. Copyright 2007 Synopsys, Inc. All rights reserved. 7

8 Paint-by-numbers scheme The key element of the automated interface between Sentaurus Structure Editor and Sentaurus Process is the paint-by-numbers scheme, which for this example works as follows. Sentaurus Structure Editor saves snapshots of the device structure during the execution of the process flow for Sentaurus Process to perform the dopant-related processing steps. For the example discussed here, after the creation of the extension spacer (Step 6), a snapshot labeled ET of the structure is saved. After the creation of the source/drain spacer (Step 8), a second snapshot labeled SDI is saved. For example, the Sentaurus Structure Editor commands for saving the ET snapshot are: (sdepe:fill-device "material" "Gas" "height" gas) (part:save "n@node@_et.sat") (sdepe:strip-material "Gas") The first command adds a gas region, which is required for Sentaurus Process. The second command saves the snapshot, and the final command removes the gas region for further processing within Sentaurus Structure Editor. At the end of the flow, Sentaurus Structure Editor takes both snapshots and creates a union structure, which contains the union of all regions in both structures. The union structure is created with the commands: (sdesp:begin) (sdesp:define-step "ET" "n@node@_et.sat") (sdesp:define-step "SDI" "n@node@_sdi.sat") (sdeio:save-dfise-bnd (get-body-list) "n@node@_msh.bnd") (sdesp:finalize "n@node@_sprocess_sde.tcl") The first four commands generate the union structure and the last command creates the paint-by-numbers table, which lists all regions in the union structure, including intermediate regions resulting from the overlaying of the two snapshots. The paint-by-numbers table lists, for each snapshot, which material properties are to be assigned to each region in order to recover the device structure of the respective snapshot. For example, to recover the ET snapshot, the region corresponding to the source/drain spacer region is assigned the material property Gas, that is, it is transparent for the purpose of the extension implant. Sentaurus Process loads the union structure as well as the paint-by-numbers table using: source n@previous@_sprocess_sde.tcl init bnd=n@previous@_msh info=2 It then discretizes the union structure and creates a finiteelement mesh for the simulation of implantation and diffusion, using the internal meshing engine MGOALS. Figure 13 on page 9 shows the mesh created by MGOALS. Sentaurus Process recreates the device structure after the creation of the extension spacer by applying the material settings specified in the paint-by-numbers table for the ET snapshot. This is performed with a single, concise command: recreate_step ET Similarly, the device structure is switched to geometry after the formation of the source/drain spacer by applying the material settings specified in the paint-by-numbers table for the SDI snapshot: recreate_step SDI Another advantage of this approach is that the 3D mesh is created only once during the entire process. This is economical because it avoids the necessity to create the CPU-intensive 3D mesh repeatedly after each geometryaltering processing step. It also improves accuracy because it avoids inherent interpolation errors when mapping doping profiles from one mesh to the next. For example, here, the mesh remains unchanged when switching from the ET to the SDI snapshot. Note that Sentaurus Structure Editor is extremely efficient in modeling the geometry-altering processing steps. The modeling of the 3D geometry through the entire process flow as described in Process flow on page 3 takes less than 2 minutes on a standard desktop running under Linux. The creation of a single 3D mesh for a complex device structure can take considerably longer than that. For example, for the FinFET discussed here, MGOALS needed approximately 5 minutes to create a high-quality finite-element mesh. Common parameterization variables In the Sentaurus Workbench project, the process flow is executed by a sequence of three tool instances (Sentaurus Structure Editor Sentaurus Process Sentaurus Structure Editor). All three tool instances share the definitions of parameterization variables. To access the definitions of these variables, select in the tool row of the Family Tree view the icon of the first instance of Sentaurus Structure Editor, and right-click. From the shortcut menu, select Edit Input > Parameter. The text editor opens with the content of the file sde.par. The structure of the parameter file is: <name> <value> <unit> [<comment>] where <name> is the name of a parameter variable and <value> is the numeric value that is assigned to it. <unit> can be one of the following: micrometer (um), nanometer (nm), ångström (A), unitless, or all other units (1). Comments are optional. Lines that start with a semicolon (;) are considered comment lines. Blank lines are permissible. As an example, a subset of the parameter definitions used in Sentaurus Workbench is given here: ; Layer Thicknesses Tsub 80 nm Substrate 8 Copyright 2007 Synopsys, Inc. All rights reserved.

9 Tbox 80 nm Tsi 50 nm Tox 20 A Burried Oxide Si layer Gate Oxide completed in approximately 1.5 hours on a 2.2 GHz AMD Opteron machine under Linux, using the iterative solver ILS. ; Litho patameters LW 45 nm Lithographic Linewidth ; Simulation Domain max 0.12 um max 0.12 um ;- Omega rounding radius factor (fraction of Tnim) Rtop Rbot The parameter settings are loaded into Sentaurus Structure Editor with: (load "GEO_lib.scm") (sdemp:setunit "nm") ; Load Geometrical Parameters (define ParList (read-sp-par-file "pp@node@_dvs.par")) (map sde:define-parameter (car ParList) (cadr ParList)) The macro library GEO_lib.scm provides the support for units as well as the parameter reader read-sp-parfile. The last Scheme command map sde:defineparameter activates the parameters on the local name space. For Sentaurus Process, the corresponding procedure is: set Unit "um" set INPUTpar "pp@previous@_dvs.par" source readinput.tcl NOTE It is not necessary to declare the parameters explicitly in the Sentaurus Structure Editor or Sentaurus Process input files. In addition, this feature relies on the local files gtooldb.tcl, GEO_lib.scm, readinput.tcl, and sde.par. Figure 13 Device structure with MGOALS mesh used by Sentaurus Process; the mesh has approximately nodes. Device generation using Sentaurus Structure Editor and Noffset3D In modern, deep submicron, MOS-type device structures, the channel gate oxide interface must be resolved to a very high level of accuracy. The finite-element mesh must resolve the very steep gradients of the inversion layer. In addition, for the accurate modeling of quantization effects, it is necessary to resolve the silicon oxide interface on the silicon side with a mesh spacing in the normal direction of the order of 1 Å or 2 Å. (With the latest implementation of the density gradient model, it is no longer necessary to have a fine mesh on the oxide side of the interface in order to obtain accurate size quantization results.) Ideally, the mesh elements at the interface should be aligned with the boundary, that is, the element faces should be parallel or orthogonal to the boundary. For nonplanar, curved interfaces, this is not a trivial task. However, the Sentaurus meshing engine Noffset3D can generate such meshes. Noffset3D is used to remesh the Omega FinFET for the device simulations. Figure 14 shows the mesh created by Noffset3D. Sentaurus Process Sentaurus Process is designed as a simulator that works independently of the dimensionality of the structures to be simulated. Therefore, model and parameter settings, as well as the processing-step definitions, are the same for 1D, 2D, and 3D simulations. For the 3D Omega FinFET simulated here, the analytic implantation model is used. For the point defects, the plus one model is activated. For the activation, the solid solubility model is used. To capture the influence of the nonequilibrium point-defect concentrations on the diffusivity of the dopants (here, phosphorus, arsenic, and boron), the advanced pair-diffusion model is used. The MGOALS-generated mesh, shown in Figure 13, has approximately nodes. The 3D implantation steps require about 30 minutes and the final RTA simulation is Copyright 2007 Synopsys, Inc. All rights reserved. Figure 14 Detail of the Noffset3D mesh used by Sentaurus Device. The mesh has approximately nodes. The slice shows the boundaryconforming mesh along the center plane of the device (x=0). 9

10 Noffset3D is called from within Sentaurus Structure Editor with: (system:command "noffset3d -F tdr It must be noted that only half of the FinFET structure is created by Sentaurus Structure Editor and meshed with Mesh. It is subsequently reflected about the vertical axis to obtain the full device. The reflection is performed in Sentaurus Structure Editor by a system call to the utility Sentaurus Data Explorer (tdx): (system:command "tdx -mtt -x -ren drain=source n@node@_msh_pof n@node@_msh") The option -x instructs Sentaurus Data Explorer to reflect the device along an axis defined by x = x min. The given half-structure has three contacts (drain, gate, and substrate) that are defined in sde_dvs.cmd. Of these, the gate and substrate contacts touch the axis of reflection and, upon reflection, are extended and thereby preserve their names. However, the drain contact in the reflected half is named drainmirrored by default. This contact is explicitly renamed source with the commandline option -ren of Sentaurus Data Explorer. Device simulation using Sentaurus Device Sentaurus Device is well known for its robustness, and robustness is particularly important when simulating modern, deep submicron, MOS-type devices, where a very advanced set of transport models must be used. For example, for the Omega FinFET structure considered here, the body may not be fully depleted. Therefore, the continuity equations for both electrons and holes must be solved simultaneously. The very short gate length of 25 nm mandates the use of the hydrodynamic transport model. Further, the thin oxide thickness (2 nm) and relatively high body doping level (~5 x cm 3 ) require the consideration of quantization effects. Here, the advanced quantization model (density gradient model) is used. Unlike other approaches to model quantization effects such as 1D Poisson Schrödinger and the modified local-density approximation (MLDA), the density gradient model is also applicable to nonplanar 3D structures. Within the density gradient model, an additional partial differential equation is solved to determine the effective quantum potential. For the 3D FinFET, Sentaurus Device solves self-consistently five partial differential equations (Poisson equation, electron and hole continuity equations, electron energy balance equation, and the quantum potential equation). et for the structure with approximately nodes, the run-time for an I d V gs sweep remains reasonable (2 hours for the low-drain bias sweep and 3 hours for the high-drain bias sweep on a 2.2 GHz AMD Opteron machine under Linux, using the iterative solver ILS). Extraction and visualization with Inspect In the Sentaurus Workbench tool flow, Sentaurus Device is followed by the visualization tool Inspect, which plots the corresponding I V characteristics and extracts relevant electrical parameters as discussed in Inspect on page 7. The extraction setup used here is similar to the one discussed in Sentaurus Technology Template: CMOS Characterization. Refer to the documentation for that project for details about visualization and parameter extraction. Results and discussion Figure 15 shows the electron concentration at four cross sections of the fin for the bias point V gs = V ds = 1 V. It can be seen that the carrier concentration is not uniform along the perimeter of the fin (channel). The highest concentrations are found near the four corners of the fin. For this reason, an accurate control of the shape of the fin corners is important for the accurate modeling of Omega FinFETs. The slice at the drain side (12.5 nm) shows a reduced electron concentration due to the pinch-off. 25 nm Electron Density [cm-3] 12.5 nm 0 nm 1.5e nm 1.1e nm 7.7e e+18 Figure 15 Electron concentration at four cross sections of the fin for the bias point V gs = V ds = 1 V. Slices are taken at the middle of the channel (0 nm), at the edges of the gate ( ± 12.5 nm), and inside the extension area ( 25 nm). ± Figure 16 on page 11 shows a two-dimensional cut of the electron distribution at the center of the device from source to drain at the bias point V gs = V ds = 1 V. The top graphic shows the results of a quantum transport simulation (that is, with the density gradient model), while the lower graphic shows the corresponding classical results. It can be seen clearly that the peak of the electron distribution for the quantum transport simulation occurs approximately 7 Å away from the silicon oxide interface, while for the classical simulation, the peak is at the interface. This is the result of the quantum-mechanical size quantization in the high transversal field of the channel. 10 Copyright 2007 Synopsys, Inc. All rights reserved.

11 QT Source Channel Figure 16 Electron concentration in the FinFET for the bias point V gs = V ds = 1 V for a cut along the center plane (y=0) from source to drain; (top) quantum transport and (bottom) classical transport. Figure 17 shows the low-drain and high-drain bias I d V gs as simulated with Sentaurus Device. The resulting key electrical parameters are mostly similar to the experimental values reported in the literature [2]: Threshold voltage V t = 318 mv I on = 995 μa/μm I off = 5 na/μm DIBL = 66 mv/v Cl Electron Density [cm -3 ] 1.2e e e e Subthreshold swing = 71 mv/decade (Following [2], the drain currents were scaled with the silicon layer thickness of 50 nm and not with the fin circumference.) Current [A] Figure 17 current as function of gate voltage for a drain bias of 50 mv (blue) and 1 V (red). Solid lines are quantum transport (including the density gradient model) and dashed lines are classical transport. References QT 50 mv QT 1 V Cl 50 mv Cl 1 V Gate Voltage [V] [1] The process flow considered does not contain an oxidation step. See Sentaurus Suite of TCAD Products in Version , TCAD News, October 2005, for a discussion on simulation of 3D oxidation with Sentaurus Process. [2] F.-L. ang et al., 25 nm CMOS Omega FETs, in IEDM Technical Digest, San Francisco, CA, USA, pp , December [3] F.-L. ang et al., 35nm CMOS FinFETs, in Symposium on VLSI Technology, Honolulu, HI, USA, pp , June The dashed lines in Figure 17 show the corresponding results of a classical transport simulation (that is, omitting the density gradient model). It is clear that quantum effects lead to a threshold voltage shift of 60 mv. For this device, this corresponds to 20% of the threshold voltage, underscoring the importance of quantum transport simulations for modern CMOS devices. When using analytic doping profiles, the threshold voltage is 20% lower compared to runs based on simulated profiles, because the effects of boron redistribution as discussed at the end of Process flow on page 3 are neglected. Copyright 2007 Synopsys, Inc. All rights reserved. 11