Simulation and Modeling Techniques for Compact LTCC Packages

Transcription

1 Simulation and Modeling Techniques for Compact LTCC Packages Ted A. Miracco, Lloyd Nakamura, Malcolm Edwards Applied Wave Research, Inc East Grand Avenue, Ste 430 El Segundo, CA Tel , Fax Abstract LTCC design methodologies using high-frequency Electronic Design Automation (EDA) tools have been a topic of debate among both designers and EDA tool suppliers. Unlike proven design methodologies for printed circuit boards (PCBs) and integrated circuits (ICs), LTCC design poses additional challenges because of the required flexibility in simulation, three dimensional layout and integration. LTCC designers are faced with very dense multilayer modules that require a flexible and configurable layout editor and a combination of simulation technologies to model geometrically complex 3D structures. A typical LTCC design problem is the design of a compact global system for mobile communications/digital communications system (GSM/DCS) diplexer using vertically integrated inductors and capacitors. This design problem illustrates the requirement of tightly integrated electromagnetic (EM) and linear circuit simulators, as the extraneous interactions between inductors, capacitors and interconnect cannot be accounted for using only a linear circuit simulator. EM simulators alone, however, are computationally expensive and completely inadequate for design synthesis, whereas linear simulators can leverage tuning, optimization, and statistical analysis which are critical for most circuit design problems. Therefore, an integrated solution that combines both linear and EM simulation is ideal for this problem. The layout editor for the LTCC design must also be tightly integrated with the simulators as the routing of interconnect in three dimensions is critical in determining the circuit performance. In this paper, a design methodology is presented for a GSM/DCS diplexer design using a highly integrated EDA solution with an architecture that is open to customization for LTCC components. Key words: Electronic Design Automation (EDA), Simulation, Electromagnetic, Layout. Low temperature co-fired ceramic (LTCC) modules are emerging as an important solution for wireless applications based upon competitive advantages in size, cost and time to market [1]. Despite the many advantages, LTCC development is undermined by a variety of unique technical challenges that limit the impact of electronic design automation (EDA) solutions. Traditional EDA tools have typically been hard wired to address either printed circuit board (PCB) design or integrated circuit (IC) design, neither of which provides all the essential features or functionality to be effective in designing LTCCs. Although LTCCs combine some of the characteristics of both dense printed circuit boards (PCBs) and integrated circuits (ICs), effective simulation requires capabilities that go beyond either of these standard design methodologies. Deficiencies in typical EDA solutions for RF module design can generally be classified into three categories: simulation issues, layout issues, and integration issues. The critical requirement for effective LTCC development is an EDA solution that combines the essential simulation technologies with comprehensive and flexible layout capabilities. Some of the issues today that undermine LTCC development are insufficient or inefficient abilities to model the interconnect and associated parasitics related to dense module development. Validity Range of Transmission Line Models Full Wav e Distributed RLGC Distributed RLC Distributed RC Lumped RC Lumped C Frequency Figure 1: Ideally, an EDA solution should provide multiple levels of abstraction for transmission lines such that engineers can trade off accuracy and computational efficiency. Although some frequency-domain and time-domain (SPICE) simulators include transmission line and even coupled transmission line models, the geometric complexity of LTCC layouts ultimately requires planar 3D electromagnetic (EM) simulation in addition to standard models or parasitic extraction

2 methods. It is ideal to have access to multi-level modeling approaches [2] as indicated in Figure 1, such that the user can make trade-offs in simulation accuracy vs. the computational efficiency as a design progresses from concept to final mask generation. Electromagnetic analysis is not only essential to final validation of a design, but ideally can be combined with circuit simulation to provide an interactive design methodology that supports real-time tuning and optimization. In addition, the EDA tools should address the statistical variations and process corners that occur in volume manufacturing of LTCCs. A best case scenario can provide multiple EM solvers that are all integrated with general purpose circuit simulators to eliminate the possibility of error in importing simulation data, and provide a mechanism for easily comparing results from a variety of solvers. To demonstrate the design process we will use a simple passive discontiguous narrowband GSM/DCS diplexer circuit. The LTCC design methodology will be built using a design environment and simulation tools from Applied Wave Research s (AWR TM ) and will leverage interfaces to third-party EM simulation tools, including a parasitic extractor, NetAN TM, from OEA Inc and a planar EM simulator, em, from Sonnet Software. Developing an LTCC Process Design Kit The first step in establishing an LTCC design methodology is development of a process design kit (PDK). PDK development involves building a custom library of electro-physical models supported by the specific process. In addition to processspecific models a customized layers file (LPF) must be created based upon the specific dielectric and metallization layers chosen for the design. The layers file will be utilized by both the simulation and layout tools to synchronize the placement of components within the dielectric stack up, and provides for the ability to easily cut and paste layout geometries into an EM simulator(s) for final verification. One of the many advantages of LTCCs is the ability to create highly compact designs by leveraging the large number of layers at the engineer s disposal. In this case we will select a 14-layer LTCC structure as it will allow sufficient vertical separation to isolate the two filter sections using a ground plane. By effectively isolating the filter sections, we can minimize the extraneous coupling between components and minimize the need for computationally expensive full wave 3D EM analysis. Figure 2: Compact vertical inductors reduce size and cost of LTCC components. User-Defined EM-Based Models/Cells To take full advantage of the LTCC process it is essential to develop a set of custom models for structures that go beyond the standard microstrip, stripline and coplanar waveguide elements in most standard RF EDA solutions. In the case of our GSM/DCS diplexer, we will require compact inductive and capacitive elements that maximize the opportunity of utilizing the Z-plane. While it would be possible to create the two-layer rectangular microstrip inductors that are popular in monolithic microwave integrated circuits (MMICs), it is far more cost effective to build the inductor on successive vertical layers in an LTCC process as seen in Figure 2. The challenge in doing so, of course, is that while many years of research, tests and measurements have been applied to modeling planar GaAs spiral inductors, each LTCC process is unique and foundries must invest in characterization of the vertical spiral structures for engineers to take advantage of the process. In most cases LTCC foundries have utilized either 3D EM simulators or measurements to generate fixed artwork cells that are tied to s-parameter data. However, in the case of the narrowband diplexer, it is highly desirable to have access to accurate continuously scalable parametric models such that the performance can be tuned or optimized for the frequencies of interest. Creating the vertical spiral model is accomplished by first running the AWR Model Wizard application which will automatically generate C++ code based upon a set parameters and a topology specified by the user in the form of a netlist. The resulting compiled model is programmed to leverage a built-in 2D quasistatic EM cross-sectional solver [3] which will

3 0 account for the coupling between all the parallel segments of Comparison of Vertical Spiral Simulations S(1,1) EM Simulation S(1,1) Circuit Simulation S(2,1) EM SImulation S(2,1) Circuit Simulation Swp Max 10GHz Swp Min 0GHz Figure 3: Validation of the vertical inductor model where the circuit based model is compared from DC to 10GHz against a full wave EM simulation using AWR s EMSight solver. the spiral. Upon compilation the user needs to place an independent dynamically linked library (DLL) element into a models directory to gain access to this new element. The key difference between the results is in simulation time. The circuit based model solves in a few seconds while the full wave EM simulation takes approximately 10 minutes for a comparable number of frequency points. Both representations provide consistent results as can be seen in Figure 3 Another element required for the diplexer is a multilayer parallel plate capacitor. The electrical representation, depicted in Figure 4a (below), PORT NVIABR PC1LIN PCLINE CAP Figure 4: A multilayer capacitor can be electrically modeled using a series of standard elements including a quasi static transmission line and coupled transmission line models (4a) and a corresponding compiled parametric layout cell (4b) is used to generate the physical representation. is implemented as a parametric sub-network containing transmission lines and capacitors from the standard element catalog. The corresponding parametric layout cell generator is created using C++ routine that is compiled and loaded into the program with the user defined models. This compiled model library has many advantages for the LTCC foundry and designers including performance, accuracy, distribution and protection of intellectual property (IP). In terms of performance a compiled model will execute more efficiently than an interpreted version of the same model. In addition, because the model is based on EM first principles, it should be more accurate and have greater dynamic range than closed-form equations which are usually based upon a limited data set. An additional benefit of compiled DLLs is distribution, as the files are small enough to be distributed as an attachment and can easily be updated if there are process changes or new models. Lastly, compiled models protect the IP of the model developer as other parties cannot easily decompile the underlying code. NVIABR PCLINE CAP PCLINE CAP NVIABR PC1LIN PORT Implementing the Diplexer Design in LTCC Once the basic building blocks for the design are in place, it is straight forward to move from concept to implementation. The basic element values are determined using a Filter Wizard to establish ideal values for the inductors and capacitors of the two filter networks. Because the diplexer is discontiguous it is not necessary to be overly concerned with the impedances at the junction of the two filters provided the connections to the first resonator are electrically

4 small. The only decision is determining how many filter sections are required to meet the -20 dbm isolation requirements for the diplexer, and, because we can expect some degradation of the design from stray coupling and manufacturing variations, it is prudent to add additional filter sections to provide a sufficient margin for implementation. Figure 5 Layout implementation of GSM filter section using LTCC components. From this point the diplexer is constructed by connecting the ideal filters and analyzing the structure with a linear circuit simulator to determine if it meets all the specifications. Next, the ideal inductors and capacitors are replaced with the LTCC elements, as seen in figure 5, and the parameters are adjusted to match the ideal values from the synthesized networks. Circuit simulation of the LTCC implemented design typically results in some disparity from the ideal model as seen in Figure 6. At this point it is possible to either tune on the element values to restore the correlation of the two structures, or use the optimizer to accomplish the same goal Comparison of Ideal and LTCC Filter with Layout 1.65 GHz db 1.7 GHz db Figure 6 Physical implementation of the LTCC filters results in degradation in transmission and rejection characteristics. Discrete Value Optimization for EM Analysis Full wave EM simulators are required to take into account all of the extraneous coupling between the interconnect and the LTCC cells. Although full wave methods of moment (MoM) simulators are available in both gridded and non gridded formulations it has been determined that the gridded methods have greater accuracy and dynamic range vs. the more geometrically flexible non-gridded approaches [5]. However, optimizers are typically geared to continuous functions. This can result in values that force the user to compromise between either long simulation times that result from a fine grid or inaccurate results stemming from descritization error due to non-conformance of the structure with the EM grid. This problem can be mitigated or completely eliminated by utilizing a discrete value optimization algorithm that will adjust the structure in specific increments that correlate with the selected grid of the EM simulator. Use of this technique significantly reduces the design cycle by cutting the time/em iteration, while dramatically increasing overall confidence in the design process. Space Mapping and Decomposition It is also possible to combine circuit simulation in concert with EM simulation to rapidly assemble the building blocks of the diplexer through a technique called space mapping and decomposition [6]. This approach uses the EM simulation sparingly as a means to calibrate a computationally more efficient circuit based simulation. Applying this approach to the filter designs is best accomplished by breaking the filter designs into physically isolated components and comparing the resulting s-parameters from EM simulations to the circuit based approach. Next, we take the delta between the two sets of s-parameters and cascade it with the circuit simulation results to re-calibrate them to match the EM results. This new circuit based network provides an accurate and efficient means to re-optimize the design for final assembly DB( S(2,1) ) DCS layout DB( S(2,1) ) DCS Frequency (GHz) Final Validation Using EM Socket With the emergence of open computing standards, such as Microsoft s Component Object Model (COM), it is possible to tightly and seamlessly integrate simulators from multiple vendors within a common design environment. The AWR architecture includes a COM-based EM Socket TM interface that acts as a server such that structures can be simulated

5 with third-party solvers in addition to the native EMsolver built into the AWR environment. Figure 7: Electromagnetic simulation of a filter section indicates stray coupling qualitatively, while providing quantitative data for recalibrating the circuit based results for final optimization. Figure 7 Completed layout for compact GSM/DCS diplexer can be validated using a variety of EM solvers accessible through the EM Socket interface. Statistical Design and Process Corners Despite the fact that a complete EM simulation of the entire design structure meets specifications, it is by no means a guarantee the circuit will provide a high yield in a manufacturing environment. To verify that the design is reproducible we must enter the statistical tolerances and distributions for all the underlying parameters in the network and run either a Monte Carlo analysis or corner analysis to see if the design remains within specifications under worst case conditions. It is especially important to consider variations in global parameters such as dielectric constant, layer thickness, and etching tolerance as each of these parameters will affect many components in a correlated manner. This provides a mechanism for engineers to validate results with multiple EM solvers. In the case of the diplexer structure electrically small sections of the filters were analyzed using the EMSight TM MoM LTCC Diplexer DB( S(2,1) ) DB( S(3,1) ) As the individual structures were integrated into larger super-structures it was possible to leverage the EM Socket by choosing the 3D planar em solver from Sonnet Software. By selecting Sonnet as the primary solver, we take advantage of unique features that assist in analyzing the complete diplexer layout. The Sonnet solver includes both a conformal meshing algorithm [7] and an adaptive band synthesis (ABS) algorithm [8] which provides significant speed advantages that facilitate analysis of the entire LTCC structure. The final EM analysis provides for validation of the complete design; however we must still take into account the variations in the manufacturing process Frequency (GHz) Figure 8: Final Validation requires both full wave EM analysis and yield analysis to take into account manufacturing tolerances. Conclusions In this paper we demonstrated the use of a modern EDA architecture to facilitate the analysis of dense LTCC structures. Enabling technology included: an open product architecture that facilitated the creation of a robust LTCC PDK through user defined electrical and physical models; discrete value optimization to efficiently take into account the effects of interconnect and parasitic layout issues with EM simulations and an EM Socket interface to leverage 3 rd party solvers. In addition, we combined simulation technologies through space mapping to optimize the final design using both EM and circuit solvers. Lastly we incorporated the statistical variations of the manufacturing process to verify the manufacturability and yield of the final design.

6 References: [1] James Spoto, "Looking Beyond Monolithic Myopia", IEE Electronics Systems and Software, August/September [2] Francese Moll, "Interconnection Noise in VLSI Circuits", Kluwer Academic Publishers, Boston, Chapter 2, pp , [3] M.B. Bazdar, A.R. Djordjevic, R.F. Harrington, and T.K. Sarkar, "Evaluation of quasi-static matrix parameters for multiconductor transmission lines using Galerkin's method," IEEE Trans. Microwave Theory Tech., vol. MTT-42, July 1994, pp [4] James C. Rautio, Testing Limits of Algorithms Associated with High Frequency Planar Electromagnetic Analysis, presented at the European Microwave Conference, October [5] Martin Versleijen, Design Technology Challenges for RF Modules, presented at the International Microwave Symposium, June [6] John Bandler, Design Optimization of Interdigital Filters Using Aggressive Space Mapping and Decomposition, IEEE Transactions On Microwave Theory And Techniques, Vol. 45, No. 5, May [7] James C. Rautio, A Conformal Mesh for Efficient Planar Electromagnetic Analysis, IEEE Transactions On Microwave Theory And Techniques, January [8] James C. Rautio, EM Approach Sets New Speed Records, Microwaves & RF, May 2002