O N C A D E N C E V I R T U O S O. CHEN, Jason Application Engineer, Keysight Technologies

Transcription

1 O N C A D E N C E V I R T U O S O CHEN, Jason Application Engineer, Keysight Technologies

2 Introduction to Momentum Momentum Features for RFIC Design Circuit/EM Cosimulation Flow on Cadence Virtuoso Conclusion 2

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4 Support Arbitrary Multi-layer structures High accuracy simulation for complex parasitics and EM coupling effects. Integrated in both ADS and Virtuoso Environment. Essential for passive components, patch antenna simulation and verification in RFIC, MMIC, PCB and RF modules. 4

5 ADS 201x Virtuoso IC / 6.x 3D Viewer BroadBand Spice Model Generator.subst.ltd 5

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7 Lateral coupling Open Boundary Vertical coupling Vias Dielectric Layer1 Dielectric Layer2 Delectric Layers are extended to infinity Different materials on the same Z-coordination is not supported Arbitrary conductors crossing layers are not supported 7

8 S I D E W A L L C U R R E N T O F T H I C K C O N D U C T O R S Sidewall current flow, including vertical and horizontal, of thick metal is considered Top Bottom horizontal Sidewall vertical Sidewall horizontal ground plane Sidewall coupling effect can be simulated. 8

9 T H I C K C O N D U C T O R M O D E L Thick conductors can be analyzed in Momentum 3 Types of setting for Conductors 1. 3D Distributed Current densities of top, bottom and sidewall are all considered. Recommended Setting 2. 2D Distributed Only vertical current is considered at sidewall 3. Sheet Sidewall current is not considered Used for specific conditions Mesh shield GND Slow wave GND Patterned GND for eddy current reduction 9

10 V I A M O D E L 1. 3D Distributed Model Vertical and Horizontal current of vias are considered For high accuracy 2. 2D Distributed Model Vertical current of Vias are considered Recommended for IC. Usually via array is simplified to single via. There is no horizontal current of merged vias. 3. Lumped Model Vias are replaced with LR lumped model. Meshes are not generated for vias. Mutual inductance and self, mutual capacitance are not considered. 10

11 R F M O D E A N D M I C R O W A V E M O D E SPICE Momentum RF Momentum MW Spice model S parameters RF S parameters MW Frequency indep. L.... Frequency indep. C.... DC Conductor Loss(s).. DC Substrate Loss(s).. Loss tangent Skin Effect Substrate Surface Radiation Space Radiation MicroWave Mode=Full Wave RF Mode= Quasi-static 11

12 F R E Q U E N C Y R A N G E O F R F M O D E Limit of Layout Size (Space radiation can be ignored) D Dimension WaveLength 2 C light 2 Freq Limit of Substrate Stack-up (Surface radiation can be ignored) Freq [GHz] Thickness < 150 D [mm] Wavelength a (e r -1) The frequency range for RF mode will be shown in Status Window when running simulation. T e r a = 20 (with ground plane) a = 10 (without ground plane) Freq [GHz] < 300 a (e r -1) T [mm] 12

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14 Cadence display.drf Support IC Interoperability Automatic Substrate Generation Metal Bias and Temperature Effect Layout Simplification Coilsys 14

15 ADS Layout Window Virtuoso Layout Window 15

16 Solving complex SiRF IC design challenges while working seamlessly of a single ADS / Virtuoso OA library Schematic and layout design optimization in ADS on OA library (EM & ETH-cosim, module and system level). Improved design efficiency and faster time to market while using RF-centric design tools at a competitive cost. Foundry PDK s & Rule Decks Forward looking nmdrc, nmlvs, PEX Calibre Interactive / Assura Schematic / Layout Virtuoso OA PDK + ADS callbacks & pcells Schematic / Layout ADS 2016 Virtuoso IC 6.1 CMOS SOI antenna switch Fan-out WLCSP Multi-technology PA module 16

17 I T F & E N C R Y P T E D I R C X Automatic substrate generation for EM from foundry ICT (Cadence) and ITF (Synopsys) formats Similar to TSMC s ircx importer of ADS2016 Optionally generates Momentum module 17

18 W I T H I T F O R I R C X EM simulation takes into account under/over etching of metal ircx and ITF files provide metal bias tables (GF and TSMC usually) Metal bias tables specify the actual line width and spacing with respect to the drawn width and spacing With metal bias Without metal bias 18

19 Momentum accounts for temperature-dependent conductor resistivity Substrate Editor Layout Simulation Circuit/EM Cosimulation 19

20 Computing Time Better accuracy, longer computing time Computing time is highly relative to number of meshes What s Mesh? Meshes are the divided elements of specific structures For larger layout, number of meshes also become larger For RFIC Although the layout size is small compared to wavelength, higher complexity leads to larger number of meshes. Layout simplification is required to reduce number of meshes without loss of accuracy 20

21 V I A A R R A Y Layout simplification for best speed and accuracy trade-off. Guidelines of Simplification Keep original layout of critical path If there are relatively thick and large ground patterns, current change on other pattern due to layout simplification is relatively small. GND Vias are used to make sure all GND patterns are at the same potential. Most current flow on thick metals and only few current flow in vias. It s better to merge Via array to single via. Via Merge Original Layout Simplified Layout 21

22 V I A A R R A Y Pcell is supported. Original layout is unchanged. Simplification is performed in background. The result of simplification can be checked and adjusted. Check in 3D viewer Display the simplified structure Pcell Can be adjust after check Simplified Model Simplification Setting (Stored in State) Via Simplification Dummy Metal Fill Option 22

23 V I A A R R A Y One more simplification method Number of meshes is less NEW Increment/clip to Lid Boundary 23

24 M E T A L F I L L 1. Metal Fill Modeling Approach 1. Ignore 2. Equivalent dielectric constant (doesn t affect memory & simulation time) Assume metal fill is uniform 3. As original layout (memory consumption and simulation time is affected) For arbitrary metal fills 2. Metal Fill Presence 1. Assume is not existed if not drawn 2. Using layer purpose 3. Using pattern size 24

25 M E T A L F I L L M O D E L I N G Used when unrelated metal (=metal fill) are existed 25

26 M E T A L F I L L M O D E L I N G : R E M O V E U N R E L A T E D M E T A L Remove unrelated metal: Ignore metal fills The effect of metal fills are not considered. Metal fill layer 26

27 M E T A L F I L L M O D E L I N G : R E P L A C E D B Y E Q U I V A L E N T L A Y E R Replace by equivalent layer: change dielectric constant to equivalent value. Simulation time is the same. Metal Fill effect is considered Metal fill layer er: 3.9 XXX is calculated at the background. Related to Area fill fraction 27

28 M E T A L F I L L M O D E L I N G : K E E P U N R E L A T E D M E T A L Keep unrelated metal: solve metal fills as normal patterns. Use new algorism for unrelated metal. Less memory consumption and lower simulation time than previous version. 28

29 A U T O M A T I C I N D U C T O R D E S I G N E R 29

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32 E M _ E X T R A C T E D V I E W G E N E R A T I O N Framework Virtuoso ADS Virtuoso Flow Create / Edit Top Design in Virtuoso Open in ADS Perform EM Partitioning Generate Views New Perform EM simulation Simulate in ADE New OA database Top Layout Top Layout Top EM Setup Top em_extracted Top_emcosim layout Top em_extracted Top_emcosim emmodel Top_emcosim emmodel Top_emcosim emmodel Express Pcell Plug-in Top_emcosim layout Express Pcell Plug-in 32

33 S T A R T F R O M V I R T U O S O L A Y O U T A N D O P E N I N A D S Top:layout in Virtuoso Top:layout* in ADS Layout and instance parameterization will be evaluated when the Top:layout express Pcells are created in Virtuoso or when ADS first uses the Top:layout view and they cannot be changed after that anymore. *Layout must be writeable if you need to edit the port setup 33

34 C R E A T E E M S E T U P V I E W A N D C O N F I G U R E T H E S E T U P Top:layout Top:emSetup Define partitioning E.g. 2 transistors and 2 mimcaps will be circuit-simulated Substrate, Simulation Options, Including proper ADS layer binding! Open the Port Editor and check/update the port definition Global scope added to override all port definitions Optionally modify the EM Model simulation setup 34

35 A U T O - C R E A T E T H E C O S I M U L A T I O N I T E M S After the user clicks Go, the following items will be auto-created: the auxiliary EM-modeling cell (Top_emCosim) with the proper CDF data the following views layout (Layout) emmodel (EM Model) spectre (symbol/cds simulation stop view) extra virtuoso cosimulation cell views: Top:emExtracted (Layout) 35

36 G E N E R A T E E M M O D E L D A T A Generate EM Model data Launch Momentum/FEM by clicking Evaluate model for default parameter values on the Database tab. Optionally included with cosimulation view creation to reduce number of clicks 36

37 T O P : E M _ E X T R A C T E D V I E W F O R S I M U L A T I O N This view can be the View for simulation in Cadence Similar to Assura-Virtuoso s av_extracted view. This auto-generated Layout view contains: The circuit-modeled component instances The em-modeled TopCell_emCosim instance The pins of TopCell:layout 37

38 R U N S I M U L A T I O N I N C A D E N C E A D E Instantiate the Top:symbol in a cadence testbench:schematic Run the simulation in ADE em_extracted must come upfront in the switch view list The EM Model view will be a stop view for spectre or GoldenGate 38

39 In this presentation, we have introduced Basics of Momentum Momentum Features for RFIC Design Circuit/EM cosimulation flow on Virtuoso With IC interoperability, users can choose Keysight solutions for advanced analyses, such as IC/Package EM simulation Electro-Thermal simulation System-Level analysis Useful tools in ADS (Loadpull, built-in display templates) 39

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