Introducing Virtuoso RF Designer (RFD) For RFIC Designs

Transcription

1 A seminar on Cadence Virtuoso RF Designer is scheduled for March 5, To know more, write to Brajesh Heda at Introducing Virtuoso RF Designer (RFD) For RFIC Designs Introduction Virtuoso RF Designer Team Parasitics have a first-order impact on RF circuit performance. These parasitics include interconnect parasitics as well as coupling among passive devices, interconnects themselves, and ground planes. Furthermore, the layout density and GHz range operating frequency introduces numerous high frequency effects including time retardation, the skin effect, substrate effects and harmonic resonances. It is essential to accurately predict parasitics and the numerous high frequency effects while designing RF integrated circuits (RFICs). A traditional RFIC design flow involves schematic design and simulation, followed by layout, then by post-layout verification and extraction. However, this traditional flow usually leads to multiple iterations between schematic and layout designs and ends up with inaccurate prediction of circuit performance and ultimately to longer time to market. The Virtuoso RF Designer (RFD) full-wave electromagnetic (EM) solver is a 2.5D EM field solver utilizing fast Method of Moments (MoM) technique with adaptive and parallel frequency sweep. It is tightly integrated with Cadence s Virtuoso design environment making it the only practical full-wave solver that can be used both as a designer s tool as well as a characterization tool. The RFD solver and its environment stand out from its competitors in several aspects. It is the world s first and only multi-layer Pre-corrected Fast Fourier Transform (PFFT) accelerated MoM solver. In conjunction with PFFT acceleration, the solver leverages your distributed computing infrastructure by interfacing to common load balancing tools such as LSF and Grid Engine. This allows customers to take advantage of their farm machines. Furthermore, because of its tight integration within Cadence s Virtuoso environment the designers can stay in their design environment and avoid time consuming and error-prone tasks like GDSII streaming, manual simplification of via geometries and manual back-annotation of solver results (stitching of s-parameters for running circuit simulation). This makes RFD the IC designer s tool of choice. Virtuoso RFD offers the modeling capacity to tackle large physical geometries. The solver s computational complexity scales as O(NlogN) with the problem size N, whereas almost all traditional solvers scale as O(N 2 ) or O(N 3 ). Hence, requirements for CPU time and memory for the RFD solver does not increase quadratically as the problem size becomes larger, but rather the increase is almost linear. This allows the RFD solver to handle more complex components and even complete RF layouts at the cell level (LNAs, Mixers, VCOs, etc.) where almost all other competitors will fall short. In this paper, we will provide a technical overview of the RFD solver. The paper will also highlight the advantages of using the RFD solver and its use in the RFIC design environment as compared to some of the existing full-wave solvers in the market today.

2 Challenges and Applications for Electromagnetic Field Solvers in RFIC Designs Parasitics have a first-order impact on RF circuit performance. These parasitics include interconnect parasitics as well as coupling among passive devices, interconnects, and ground planes. Traditionally, EM solvers were more commonly used in Monolithic Microwave Integrated Circuit (MMIC), board, and package designs. However, as the process node shrinks from 180nm to 90nm to 65nm and to even smaller values, and as the design frequency continues to rise to several GHz, the need for using EM solvers in modern RFIC design flows is becoming acute. The most common application for EM solvers in IC and package design is to solve interconnect type problems, which include transmission lines, inductors, Metal Insulator Metal (MIM) capacitors and package traces. Each of these problems requires the modeling of metal interconnects with skin effect and proximity effects. These metal interconnects were usually modeled as metal sheets, using one sheet for the so-called thin metal model and adding additional sheets to capture the thickness of the metal. However, as can be seen from Figure 1, the width to height and the width to spacing ratios for such metal lines are becoming less than 1, thus requiring accurate 3D modeling of the lines, including current flowing on the sidewalls. Figure 1 3D Metal in modern processes (source Intel) At the same time, the process itself is getting complicated with conformal or non-planar dielectrics, deep trenches, sinkers and wells. Newer design rules are mandating slotting in the metal and dummy metal fills. Furthermore, RF designs are now being done on lossier substrates such as CMOS which needs additional techniques like multiple layers, shields, and guard rings to maintain quality factors for inductors. Also, the design frequency is increasing. A typical operating frequency now resides at 3-5 GHz, which means that the third harmonics are very close to 20 GHz. As a result, quasi-static field solvers, electric or magnetic, are no longer accurate enough at the

3 frequencies of interest. More RFIC designers are turning to full-wave solutions to meet accuracy requirements. Electromagnetic Field Solvers in the Market Traditionally, it has been difficult to use EM solvers in an RFIC design flow due to lack of integration with the design environment and insufficient speed and capacity. That is why EM solvers have been historically treated as stand-alone tools that require deep domain expertise to operate successfully. Ansoft HFSS is a general purpose Finite Element Method (FEM) solver capable of accurately modeling true 3D structures. The FEM technique is a differential equation technique which requires the discretization of the entire problem space by a volumetric mesh, making it computationally prohibitive for IC design applications. The other popular technique is the Method of Moments (MoM) technique, which is an integral equation technique. It is used by Agilent Momentum and Sonnet. The MoM technique is computationally more efficient. Also, it is very well suited for planar dielectric materials making it an ideal candidate for solving IC and packaging problems. However, the main bottleneck for MoM is its full matrix. Traditional MoM solvers have O(N 2 ) memory requirements and need O(N 2 ) or O(N 3 ) solution time, where N is the number of unknowns. Without a faster algorithm, MoM solvers face a challenge when applied to RFICs. Technical Overview of the Virtuoso RFD Solver Multi-Layer Green s Function With PFFT Accelerated GMRES Solution Virtuoso RFD is a 2.5D, full-wave EM field solver that utilizes a fast Method of Moments (MoM) technique that supports both adaptive and parallel frequency sweeps. As shown below in Figure 2, MoM solvers decouple the dielectric media and the metal and via layers. The multi-layer dielectric media is solved by the Green s function. The metal interconnects are meshed and then solved. Because MoM solvers only mesh the metal interconnects, they have a lot fewer unknowns than their FEM counterparts, which is an advantage. MoM solvers can solve the resultant matrix using direct methods, like factorization or decomposition, or iterative methods. While direct solvers are very dependable, they are limited by the matrix size, thereby making them unusable for larger problems such as those faced by RFIC designers. Iterative solvers, on the other hand, can handle much larger problems typically found in today s designs. The RFD solver utilizes the generalized minimal residual (GMRES) method for its iterative solver. Even though the number of unknowns is less, a MoM matrix is a full matrix. Filling and solving that matrix is the main challenge for MoM solvers. There are several techniques available for speeding up the matrix solution, among which Fast Multipole Method

4 (FMM), Singular Value Decomposition (SVD), and QR decomposition are some of the common ones. Figure 2 Decoupling dielectric and metal in MoM solvers The RFD solver utilizes pre-corrected FFT to accelerate the dense matrix-vector product associated with the iterative solution of the discretized electric field integral equations (EFIE) while maintaining accuracy. [1] Unlike the fast multi-pole algorithm, the multiplane PFFT method does not experience any complications with the incorporation of layered media Green s function in the computational kernel, thus localizing the unknown field quantities only to the conducting surfaces of the circuit. This allows for the creation of a pre-computed database of Green s function samples describing elementary interactions in the semiconductor substrate. The Green s function samples are stored in a database for use in subsequent simulations. Therefore, the PFFT algorithm reduces the computation order from O(N 2 ) to O(NlogN), where N is the number of unknowns. Figures 3 and 4 below illustrate the performance of the RFD solver compared with traditional solvers in terms of CPU time and memory requirement.

5 Figure 3 Comparing CPU time versus number of inductors Figure 4 Memory requirements versus number of inductors modeled Conductor Modeling In MoM solvers, metal layers are modeled in one of the following ways: A metal layer can be modeled as a thin metal, which assumes no current inside the metal. In this case, skin depth is ignored. This holds true for lower metal layers (M1-M3) in typical IC processes where the thickness is ~0.2 um. Q factor prediction can be significantly off if thin metal modeling is used for RF inductors. A metal layer can be modeled as thick metal. This is needed for higher metal layers in typical IC processes (M4 and higher) where the thickness is ~1.0 um or higher. Sonnet utilizes a multi-sheet technique to model thick conductors. The disadvantage of the method is that the size of the problem is proportional to the number of sheets, which can become prohibitively large. Momentum uses two

6 sheets with via walls to do thick metal modeling. RFD also uses the two sheet approach where the two sheets have a coupling coefficient. The thick metal model can provide a much better prediction of the Q factor than the thin metal model. Finally, a metal layer can be modeled as 3D with top and bottom sheets and side walls. This is especially important if width-to-thickness and spacing-to-thickness ratios for metal layers can be close to or even below 1. Momentum uses a sidewall model to handle thick conductors, but it models the horizontal currents only. In addition, the problem size is limited because it is not accelerated by fast solver. The RFD solver uses Multi-plane PFFT to handle general 3D metal structures. RFD currently has an Engineering build with the side wall feature that has already been verified with measurement data from several foundries. With 3D side wall modeling very accurate Q prediction is possible. Figure 5 below shows a summary of the different modeling techniques for metals in MoM solvers. Note that the 3D modeling can be achieved by (a) top and bottom sheets with side walls, (b) multiple sheets, and (c) volumetric current modeling. Figure 5 Summary of different modeling techniques for metal layers in MoM solvers Figure 6 below shows the current crowding on the side walls of a 65nm on-chip inductor. As can be seen, the current hot spots are actually on the side walls and without modeling this current the Q prediction will be seriously off.

7 Figure 6 Current crowding on the side walls of a 65nm on-chip inductor Figure 7 below shows Quality factor (Q) and inductance (L) values for a similar inductor and compares measurement, RFD solution without side walls, i.e., thick metal modeling (VRFD-2D), and RFD solution with 3D side wall modeling (VRFD-3D). As can be seen, both peak Q and self-resonant frequencies match better with measurement when 3D side wall modeling is used. Figure 7 Comparing Q and L values derived from measurement, RFD-2D (thick metal) and RFD-3D (with side wall) simulations for an on-chip inductor (65nm) Integration of RF Designer in Virtuoso A big barrier in using EM solvers as a design tool within an RF design flow is their lack of integration with a design environment. Historically, EM solvers have been treated as stand-alone tools, thus making them very difficult to use in a design flow. The RFD solver and its environment stand out from its competitors in several aspects. Because of its tight integration in Cadence s Virtuoso environment it allows the designers to stay in their design environment and avoid time consuming, error-prone tasks like GDSII streaming, manual simplification of geometries (e.g., vias) and manual back-annotation of solver results (stitching of s-parameters for running circuit simulation).

8 As shown in Figure 8, RFD offers two use-models. One is the classic, layout driven flow, in which the user runs the solver from the layout by setting up the process information, selecting geometries such as nets, instances, cells, Pcells, or shapes, assigning solver ports, and defining simulation parameters. Figure 8 Flow and use-model for Virtuoso RF Designer solver Even in the layout driven flow, RFD offers certain advantages compared with the competitors. For example, all solvers mandate that users clean their layout and retain only the shapes that will be simulated in the solver. This leads to multiple versions of the same layout, thereby making design management difficult. Using RF Designer, the designer can easily pick and choose components and nets from the layout without performing the cleanup step. Additionally, all solvers need users to manually defeature vias, i.e., replace via arrays by larger equivalent vias. This is a very manual and error-prone process. Because RFD can automatically defeature vias, the user runs structures like multi-layer inductors without having to manually defeature them.

9 Finally, all solvers require users to stream out their layout and import it into the solver s own environment. The RFD solver works natively on the Cadence database (CDBA). The user does not need to stream in and out. This saves a lot of unnecessary grief. RFD also offers an automated, schematic-layout driven use-model where the user can take advantage of a Virtuoso XL layout. The basic steps mentioned above, and as shown in the Figure 8, are the same for this flow as well. The advantage is that after the solver simulation is complete, a simulatable schematic that contains s-parameter results is generated automatically. This saves a lot of manual steps, especially if the user is running a high port count solver simulation. Note that the Virtuoso XL layout need not be LVS clean. The user can run the solver on an incrementally built, incomplete layout, thereby offering an EM solver truly in the design loop. EM Analysis and Synthesis Flow Using Virtuoso Passive Component Designer and Virtuoso RF Designer Virtuoso RF Designer can be used in conjunction with another Virtuoso product called Virtuoso Passive Component Designer (PCD) for EM synthesis and synthesized component analysis in RFICs. Figure 9 Using Virtuoso RFD and PCD for EM analysis and synthesis needs As shown in the Figure 9, PCD can be used to synthesize a family of inductor Pcells with both accurate time- and frequency-domain models. The user can then use these inductors in the layout and start incrementally analyzing the high frequency effects that can change the circuit performance. By running the fast RFD EM solver and manually tweaking or optimizing the layout, the designer can quickly close the schematic-layout loop for RF blocks. A typical first pass of the layout may need multiple EM analysis runs. Running 40 or 50 EM simulations is not uncommon. Because of all the automation

10 provided in RFD, an automatically generated solver schematic view, distributed computing and adaptive sweep, etc. running such a high number of EM simulations is not only possible, but can be achieved within a couple of days. This unique flow makes RFD the designer s tool of choice. Benchmark Results RFD has been benchmarked for the past 5 years against measurement data from a number of foundries that includes TSMC, IBM, Jazz, and other captive foundries. Almost all of that work has been done under Non Disclosure Agreements (NDA) and hence details about those foundry processes or the actual structures cannot be disclosed in this paper. However, we include correlation results from a few benchmarks below. Figure 10 shows the comparison of Q, L, and R values derived from RFD results and measurement data. This was a single layer on-chip inductor coil with the measurement test fixture in a 180nm process. The data shows good correlation between measured and modeled. Figure 10 Comparing Q, L, and R plots derived from RFD simulation and measurement for an on-chip inductor (180nm) Figure 11 shows similar Q, L, and R comparison with measurement data for another onchip inductor in a 65nm CMOS process.

11 Figure 11 Comparing Q, L, and R plots derived from RFD simulation and measurement for an on-chip inductor (65nm) Figure 12 shows the correlation between RFD results and measurement data for a microstrip antenna. This structure along with the measurement and calculated data was published in [2]. Readers should keep in mind that RFD does not model antenna radiation or patterns associated with antennas.

12 Figure 12 Comparison between RFD results and measurement data for a microstrip patch antenna (a) patch antenna structure (b) measurement result from [2] (c) RFD solver result Summary: Advantages of Using RFD in an RFIC Design Flow We would like to summarize the reasons that will make RFD an important tool for RF designers: RF Designer is a full-wave solver that simulates high-frequency effects such as Cross-talk, skin-effect, substrate effects, thick metal, multiple dielectrics, etc. RF Designer is tightly integrated in the Virtuoso environment minimizing pre- & post-processing for solver No need for GDSII stream in/out No need for manual via de-featuring Automatic back-annotation to extracted schematic view. A broad array of structures can be modeled including Passives (inductors, capacitors, MIM capacitors), interconnects, ground planes and combinations of these structures. RF Designer is accurate at low through high frequencies (1 Hz to 60+ GHz) RF Designer can tackle complex, physically large problems Model EM effects for entire RF data path. RF Designer is fast It utilizes a Method of Moments (MoM) formulation with multi-layer PFFT acceleration It offers parallelization in frequency-sweep and adaptive sweep utilizing compute server farms. RF Designer is a design tool integrated into the RF design flow Eliminates the need for standalone EM solvers.

13 References [1] F. Ling, V. Okhmatovski, W. Harris, S. McCracken, and A. Dengi, Large-scale broadband parasitic extraction for fast layout verification of 3D RF and mixed-signal onchip structures, IEEE International Microwave Symposium, Fort Worth, TX, June 2004 [2] D. M. Sheen, S. M. Ali, M. D. Abouzahra, and J. A. Kong, Application of the three dimensional Finite-Difference Time-Domain method to the analysis of planar microstrip circuits, IEEE Transactions on Microwave Theory and Techniques, Vol. 38, No. 7, July 1990