0.6μm BiCMOS 0.6 Micron BiCMOS Technology for Analog Product Applications
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1 0.6μm BiCMOS 0.6 Micron BiCMOS Technology for Analog Product Applications Description 06BC is CSMC s standard BiCMOS process platform. In addition to the double poly, double metal 0.6 micron drawn gate length process for digital applications, process modules are available for 5V or 12V Poly emitter VNPN, 5V or 12V LPNP, PIP and Sinker capacitor and High value resistors. All main modules are comparable in Design Rules. Comprehensive design rules, accurate SPICE models, DRC and LVS common file support the process on platforms supplied by the major EDA tool vendors Key Features - 5V logic layout & performance compatible with the industry standard - Modular concept (MOS/ CAP / BJT /RES/ Special require.) - 5V/ 12V Poly emitter VNPN - 5V/ 12V LPNP - capacitor (PIP, Poly1/ N sinker, Poly2 / N sinker, stacking) - High value poly resistor (Poly1, Base) - Provide high temperature models - (MOS, BJT, RES, CAP) Applications - FM Tune TV Signal control Quality Assurance CSMC continue to improve the process quality and reliability and to provide competent support to the customers. CSMC follow APQP procedures developed process technology. This comprehensive, proprietary quality improvement system has been certified to fulfill the requirements of the ISO 9001, QS 9000, ISO TS and other standards. Deliverables PCM tested wafers Optional production services: wafer probe sort Optional production services(turn key): packages and final sort Optional Engineering services: Multi Project Wafer (MPW) and Multi Layer Service (MLM)
2 Process Flow Baseline Module BN photo and implant BP photo and implant N-well photo and implant P-well photo and implant Active Area N-Field N sinker photo and implant Poly 1 CMOS Base photo and implant emitter Poly2 NLDD N+ Implant P+ Implant Contact Plug photo and implant Metal 1 Via 1 Metal 2 PAD Additional Module Poly high resistor ONO capacitor Schematic Cross Sections
3 Document list Mask Tooling Information Electrical Design Rule PCM Specification SPICE model Basic Design Rules Basic design rules Parameter Width(µm) Space(µm) Pitch(µm) N bury layer P bury layer N well P well Active Nsinker IM Poly Cmos Base Emitter Poly2 (Gate poly) N P Contact M Via Top Metal (Thin)
4 Key Device Parameters of 5V BiCMOS MOS Transistor Device Device name VT (V) Ids (ua/um) Bvd/sgt (V) Ioff (pa/um) Max. Vds Max.Vgs normal NMOS NMOS >8 < normal PMOS PMOS <-8 < BJT Transistor Device Device name Hfe BVceo (V) BVcbo (V) BVebo (V) VA 5V VNPN npn >12 5V LPNP pnp >6 5V VPNP pnp >45 Resistor and conductors Device Device name Rs(ohm/sq) Thickness(um)/junction depth(um) Buried N+ RES Buried N NW_F 77.6/19.4 RES N well N+ SHEET RES N+ Res P+ SHEET RES P+ Res NSINKER RES N SINKER Res 21 - LOW POLY1 RES Poly Res HIGH POLY1 RES Poly Res POLY2 RES Poly Res P-BASE RES Base Res Capacitors Device Device name Area Cap.(fF/um2) BV (V) CAPS ONO PIP CAP 1.8 >8 CAPS Poly2/Nsinker Nsinker CAP 2.3 >8 CAPS Poly1/Nsinker Nsinker CAP 1.2 >18 GOX/NW CAP MOS CAP 2.5 >8 GOX/PW CAP MOS CAP 2.5 >8 Key Device Parameters of 12V BiCMOS MOS Transistor Device Device name VT (V) Ids (ua/um) Bvd/sgt (V) Ioff (pa/um) Max. Vds Max.Vgs normal NMOS NMOS >8 < normal PMOS PMOS <-8 < BJT Transistor Device Device name Hfe BVceo (V) BVcbo (V) BVebo (V) VA 12V VNPN npn >30 12V LPNP pnp >15 Resistor and conductors Device Device name Rs(ohm/sq) Thickness(um)/junction depth(um) Buried N+ RES Buried N NW_F 77.6/19.4 RES N well N+ SHEET RES N+ Res P+ SHEET RES P+ Res NSINKER RES N SINKER Res 21 - LOW POLY1 RES Poly Res HIGH POLY1 RES Poly Res POLY2 RES Poly Res P-BASE RES Base Res Capacitors Device Device name Area Cap.(fF/um2) BV (V) CAPS ONO PIP CAP 1.8 >8 CAPS Poly2/Nsinker Nsinker CAP 2.3 >8 CAPS Poly1/Nsinker Nsinker CAP 1.2 >18 GOX/NW CAP MOS CAP 2.5 >8 GOX/PW CAP MOS CAP 2.5 >8
5 Examples for measured and modeled parameter characteristics Figure1. NMOS W/L=20/0.6 Figure2. PMOS W/L=20/0.6 Figure3. 5V LPNP Figure4. 5V VNPN Figure5. 12V LPNP Figure6. 12V VNPN
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