Circuits Multi-Projets
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1 Circuits Multi-Projets Technology Processes & Runs in 2017 MPW Service Center for ICs, Photonics, & MEMS Prototyping & Low Volume Production Grenoble - France
2 Available Processes Process Name Process Feature C35B4C3 0.35µ CMOS 3.3V / 5.0V C35B4C2 0.35µ CMOS 3.3V C35B4O1 C35B4OA S35D4M5 C35B4M3 H35B4D3 ac18a6 ah18a6 BYE / BYQ 0.35µ CMOS-Opto ARC 0.35µ CMOS-Opto BARC 0.35µ SiGe BiCMOS 0.35µ CMOS-RF 0.35µ HV-CMOS 0.18µ CMOS 0.18µ HV-CMOS 0.8µ BiCMOS (available on request) 2
3 CMOS 0.35µ C35 (C35B4C3) Process (0.35µ CMOS) 2 Layers Polysilicon, 4 Layers Metal, 3.3V / 5.0V, High Resistive Poly. 3.3V / 5.0V I/O pads. Peripheral cells with high driving capability (from 1mA to 24mA) Application : Analog, Digital, Mixed A/D, RF. Density : 18 kgates/mm 2 Gate Delay: 100ps (NAND2 typical) Libraries : Digital and Analog Standard Cells + Pads + P-Cells. CORELIB qualified for 1.8V / 2.2V / 2.7V / 3.3V CORELIB_V5 qualified for 2.0V / 3.0V / 4.0V / 5.0V Thick Metal and MIM available in C35B4M3. 4 MPW runs scheduled in
4 CMOS-Opto 0.35µ (ARC) CMOS-Opto 0.35µ (C35B4O1) Planarization and anti-reflective coating allows better optical features. P-Epi wafers for lowering current leakage in the diode (lower dark current). Anti reflective coating Fox P+ P- metal4 via3 metal3 via2 metal2 via1 metal1 contact PHOTO_DIODE n+ n- P+ P- P- Epi P- substrate Design-kit compatible with the 4 layers metal process option C35B4. Every C35 MPW run planned by CMP includes the CMOS-Opto option. 4 MPW runs scheduled in
5 CMOS-Opto BARC C35B4OA CMOS-Opto 0.35µ with Bottom Anti-Reflective Coating (BARC) (C35B4OA) Bottom Anti-Reflective Coating allows better sensitivity than ARC. P-Epi wafers for lowering current leakage in the diode (lower dark current). Cross-section of a photo-diode (BARC process option) 4 MPW runs scheduled in
6 Process (0.35µ SiGe) SiGe HBT-BiCMOS 0.35 µ S35D4M5 4 Layers Polysilicon / 4 Layers Metal. Power supply voltage range (2.5V 3.6V / 5.5V) Vertical SiGe-HBT NPN : Ft = 70 GHz High Resistive Polysilicon. Poly1/Poly2 capacitors MIM capacitors Thick Top Metal 3 MPW runs scheduled in
7 Process (0.35µ HV-CMOS) HV CMOS 0.35 µ H35 (H35B4D3) 2 Layers Polysilicon, 4 Layers Metal, High Resistive Poly, Thick 4 th Metal. 20V / 50 V / 120 V Maximum operating voltage. 3.3V / 5.0V / 20V Maximum gate voltage. R on = 0.11 Ohm mm 2 for HV-NMOS 4 MPW runs scheduled in 2018 R on = 0.29 Ohm mm 2 for HV-PMOS NMOS50 (50V) PMOS50 (50V) NMOS120 (120V) PMOS120 (120V) NMOSI50 (50V) VERTN1 Isolated 3.3V / 5V Standard 3.3V / 5V 7
8 - CMOS technology with 3 mask level adders for HV - Three gate oxides available: 1.8, 5V and 20V - 6 metal levels (last metal: 4 µm Al power metal) - Full set of 20 V and 50 V LDMOS devices - Low Rdson < 14 m *mm V BVDSS < 130 m *mm V BVDSS V and 5 V floating logic (N/PFET) - High-voltage vertical NPN & PNP bipolar transistors - Isolated JFET - High-voltage VN capacitors (20-50V) - High voltage well based resistors - 1 kv, 2 kv and 4 kv HBM ESD protection structures - OTP (Efuse) - Tool for safe operating area check (SOAC) 0.18µ CMOS & High-Voltage CMOS 2 MPW runs scheduled in
9 Runs in 2017 Number of prototypes in 2017 : 70 (87 in 2016) Number of Low volume prod. in 2017 : 16 (25 in 2016) 38 scheduled MPW runs (29 in 2016) 8 extra runs (Production) (3 in 2016) CMOS 47 (35 in 2016) 67% (40% in 2016) 2017 CMOS SiGe HV-CMOS MEMS MEMS Bulkmicromachining 2 (0 in 2016) 3% (0% in 2016) SiGe 9 (27 in 2016) 13% (31% in 2016) HV-CMOS 12 (25 in 2016) 17% (29% in 2016) 2016 CMOS SiGe HV-CMOS 9
10 From layout to chips Runs Histogram Prototypes Productions
11 Low Volume Productions (2017) Run / Techno Company Qty Package A35C14_4 (0.35um CMOS) University of Oulu 260 QFN24 SA35C17_1 (0.35um CMOS) SONICSMITH 6 wafers ( parts) QFN32 SA35C13_1 (0.35um CMOS) CEA Saclay QFP128 A18V17_1 (0.18um CMOS) Linköping University A35C17_3 (0.35um CMOS) ID-MOS A18V17_4 (0.18um CMOS) ENSI Caen - LPC 50 - A35S17_3 (0.35um SiGe) IM2NP A35V17_4 (0.35um HV) Siliconsortium 75 - SA35C17_3 (0.35um CMOS) Noptel / University Oulu 6 wafers (1 000 parts) QFN24 SA35S17_1 (0.35um SiGe) Thales SA 12 wafers ( parts) QFN40 SA35S16_1 (0.35um SiGe) OMEGA / IN2P3 12 wafers (8 350 parts) - SA35S16_1 (0.35um SiGe) LPSC / IN2P3 800 PQFP64 SA35V12_1 (0.35um HV) Thales SA 6 wafers (8 800 parts) LQFP64 SA35V12_2 (0.35um HV) Aptasic 6 wafers - SA35V12_2 (0.35um HV) Aptasic 6 wafers - A35C16_2 (0.35um CMOS) Siliconsortium
12 Success Story : SONICSMITH AMS 0.35um CMOS QFN32 package parts 12
13 Conclusion Comprehensive Process portfolio : CMOS, CMOS-Opto, CMOS-RF, SiGe, HV-CMOS, Prototype s projects number decreasing in A strong increase of parts quantities in low volume productions. Continuing the strong partnership and collaboration CMP / ams AG. 13
Circuits Multi-Projets
Circuits Multi-Projets 0.35µm, 0.18µm MPW services http://mycmp.fr Grenoble - France Available Processes Process Name Process Feature C35B4C3 0.35µm CMOS 3.3V / 5.0V C35B4C2 0.35µm CMOS 3.3V C35B4O1 C35B4OA
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