Register Transfer Level (RTL) Design

Transcription

1 CSE4: Components and Design Techniques for Digital Systems Register Transfer Level (RTL) Design Instructor: Mohsen Imani Slides from Tajana Simunic Rosing

2 CAPE CAPEs are out!!! Please submit your evaluations!!!! Your feedback is very important, please take the time to fill out the survey.

3 3D Xpoint Memory

4 About the final ~5 minutes Final Exam Bring one 8 ½ x paper with handwritten notes, but nothing else Problems including (but not limited to): - design - components (shifters, adders, etc.) - FSM - Moore, Mealy, design of FSM using state table, excitation table - Timing constraints - RTL design and HLSM

5 : Arithmetic Logic Unit

6 Designing an Arithmetic Logic Unit op A 3 N Zero N Result Overflow B N CarryOut Control Lines (op) Function And Or Add Subtract Set-on-less-than 6

7 A One Bit This -bit performs AND, OR, and ADD

8 A 32-bit -bit 32-bit 8

9 Subtract We d like to implement a means of doing A-B (subtract) but with only minor changes to our hardware. How?. Provide an option to use bitwise NOT A 2. Provide an option to use bitwise NOT B 3. Provide an option to use bitwise A XOR B 4. Provide an option to use instead of the first CarryIn 5. Provide an option to use instead of the first CarryIn Selection Choices A alone B Both and 2 C Both 3 and 4 D Both 2 and 5 E None of the above 9

10 Full 32-bit what signals accomplish ADD? Binvert CIn Oper A 2 B 2 C 2 D 2 E NONE OF THE ABOVE sign bit (adder output from bit 3)

11 Full 32-bit what signals accomplish OR? Binvert CIn Oper A B C D E NONE OF THE ABOVE sign bit (adder output from bit 3)

12 Full 32-bit Little more intense can you get this? what signals accomplish SUB? Binvert CIn Oper A 2 B 2 C 2 D 2 E NONE OF THE ABOVE sign bit (adder output from bit 3) 2

13 Arithmetic Logic Unit Example 2 A A B N N B N N N N F2 Y N Cout + [N-] S Zero Extend N N N N F F2: Function A&B A B A+B Not used A & ~B A ~B A-B Not used F: N Y

14 Problem x y z OP A+B A-B A+A A<B A*4 A/4 Reverse (A) 2-complement (B) Design an with two 8bit inputs A and B that has three control bits xyz and implements the operations described in the table

15 Problem x y z OP A+B A-B A+A A<B A*4 A/4 Reverse (A) 2-complement (B)

16 Problem x y z OP A+B A-B A+A A<B A*4 A/4 Reverse (A) 2-complement (B)

17 Problem x y z OP A+B A-B A+A A<B A*4 A/4 Reverse (A) 2-complement (B)

18 Design of a new FF (waveforms) Q(t) x Q(t+)

19 Design of a new FF Q(t+) = Q(t) x + Q(t)x Q(t) x Q(t+)

20 Problem: FSM from circuit to state diagram

21 Problem: FSM from circuit to state diagram D = y= Q a D y Qo \ a

22 Problem: FSM from circuit to state diagram D = Q *a y = Qo + a Q a D y Qo \ a,,,,

23 Problem: FSM from word description to state diagram A microwave oven has 3 modes of operation when it is on: High temperature (H), Low temperature (L) and Defrost (D). A -bit input signal X is controlled by a button. Whenever the button is pressed, X changes its value. When the oven is off, X = will make it switch on to D mode. After that, every time X changes its value, the oven goes to L, then H the off again. a. Is it a Moore or a Mealy machine? b. How many states does it have? How many bits are required to represent them? c. Draw the state diagram

24 Solution

25 Solution

26 Solution

27 Problem: FSM from state diagram to circuit QQ D A D Y QQ\A,,,,,,,,

28 Solution QQ D A D Y QQ\A,,,,,,,,

29 Solution D = Q Q \ QA D = QQ + QA + Q A Q \ QA Y = Q Q + QQA Q \ QA QQ D A D Y

30 Solution

31 Circuit timing recap Gate: - minimum (contamination) delay : t_cd - maximum (propagation) delay : t_pd D-FF: - Input: - Setup : t_setup - Hold : t_hold - Output: - Minimum (contamination) delay : t_ccq - Maximum (propagation) delay : t_pcq

32 Time constraints Setup time constraints: T_c t_pcq + t_pd + t_setup Hold time constraints: t_hold < t_ccq + t_cd

33 Time constraints with skew Setup time constraints: T_c t_pcq + t_pd + t_setup + t_skew t_pd T_c (t_pcq + t_setup + t_skew) Hold time constraints: t_ccq + t_cd > t_hold + t_skew t_cd > t_hold + t_skew t_ccq

34 Timing constraints example D-FF: - t_ccq = 4 - t_pcq = 6 - t_setup = 7 - t_hold = 8 Gates: AND: - t_pd = 4 - t_cd = 3 OR: - t_pd = 4 - t_cd = 3 NOT: - t_pd = 3 - t_cd = 2

35 Timing constraints example D-FF: - t_ccq = 4 - t_pcq = 6 - t_setup = 7 - t_hold = 8 Gates: AND: - t_pd = 4 - t_cd = 3 OR: - t_pd = 4 - t_cd = 3 NOT: - t_pd = 3 - t_cd = 2

36 Timing constraints example Setup time constraints: T_c t_pcq + t_pd + t_setup T_c (6) + (3*4 + 3) + 7 T_c 28ps Hold time constraints: t_hold < t_ccq + t_cd 8 < > NO!! ----> add buffer!

37 Timing constraints example Setup time constraints with skew: What is the maximum t_skew that can be tolerated before having a setup timing error with a frequency of 3 GHz? T_c = / f = / 3e9 = 333ps T_c t_pcq + t_pd + t_setup + t_skew (6) - (3*4 + 3) - 7 t_skew 53ps t_skew

38 CPU Control and Datapath Execute Instruction Set Processor Control Datapath PC R E G I S T E R S DEVICES IN Main Memory OUT Control takes program as input; it interprets each instruction and tells the Datapath to operate on data via, memory and registers 38

39 PC+4 [3-28] JMP ADDRESS [3-] 4 ADDER ADDER I[25-] PC << 2 JMP ADDRESS [25-] << 2 BRANCH REG_DST INSTRUCTION[3-26] REG_ ADDRESS INSTRUCTION[25-2] REGISTER INSTRUCTION[2-6] REGISTER 2 INSTRUCTION MEMORY INSTRUCTION [3-] INST[5-] _SRC MEM_,MEM OP ZERO REGISTERS REGISTER JUMP MEM_TO_REG CON TROL 2 ADDRESS MEMORY INSTRUCTION[5-] Sign Extend INSTRUCTION[5-] CONTROL 39

40 CPU Components Single Cycle Execution Assumptions: Every machine language instruction happens in Clock Cycle MIPS architecture Microprocessor without interlocked pipeline stages reg-reg architecture: all operands must be in registers (total 24) 3 Instruction Types; each instruction 32 bits long. R-type: all data in registers (most arithmetic and logical) e.g. add $s, $s2, $s3 2. I-type: branches, memory transfers, constants e.g. beq $s, $s2, Label; lw $s, 32($s2) 3. J-type: jumps and calls e.g. j Label; add $s, $s, $s

41 R-type Instruction: reg-reg ops (e.g. add, and) Tells specific variant of operation (e.g. add/sub have same opcode) Tells operation to be performed R-type Instruction OPCODE = 3-26 RS 25-2 RT RD shamt FUNCT = 32 or ADD $S, $S2, $S3 ADD RD, RS, RT Source Register (attached to Read Register input) Shift amount (for sll, srl etc.) Source Register 2 (attached to Read Register 2 input) Destination Register (attached to Write Register input) 4

42 4 ADDER ADDER << 2 PC REG_DST INSTRUCTION[3-26] INSTRUCTION[25-2] REGISTER INSTRUCTION[2-6] REGISTER 2 INSTRUCTION MEMORY INSTRUCTION [3-] INST[5-] _SRC MEM_,MEM OP ZERO REGISTERS REGISTER MEM_TO_REG REG_ ADDRESS BRANCH CON TROL 2 ADDRESS MEMORY INSTRUCTION[5-] Step (R-type): Fetch instruction and advance PC Sign Extend INSTRUCTION[5-] CONTROL 42

43 4 ADDER ADDER << 2 PC REG_DST INSTRUCTION[3-26] INSTRUCTION[25-2] REGISTER INSTRUCTION[2-6] REGISTER 2 INSTRUCTION MEMORY INSTRUCTION [3-] INST[5-] REGISTER MEM_,MEM OP ZERO REGISTERS _SRC MEM_TO_REG REG_ ADDRESS BRANCH CON TROL 2 ADDRESS MEMORY Sign Extend INSTRUCTION[5-] INSTRUCTION[5-] Step 2 (R-type): Read two registers and set control signals CONTROL 43

44 4 ADDER ADDER << 2 PC REG_DST INSTRUCTION[3-26] INSTRUCTION[25-2] REGISTER INSTRUCTION[2-6] REGISTER 2 INSTRUCTION MEMORY INSTRUCTION [3-] INST[5-] _SRC MEM_,MEM OP ZERO REGISTERS REGISTER MEM_TO_REG REG_ ADDRESS BRANCH CON TROL 2 ADDRESS MEMORY INSTRUCTION[5-] Step 3 (R-type): Perform the operation Sign Extend INSTRUCTION[5-] CONTROL 44

45 4 ADDER ADDER << 2 PC REG_DST INSTRUCTION[3-26] INSTRUCTION[25-2] REGISTER INSTRUCTION[2-6] REGISTER 2 INSTRUCTION MEMORY INSTRUCTION [3-] INST[5-] _SRC MEM_,MEM OP ZERO REGISTERS REGISTER MEM_TO_REG REG_ ADDRESS BRANCH CON TROL 2 ADDRESS MEMORY INSTRUCTION[5-] Step 4 (R-type): Write result to register Sign Extend INSTRUCTION[5-] CONTROL 45

46 I-Type: Store Instruction Tells operation to be performed Store Instruction OPCODE = 35 or Base Address Register (attached to Read Register input) SW $S, 32($S2) SW RT, #(RS) RS 25-2 RT OFFSET Source register whose value will be stored to memory (attached to Read Register 2 input) Constant offset (added to the base address in RS) Note: same as x86 MOV [ebx+32], eax

47 4 ADDER ADDER << 2 PC REG_DST INSTRUCTION[3-26] INSTRUCTION[25-2] REGISTER INSTRUCTION[2-6] REGISTER 2 INSTRUCTION MEMORY INSTRUCTION [3-] INST[5-] _SRC MEM_,MEM OP ZERO REGISTERS REGISTER MEM_TO_REG REG_ ADDRESS BRANCH CON TROL 2 ADDRESS MEMORY INSTRUCTION[5-] Step (store): Fetch instruction and advance PC Sign Extend INSTRUCTION[5-] CONTROL 47

48 4 ADDER ADDER << 2 PC REG_DST INSTRUCTION[3-26] INSTRUCTION[25-2] REGISTER INSTRUCTION[2-6] REGISTER 2 INSTRUCTION MEMORY INSTRUCTION [3-] INST[5-] _SRC MEM_,MEM OP ZERO REGISTERS REGISTER MEM_TO_REG REG_ ADDRESS BRANCH CON TROL 2 ADDRESS MEMORY INSTRUCTION[5-] Step 2 (store): Read register values and set control signals Sign Extend INSTRUCTION[5-] CONTROL 48

49 4 ADDER ADDER << 2 PC REG_DST INSTRUCTION[3-26] INSTRUCTION[25-2] REGISTER INSTRUCTION[2-6] REGISTER 2 INSTRUCTION MEMORY INSTRUCTION [3-] INST[5-] _SRC MEM_,MEM OP ZERO REGISTERS REGISTER MEM_TO_REG REG_ ADDRESS BRANCH CON TROL 2 ADDRESS MEMORY INSTRUCTION[5-] Step 3 (store): Compute the address Sign Extend INSTRUCTION[5-] CONTROL 49

50 4 ADDER ADDER << 2 REG_DST INSTRUCTION[3-26] INSTRUCTION[25-2] REGISTER INSTRUCTION[2-6] REGISTER 2 PC INSTRUCTION MEMORY INSTRUCTION [3-] INST[5-] _SRC MEM_,MEM OP ZERO REGISTERS REGISTER MEM_TO_REG REG_ ADDRESS BRANCH CON TROL 2 ADDRESS MEMORY INSTRUCTION[5-] Step 4 (store): Write the value to memory Sign Extend INSTRUCTION[5-] CONTROL 5

51 I-Type: Conditional Branch BEQ/BNE Instruction OPCODE = 4 or 5 RS RT BRANCH TARGET S OFFSET Source Register Source register 2 (attached to Read (attached to Read Register input) Register 2 input) BEQ Source, Source2, Offset BEQ $S, $S2, = AL = ML (in binary) 5- Word Offset, which we multiply by 4 (via <<2) to get Bit Offset, then add to PC+4 to get the address of the instruction to which we branch if RS = RT) PC-relative address 5

52 4 ADDER ADDER << 2 PC REG_DST INSTRUCTION[3-26] INSTRUCTION[25-2] REGISTER INSTRUCTION[2-6] REGISTER 2 INSTRUCTION MEMORY INSTRUCTION [3-] INST[5-] REGISTER MEM_,MEM OP ZERO REGISTERS _SRC MEM_TO_REG REG_ ADDRESS BRANCH CON TROL 2 ADDRESS MEMORY Sign Extend INSTRUCTION[5-] INSTRUCTION[5-] Step (beq): Fetch instruction and advance PC CONTROL 52

53 4 ADDER ADDER << 2 PC REG_DST INSTRUCTION[3-26] INSTRUCTION[25-2] REGISTER INSTRUCTION[2-6] REGISTER 2 INSTRUCTION MEMORY INSTRUCTION [3-] INST[5-] _SRC MEM_,MEM OP ZERO REGISTERS REGISTER MEM_TO_REG REG_ ADDRESS BRANCH CON TROL 2 ADDRESS MEMORY INSTRUCTION[5-] Step 2 (beq): Read register values and set control signals Sign Extend INSTRUCTION[5-] CONTROL 53

54 4 ADDER ADDER << 2 PC REG_DST INSTRUCTION[3-26] INSTRUCTION[25-2] REGISTER INSTRUCTION[2-6] REGISTER 2 INSTRUCTION MEMORY INSTRUCTION [3-] INST[5-] _SRC MEM_,MEM OP ZERO REGISTERS REGISTER MEM_TO_REG REG_ ADDRESS BRANCH CON TROL 2 ADDRESS MEMORY INSTRUCTION[5-] Sign Extend INSTRUCTION[5-] Step 3 (beq): Compare registers, calculate branch target, and choose new PC CONTROL 54

55 J-Type: Unconditional Branch JMP/JAL Instruction OPCODE = 2 or BRANCH TARGET ADDRESS 25- J Offset Actual Address (in words) which we multiply by 4 (<<2) to get 28-Bit Address, J = AL then concatenate to upper 4 bits of PC = ML (in binary) to get the 32-bit addresss of instruction to which we branch unconditionally 55

56 PC+4 [3-28] JMP ADDRESS [3-] 4 ADDER ADDER I[25-] PC << 2 JMP ADDRESS [25-] << 2 BRANCH REG_DST INSTRUCTION[3-26] REG_ ADDRESS INSTRUCTION[25-2] REGISTER INSTRUCTION[2-6] REGISTER 2 INSTRUCTION MEMORY INSTRUCTION [3-] INST[5-] _SRC MEM_,MEM OP ZERO REGISTERS REGISTER JUMP MEM_TO_REG CON TROL 2 ADDRESS MEMORY INSTRUCTION[5-] Single-Cycle Datapath with Support for the Jump Instruction Sign Extend INSTRUCTION[5-] CONTROL 56

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