Embedded Systems Design: A Unified Hardware/Software Introduction. Outline. Chapter 2: Custom single-purpose processors.

Transcription

1 Hrdwre/Softwre Itroductio Chpter Custom sigle-purpose processors Itroductio Combitiol logic Sequetil logic Outlie Custom sigle-purpose processor desig RT-level custom sigle-purpose processor desig Hrdwre/Softwre Itroductio, (c) 2 Vhid/Givrgis 2 Itroductio CMOS trsistor o silico Processor Digitl circuit tht performs computtio tsks Cotroller d Geerl-purpose: vriet of computtio tsks Sigle-purpose: oe prticulr computtio tsk Custom sigle-purpose: o-stdrd tsk A custom sigle-purpose processor m be st, smll, low power But, high NRE, loger time-to-mrket, less fleible les CCD Digitl cmer chip A2D JPEG codec DMA ler CCD preprocessor Microler Piel coprocessor Displ ctrl D2A Multiplier/Accum Memor ler ISA bus iterfce UART LCD ctrl Trsistor The bsic electricl compoet i digitl sstems Acts s o/off switch Voltge t gte s whether curret flows from source to dri Do t cofuse this gte with logic gte gte IC pckge IC source gte oide chel dri Silico substrte source Coducts if gte= dri Hrdwre/Softwre Itroductio, (c) 2 Vhid/Givrgis 3 Hrdwre/Softwre Itroductio, (c) 2 Vhid/Givrgis 4

2 CMOS trsistor implemettios Bsic logic gtes Complemetr Metl Oide Semicoductor We refer to logic levels Tpicll is V, is 5V Two bsic CMOS tpes MOS coducts if gte= pmos coducts if gte= Hece complemetr Bsic gtes Iverter, NAND, NOR gte iverter source Coducts if gte= dri MOS = ' gte NAND gte = ()' source Coducts if gte= dri pmos NOR gte = (+)' = Driver = Iverter = AND = ( ) NAND = + OR = (+) NOR =! XOR = XNOR Hrdwre/Softwre Itroductio, (c) 2 Vhid/Givrgis 5 Hrdwre/Softwre Itroductio, (c) 2 Vhid/Givrgis 6 Combitiol logic desig RT-Level Combitiol compoets A) Problem descriptio is if is to, or b d c re. z is if b or c is to, but ot both, or if ll re. D) Miimized output equtios bc z bc Combitiol circuit - digitl circuit whose output is purel fuctio of its preset iputs. = + bc z = b + b c + bc B) Truth tble Iputs Outputs b c z b c C) Output equtios = 'bc + b'c' + b'c + bc' + bc z = 'b'c + 'bc' + b'c + bc' + bc E) Logic Gtes z I(m-) I I S -bit, m Multipleor S(log m) O O = I if S=.. I if S=.. I(m-) if S=.. I(log -) I log Decoder O(-) O O O = if I=.. O = if I=.. O(-) = if I=.. With eble iput e! ll O s re if e= A B -bit Adder sum = A+B (first bits) crr = (+) th bit of A+B With crr-i iput Ci! crr sum sum = A + B + Ci A B -bit Comprtor less equl greter less = if A<B equl = if A=B greter= if A>B A B bit, m fuctio S ALU S(log m) O O = A op B op determied b S. M hve sttus outputs crr, zero, etc. Hrdwre/Softwre Itroductio, (c) 2 Vhid/Givrgis 7 Hrdwre/Softwre Itroductio, (c) 2 Vhid/Givrgis 8

3 Sequetil compoets Sequetil logic desig Sequetil circuit - digitl circuit whose outputs re fuctio of the preset iputs s well s the previous iputs A) Problem Descriptio C) Implemettio Model D) Stte Tble (Moore-tpe) lod cler -bit Register Q = if cler=, I if lod= d clock=, Q(previous) otherwise. I Q shift I Q = lsb - Cotet shifted - I stored i msb -bit Shift register Q -bit Couter Q = if cler=, Q(prev)+ if cout= d clock=. Q You wt to costruct clock divider. Slow dow our preeistig clock so tht ou output for ever four clock ccles = = B) Stte Digrm - SM = = = 3 = = = 2 = = = = Combitiol logic (Geerte output vlues d et stte) Q Q Stte register (Stores curret stte) I I I I Iputs Outputs Q Q I I Give this implemettio model Sequetil logic desig quickl reduces to combitiol logic desig Hrdwre/Softwre Itroductio, (c) 2 Vhid/Givrgis 9 Hrdwre/Softwre Itroductio, (c) 2 Vhid/Givrgis Sequetil logic desig (cot.) Custom sigle-purpose processor bsic model I QQ I QQ QQ E) Miimized Output Equtios ) Combitiol Logic I = Q Q + Q + QQ I = Q + Q = QQ Q Q I I eterl iputs ler eterl outputs iputs outputs ler d eterl dt iputs eterl dt outputs ler et-stte d logic stte register registers fuctiol uits view iside the ler d Hrdwre/Softwre Itroductio, (c) 2 Vhid/Givrgis Hrdwre/Softwre Itroductio, (c) 2 Vhid/Givrgis 2

4 Emple: gretest commo divisor Stte digrm templtes irst crete lgorithm Covert lgorithm to comple stte mchie Kow s SMD: fiitestte mchie with C use templtes to perform such coversio () blck-bo view go_i _i GCD d_o _i (b) desired fuctiolit : it, ; : while () { while (); = _i; = _i; while (!= ) { if ( < ) 7: = - ; else 8: = - ; d_o = ; : 2-J: 7: = - 8: = - -J: 6-J: 5-J: < = _i = _i d_o =!=!!()!(!=)!(<) (c) stte digrm Assigmet sttemet = b et sttemet = b et sttemet C: J: Loop sttemet while (cod) { loop-bodsttemets et sttemet cod loop-bodsttemets et sttemet!cod c stmts Brch sttemet if (c) c stmts else if c2 c2 stmts else other stmts et sttemet C: c J: c2 stmts!c*c2 et sttemet!c*!c2 others Hrdwre/Softwre Itroductio, (c) 2 Vhid/Givrgis 3 Hrdwre/Softwre Itroductio, (c) 2 Vhid/Givrgis 4 Cretig the Cretig the ler s SM Crete register for declred vrible Crete fuctiol uit for ech rithmetic opertio Coect the ports, registers d fuctiol uits Bsed o reds d writes Use multipleors for multiple sources Crete uique idetifier for ech compoet iput d output : 2-J: 7: = - 8: = - -J: 6-J: 5-J: < = _i = _i d_o =!=!!()!(!=)!(<) _i _i _sel -bit 2 -bit 2 _sel _ld : : _ld!= <!= < 8: - _eq lt_ d_ld Dtpth 7: - d d_o : 2-J: 7: = - 8: = - -J: 6-J: 5-J: < = _i = _i d_o =!=!!()!(!=)!(<) Cotroller : 2-J: _lt_!_lt_ 7: _sel = 8: _sel = _ld = _ld = 6-J: 5-J: -J: _sel = _ld = _sel = _ld = d_ld =! _eq_!()!_eq_ go_i Sme structure s SMD Replce comple ctios/coditios with cofigurtios _sel _sel _ld _ld!= < _eq lt_ d_ld _i!= -bit 2 _i : : < -bit 2 8: - Dtpth d 7: - d_o Hrdwre/Softwre Itroductio, (c) 2 Vhid/Givrgis 5 Hrdwre/Softwre Itroductio, (c) 2 Vhid/Givrgis 6

5 Splittig ito ler d Cotroller stte tble for the GCD emple Cotroller implemettio model go_i Combitiol logic Q3 Q2 Q Q I3 Stte register I2 I I _sel _sel _ld _ld _eq lt_ d_ld Cotroller : 2-J: _lt_= _lt_= 7: _sel = 8: _sel = _ld = _ld = 6-J: _sel = _ld = _sel = _ld =!!() _eq_= _eq_= go_i _sel _sel _ld _ld _i -bit 2!= < _eq lt_ d_ld!= _i -bit 2 : : < 8: - (b) Dtpth 7: - d d_o Iputs Outputs Q3 Q2 Q Q _eq _lt_ go_i I3 I2 I I _sel _sel _ld _ld d_ld _ * * * X X * * X X * * X X * * * X X * * * X * * * X * * X X * * X X * * X X * * X X * * * X * * * X * * * X X * * * X X * * * X X 5-J: d_ld = * * * X X * * * X X * * * X X -J: * * * X X Hrdwre/Softwre Itroductio, (c) 2 Vhid/Givrgis 7 Hrdwre/Softwre Itroductio, (c) 2 Vhid/Givrgis 8 Completig the GCD custom sigle-purpose processor desig We fiished the We hve stte tble for the et stte d logic All tht s left is combitiol logic desig This is ot optimized desig, but we see the bsic steps ler et-stte d logic stte register registers fuctiol uits view iside the ler d RT-level custom sigle-purpose processor desig We ofte strt with stte mchie Rther th lgorithm Ccle timig ofte too cetrl to fuctiolit Emple Bus bridge tht coverts 4-bit bus to 8-bit bus Strt with SMD Kow s register-trsfer (RT) level Eercise: complete the desig Problem Specifictio SMD Sede r rd_i clock dt_i(4) rd_i= rd_i= Witirst4 rd_i= WitSecod4 Sed8Strt dt_out=dt_hi & dt_lo rd_out= Bridge A sigle-purpose processor tht coverts two 4-bit iputs, rrivig oe t time over dt_i log with rd_i pulse, ito oe 8-bit output o dt_out log with rd_out pulse. Bridge Recirst4Strt dt_lo=dt_i rd_i= rd_i= RecSecod4Strt dt_hi=dt_i rd_i= Sed8Ed rd_out= rd_out dt_out(8) rd_i= Recirst4Ed rd_i= RecSecod4Ed Rece iver Iputs rd_i: bit; dt_i: bit[4]; Outputs rd_out: bit; dt_out:bit[8] Vribles dt_lo, dt_hi: bit[4]; Hrdwre/Softwre Itroductio, (c) 2 Vhid/Givrgis 9 Hrdwre/Softwre Itroductio, (c) 2 Vhid/Givrgis 2

6 RT-level custom sigle-purpose processor desig (cot ) Optimizig sigle-purpose processors () Cotroller rd_i= rd_i clk dt_i(4) Witirst4 rd_i= WitSecod4 Sed8Strt dt_out_ld= rd_out= Bridge rd_i= Recirst4Strt dt_lo_ld= rd_i= rd_i= RecSecod4Strt dt_hi_ld= Sed8Ed rd_out= rd_i= Recirst4Ed rd_i= RecSecod4Ed rd_out dt_out Optimiztio is the tsk of mkig desig metric vlues the best possible Optimiztio opportuities origil progrm SMD SM to ll registers (b) Dtpth dt_out_ld dt_hi_ld dt_hi dt_out dt_lo dt_lo_ld Hrdwre/Softwre Itroductio, (c) 2 Vhid/Givrgis 2 Hrdwre/Softwre Itroductio, (c) 2 Vhid/Givrgis 22 Optimizig the origil progrm Optimizig the origil progrm (cot ) Alze progrm ttributes d look for res of possible improvemet umber of computtios size of vrible time d spce compleit opertios used multiplictio d divisio ver epesive origil progrm : it, ; : while () { while (); = _i; = _i; while (!= ) { if ( < ) 7: = - ; else 8: = - ; d_o = ; GCD(42, 8) - 9 itertios to complete the loop replce the subtrctio opertio(s) with modulo opertio i order to speed up progrm d vlues evluted s follows : (42, 8), (43, 8), (26,8), (8,8), (, 8), (2,8), (2,6), (2,4), (2,2). optimized progrm : it,, r; : while () { while (); // must be the lrger umber if (_i >= _i) { =_i; =_i; else { 7: =_i; 8: =_i; while (!= ) { : r = % ; : = ; = r; d_o = ; GCD(42,8) - 3 itertios to complete the loop d vlues evluted s follows: (42, 8), (8,2), (2,) Hrdwre/Softwre Itroductio, (c) 2 Vhid/Givrgis 23 Hrdwre/Softwre Itroductio, (c) 2 Vhid/Givrgis 24

7 Optimizig the SMD Optimizig the SMD (cot.) Ares of possible improvemets merge sttes sttes with costts o trsitios c be elimited, trsitio tke is lred kow sttes with idepedet opertios c be merged seprte sttes sttes which require comple opertios (*b*c*d) c be broke ito smller sttes to reduce hrdwre size schedulig 7: it, ;! :!() 2-J: = _i = _i!(!=)!= <!(<) = - 8: = - 6-J: origil SMD elimite stte trsitios hve costt vlues merge stte 2 d stte 2J o loop opertio i betwee them merge stte 3 d stte 4 ssigmet opertios re idepedet of oe other merge stte 5 d stte 6 trsitios from stte 6 c be doe i stte 5 elimite stte 5J d 6J trsitios from ech stte c be doe from stte 7 d stte 8, respectivel optimized SMD < it, ; = _i = _i > go_i 7: = - 8: = - d_o = 5-J: d_o = elimite stte -J trsitio from stte -J c be doe directl from stte 9 -J: Hrdwre/Softwre Itroductio, (c) 2 Vhid/Givrgis 25 Hrdwre/Softwre Itroductio, (c) 2 Vhid/Givrgis 26 Optimizig the Optimizig the SM Shrig of fuctiol uits oe-to-oe mppig, s doe previousl, is ot ecessr if sme opertio occurs i differet sttes, the c shre sigle fuctiol uit Multi-fuctiol uits ALUs support vriet of opertios, it c be shred mog opertios occurrig i differet sttes Stte ecodig tsk of ssigig uique bit ptter to ech stte i SM size of stte register d combitiol logic vr c be treted s orderig problem Stte miimiztio tsk of mergig equivlet sttes ito sigle stte stte equivlet if for ll possible iput combitios the two sttes geerte the sme outputs d trsitios to the et sme stte Hrdwre/Softwre Itroductio, (c) 2 Vhid/Givrgis 27 Hrdwre/Softwre Itroductio, (c) 2 Vhid/Givrgis 28

8 Summr Custom sigle-purpose processors Strightforwrd desig techiques C be built to eecute lgorithms Tpicll strt with SMD CAD tools c be of gret ssistce Hrdwre/Softwre Itroductio, (c) 2 Vhid/Givrgis 29