A System-on-Programmable-Chip Approach for MIMO Lattice Decoder

Transcription

1 University of New Orlens University of New Orlens Theses nd Disserttions Disserttions nd Theses A System-on-Progrmmble-Chip Approch for MIMO Lttice Decoder Vipul Hirll Ptel University of New Orlens Follow this nd dditionl works t: Recommended Cittion Ptel, Vipul Hirll, "A System-on-Progrmmble-Chip Approch for MIMO Lttice Decoder" (2004). University of New Orlens Theses nd Disserttions This Thesis is brought to you for free nd open ccess by the Disserttions nd Theses t ScholrWorks@UNO. It hs been ccepted for inclusion in University of New Orlens Theses nd Disserttions by n uthorized dministrtor of ScholrWorks@UNO. The uthor is solely responsible for ensuring complince with copyright. For more informtion, plese contct scholrworks@uno.edu.

2 A SYSTEM-ON-PROGRAMMABLE-CHIP APPROACH FOR MIMO LATTICE DECODER A Thesis Submitted to the Grdute Fculty of the University of New Orlens in prtil fulfillment of the requirements for the degree of Mster of Science in The Deprtment of Electricl Engineering by Vipul Hirll Ptel B.S., University of Pune, 2000 December 2004

3 Acknowledgements I would like to express my grtitude to my Advisor, Dr Xinming Hung, for his support nd timely dvice through out my reserch. I pprecite nd vlue his consistent feedbck on my progress, which ws lwys constructive nd encourging, nd ultimtely drove me to the right direction. I would like to express my sincere thnks to the other committee members, Dr. Jing M nd Dr. Dimitrios Chlrmpidis for their willingness to be on my thesis committee. Their invluble suggestions nd insightful comments hve mde my work more presentble. I tke this opportunity to thnk my prents nd wife for their unconditionl love nd support through out my life. Finlly I express my grtitude to my friends for their encourgement nd motivtion. ii

4 Tble of Contents LIST OF ILLUSTRATIONS...v List of Figures...v List of Tbles...vi Glossry of Abbrevitions...vii ABSTRACT...viii 1. Introduction Motivtion for Implementing MIMO Lttice Decoder Reserch Objectives Thesis Contribution Orgniztion of Thesis Introduction to Alter System-on-Chip Introduction of Nios Development Bord Generl Description EP1S10 Device Flsh Memory Device Seril Port Connector Design Tools Qurtus II SOPC Builder DSP Builder System Components CPU Architecture Instruction Set Register File Cche Memory Exception Hndling Hrdwre Accelertion Custom Instructions Stndrd CPU Options Multiple Input Multiple Output Systems nd Lttice Decoder Multiple Input Multiple Output System Trnsmitter...17 iii

5 3.1.2 Receiver Closest Point Serch in Lttices Conceptul Description of Closest Point Serch Algorithm Algorithms Decoder A Geometric view of squre root Strssen Mtrix Inversion Method Reduction of Strssen Mtrix Inversion lgorithm of 4x4 lower tringulr mtrix QR Decomposition of Mtrix Householder Mtrix Prototyping of Closest Point Serch Algorithm Why System-on-Chip? Prototyping Closest Point Serch Algorithm Interfce between Nios microprocessor bsed system nd controller Interfce between stte A, B, C nd Controller VHDL Code structure of Controller for Interfce with stte A, B, C Results...47 References...54 VITA...55 iv

6 List of Illustrtions List of figures: Figure 2.1 Figure 2.2 Nios Development Bord...4 Nios Processor Bsed System...11 Figure 2.3 Custom Instruction Logic...14 Figure 3.1 MIMO Trnsmitter...16 Figure 3.2 MIMO Receiver...16 Figure 4.1 Figure 4.2 Figure 4.3 Figure 4.4 Flowchrt of Decoding Algorithm...22 Flowchrt of Stte A of Decoding Algorithm...23 Flowchrt of Stte B of Decoding Algorithm...23 Flowchrt of Stte C of Decoding Algorithm...24 Figure 4.5 Geometric view of the squre of three digit number...26 Figure 4.6 Geometric view of the squre of three digit number...26 Figure 4.7 Flow chrt of Squre Root Algorithm...30 Figure 4.8 Flow chrt of Strssen Mtrix Inversion Algorithm...33 Figure 4.9 Flowchrt of QR Decomposition Algorithm...40 Figure 5.1 Figure 5.2 Figure 5.3 Hrdwre rchitecture of Lttice Decoder...42 Interfce between controller nd Nios Microprocessor bsed system...43 Interfce between Controller nd Stte A, B, C...44 v

7 List of Tbles: Tble 2.1 Strtix EP1S10 Device Fetures...6 Tble 2.2 Comprison of Different Nios Processor Multipliers...15 Tble 6.1 Comprison of Nios Processor with nd without divider to perform Division...48 Tble 6.2 Comprison of sqrt function in C lnguge nd squre root lgorithm...48 Tble 6.3 Number of cycles required to invert 4x4 nd 8x8 lower tringulr mtrix using Strssen method...49 Tble 6.4 Number of cycles to perform QR Decomposition of 4x4 mtrix...50 Tble 6.5 Number of cycles required to perform pre processing prt of decoding...50 Tble 6.6 Sequence of stte in Mtlb...51 Tble 6.7 Sequence of stte in VHDL...51 Tble 6.8 Synthesis results of MIMO Lttice Decoder with Preprocessing Prt...53 vi

8 Glossry of Abbrevitions MIMO Multiple Input Multiple Output FPGA Field Progrmmble Gte Arrys DSP Digitl Signl Processing VHDL Very High speed integrted Description Lnguge CPU Centrl Processing Unit vii

9 Abstrct The pst decde hs shown distinct dvnces in the theory of multiple input multi output techniques for wireless communiction systems. Now, the time hs come to demonstrte this progress in terms of pplictions. This thesis introduces implementtion of Schnorr- Euchner strtegy bsed decoding lgorithm pplied on Alter system-on-chip (Strtix EP1S10F780C6) with Nios embedded processor. The lttice decoder is developed on FPGA using VHDL. The preprocessing prt of lgorithm is trgeted for Nios embedded processor using C lnguge. A controller is lso designed to interfce nd communicte between the Nios embedded processor nd lttice decoder. viii

10 1 Chpter 1 Introduction 1.1 Motivtion for Implementing MIMO Lttice Decoder Wireless systems re rpidly developing to provide high speed voice, text nd multimedi messging services. To support these services, chnnels with lrge cpcities re required. The most brute-force pproch to incresing wireless dt rte is to use more frequency chnnels to increse modultion rte. This "chnnel bonding" pproch will not meet the needs of WLAN consumers, for mny resons. First, while chnnel bonding increses dt rte, it decreses rnge for the sme trnsmit power. Second, chnnel bonding robs chnnels from other systems tht operte nerby. Finlly, chnnel bonding violtes government regultions in Jpn nd some Europen ntions [12] MIMO nswers the question of how to chieve higher dt rtes with longer rnge, bckwrd comptibility, globl regultory complince, ll without using more frequency spectrum. MIMO systems use multiple trnsmit nd receive ntenns. A highrte dt strem is divided into multiple lower-rte strems, ech of which is modulted nd trnsmitted through different ntenn t the sme time using the sme frequency chnnel. Becuse of multipth reflections, ech receive ntenn output is liner combintion of the multiple trnsmitted dt strems. The dt strems re seprted t

11 2 the receiver using lgorithms tht rely on estimtes of ll chnnels between ech trnsmitter nd ech receiver. In ddition to multiplying throughput, rnge is incresed becuse of n ntenn diversity dvntge, since ech receive ntenn hs mesurement of every trnsmitted dt strem. The MIMO lgorithm nd its rchitecture re ctive reserch re in wireless communiction tht motivted the reserch in MIMO systems. 1.2 Reserch Objectives The min objectives of this thesis is to develop system-on-chip pproch for MIMO lttice decoder by using closest point serch lgorithm described in [1] nd lso to utilize prllelism offered by FPGAs to chieve high dt rte. 1.3 Thesis Contribution The implementtion of lttice decoder hs two prts: 1) the preprocessing prt nd 2) the decoding prt. To chieve high decoding rte, the decoding prt cn be implemented by developing customized hrdwre unite (IP core) in FPGA. The preprocessing prt contins opertion like mtrix inversion. Developing specil hrdwre unite to directly implement it in FPGA is complicted nd not efficient. Since speed requirement for preprocessing prt is not s criticl, the microprocessor bsed system is suitble for the preprocessing prt. This thesis explins how to implement preprocessing prt on n embedded processor system together with the decoding prt on FPGA. The min contribution of this thesis is tht it explins how to develop embedded processor bsed system nd FPGA bsed lttice decoder on the sme progrmmble chip.

12 3 1.4 Orgniztion of Thesis Chpter 2 describes Alter system-on-chip. It ddition, it describes how to develop the whole system using SOPC builder nd Qurtus II softwre. It lso describes hrdwre ccelertion techniques. Chpter 3 gives informtion bout MIMO system. It lso describes detils of closest point serch lgorithm. Chpter 4 describes Strssen mtrix inversion method, QR decomposition using Householder mtrix, finding squre root, nd decoding the closest point serch lgorithm s prt of decoder. Chpter 5 tells how to develop interfce between Nios processor bsed system nd FPGAs. It lso describes prodying of closest point serch lgorithm. Finlly, chpter 6 gives the simultion results obtined during this thesis reserch.

13 4 Chpter 2 Introduction to Alter System-On-Chip This chpter gives the introduction of Alter system-on-chip (Strtix EP1S10F780C6). It lso explins its progrmming techniques nd how to develop the whole system using SOPC builder nd Qurtus II softwre with hrdwre ccelertion techniques. 2.1 Introduction of Nios Development Bord Figure 2.1 Nios Development Bord

14 5 The figure 1.1 [7] shows Nios development bord. It hs following fetures: 1. Progrmmble chip Strtix EP1S10F780C Mbytes of sttic RAM, 16 Mbytes of SDRAM, 8 Mbytes of flsh memory 3. On bord logic for configuring the progrmmble chip from flsh memory 4. Two RS-232 seril ports for seril communiction MHz clock genertor 6. Dul 7-segment LED disply nd LCD disply 7. JTAG connector which is used to lod hrdwre imge from host computer 2.2 Generl Description The Nios development bord, Strtix edition, provides hrdwre pltform for developing embedded systems bsed on Alter Strtix devices. The Nios development bord fetures Strtix EP1S10F780C6 device with 10,570 logic elements (LEs) nd 920 Kbits of on-chip memory. When power is pplied to the bord, the on-bord configurtion logic configures the Strtix FPGA using hrdwre configurtion dt stored in flsh. When the device is configured, the Nios processor design in the FPGA wkes up nd begins executing boot code from flsh memory. User defined softwre nd hrdwre configurtion dt cn be downloded to the bord from host computer. Downlod methods include seril cble, JTAG downlod cble, or n Ethernet cble. At power on, or when the Reset, Config button (SW10 in figure1.1) is pressed, the configurtion controller reds user configurtion dt out of flsh t ddress 0x This dt, nd suitble control signls, re used in n ttempt to configure the FGPA. FPGA Imge configurtion dt written into this region of flsh memory is conventionlly clled the

15 6 User Hrdwre Imge. If there is no vlid User Hrdwre Imge, or if SW9 (Sfe Config in figure1.1) is pressed, the configurtion controller begins reding dt out of flsh t ddress 0x Any FPGA configurtion dt stored t this loction is conventionlly clled the Sfe Hrdwre Imge. The development bord ws fctory progrmmed with Sfe Hrdwre Imge EP1S10 Device Device U53 in figure1.1 is Strtix EP1S10F780C6 FPGA in 780-pin FineLine BGA pckge. Tble 1 lists the Strtix device fetures. LEs 10,750 Totl RAM bits 920,448 DSP blocks 6 Embedded multipliers 48 Mximum user I/O pins 426 Tble 2.1 Strtix EP1S10 Device Fetures There re two methods for configuring Strtix device: 1 By using the Qurtus II softwre running on host computer nd JTAG connector, we cn downlod hrdwre imge file into Strtix device. 2 Store hrdwre imge into flsh memory so tht on bord configure logic configure the device during the reset or when power is pplied to the bord.

16 Flsh Memory Device Device U5 in figure 1.1 is n 8 Mbyte AMD AM29LV065D flsh memory chip connected to the Strtix device nd cn be used for two purposes: 1. It cn be used s generl-purpose redble memory nd non-voltile storge. 2. It is minly used to store hrdwre imge creted by user or defult hrdwre imge. It lso used to store softwre progrm for Nios embedded processor Seril Port Connectors J19 & J27 in figure1.1 re the seril connectors used for communiction with host computer using stndrd, 9-pin seril cble connected to the seril port of host computer. The Nios bord development provides two seril connectors, one lbeled Console nd the other lbeled Debug. Mny processor systems mke use of multiple UART communiction chnnels during prototype nd debug stges. When we use printf commnd in softwre code of Nios processor, the Nios system sends dt to the host computer using debug seril connector. Both connectors connect to the Strtix FPGA in the sme mnner, nd Nios processor system cn use either seril port for ny purpose, nd is not limited to the usge implied by the lbel. Both FPGA logic ports re ble to trnsmit ll RD-232 signls. Alterntively, the Strtix design my use only the signls it needs, such s RXD nd TXD. LEDs re connected to the RXD nd TXD signls, giving visul indiction when dt is being trnsmitted or received.

17 8 2.3 Design Tools Alter provides three design softwre tools to develop system on progrmmble chip. They re: 1. Qurtus II 2. SOPC builder 3. DSP builder Qurtus II Qurtus II is used to integrte Nios processor bsed system creted using SOPC builder with other hrdwre block. It is lso used to synthesize system design nd downlod into Strtix EP1S10F780C6 device SOPC Builder The SOPC builder is system integrtion tool included in the Qurtus II softwre tht provides designers with powerful pltform for composing memory-mpped systems from common system components. SOPC Builder librry components cn be either simple blocks of fixed logic, or complex, prmeterized, nd dynmiclly generted subsystems. Exmples of SOPC Builder librry components include: 1. Processors (Exclibur stripe & Nios embedded processor) 2. Intellectul property (IP) & peripherls (including SOPC Builder Redy IP cores) 3. Bridges (AMBA AHB-to-Avlon, Avlon-to-PCI) 4. Softwre (compilers, debuggers & rel-time operting system (RTOS))

18 9 In ddition to the integrted FPGA solution generted, SOPC Builder provides softwre files for developing simple to complex pplictions. Exmples of the SOPC Builder file outputs include: 1. Heder files 2. Generic C drivers 3. OS kernels 4. Softwre Models for hrdwre-softwre co-simultion DSP builder DSP system design in Alter progrmmble logic devices requires both high-level lgorithm nd hrdwre description lnguge (HDL) development tools. The Alter DSP Builder integrtes these tools by combining the lgorithm development, simultion, nd verifiction cpbilities of The MthWorks MATLAB nd Simulink system-level design tools with VHDL synthesis, simultion, nd Alter development tools. The DSP Builder shortens DSP design cycles by helping designers crete the hrdwre representtion of DSP design in n lgorithm-friendly development environment. The existing MATLAB functions nd Simulink blocks cn be combined with Alter DSP Builder blocks nd Alter intellectul property (IP) MegCore functions to link system-level design nd implementtion with DSP lgorithm development. DSP Builder llows system, lgorithm, nd hrdwre designers to shre common development pltform. Designers cn use the blocks in DSP Builder to crete hrdwre implementtion of system modeled in Simulink in smpled time.

19 System Components Nios embedded processor-bsed systems include one or more Nios CPUs nd the Avlon switch fbric. Nios processor-bsed systems cn lso contin multiple bus msters, such s multiple Nios CPUs Designers cn crete nd integrte these multimster systems esily when using Alter s SOPC builder system development tool. SOPC Builder utomticlly genertes the interfce to ll of these components. The following components cn be used to form Nios processor-bsed embedded system: 1. Nios CPU 2. Cche memory 3. Avlon switch fbric 4. Peripherls nd memory interfce 5. On chip debug Designers cn use SOPC Builder to custom-build Nios processor-bsed systems to their own specifictions. Figure 1.2 [7] shows n exmple of Nios processor-bsed system built using SOPC Builder. This prticulr system contins Nios CPU with instruction nd dt cche, n on-chip debugging core, direct memory ccess (DMA) controller, severl peripherls such s UART, prllel I/O (PIO), n Ethernet port, nd memory interfces, nd simultneous multi-mster Avlon switch fbric.

20 11 Nios D-cche CPU I-cche On-Chip Debug DMA Controller Avlon Switch Fbric Dt Memory Instruction Memory SDRAM Controller UART PIO Ethernet 10/100 Figure 2.2 Nios Processor-Bsed System CPU Architecture The Nios embedded processor CPU instruction set rchitecture is optimized for progrmmble logic nd system-on--progrmmble-chip (SOPC) integrtion. The Nios CPU is five-stge pipelined generl-purpose RISC microprocessor tht supports both 32-bit nd 16-bit rchitecturl vrints. Both the 32-bit nd 16-bit Nios CPUs utilize 16-bit instruction formt to reduce code footprint nd instruction memory bndwidth. The instruction set is optimized for compiled embedded pplictions. The Nios embedded processor implements the CPU with seprte dt nd instruction-memory bus msters, generlly known s modified-hrvrd memory rchitecture. The SOPC builder llows users to esily specify connections between both Avlos msters nd slves in system. These slves my be memories or peripherls.

21 Instruction Set The Nios instruction set is tilored to support compiled C nd C++ progrms. It includes stndrd set of rithmetic nd logicl opertions nd instruction support for bit opertions, byte extrction, dt movement, control flow modifiction, s well s smll set of conditionlly executed instructions, which cn be useful in eliminting short conditionl brnches. The instruction set contins rich ddressing modes to reduce code size nd increse the processor performnce Register File The Nios CPU rchitecture hs lrge generl-purpose windowed register file, severl mchine-control registers, progrm counter, nd the K register tht is used for instruction prefixing. The generl-purpose registers re 32 bits wide in the 32-bit Nios CPU nd 16 bits wide in the 16-bit Nios CPU. The register file size is configurble nd contins totl of 128, 256, or 512 registers. The softwre cn ccess the registers exposed in 32-register-long sliding window tht moves with 16-register grnulrity. This sliding window llows fst context switching, ccelerting subroutine clls nd returns Cche Memory The configurble Nios CPU cn optionlly contin n instruction nd dt cche. In generl, cche is used to improve CPU performnce by providing locl memory system tht cn respond quickly to CPU-generted bus trnsctions. The Nios cche

22 13 implementtion is simple, direct-mpped, write-through rchitecture tht is designed to mximize performnce nd minimize device resource consumption Exception Hndling The Nios processor llows up to 64 vectored exceptions, which cn be generted from ny of these three sources: externl hrdwre interrupts, internl exceptions, or explicit softwre trp instructions. The Nios exception-processing model llows precise hndling of ll internlly generted exceptions. Users cn optionlly disble support for TRAP instructions, hrdwre interrupts, nd internl exceptions. This option reduces the size of the Nios system, nd is intended for use only in systems where the processor is not running complex softwre Hrdwre Accelertion The Nios instruction set cn be configured to tke dvntge of hrdwre to increse system performnce. Specific cycle-intensive softwre opertions cn be offloded to hrdwre, incresing system performnce significntly. This feture is provided through instruction set modifictions. The Nios processor hs two levels of instruction set modifictions: 1. Custom instructions 2. Stndrd CPU options

23 Custom Instructions Developers cn ccelerte time-criticl softwre lgorithms by dding custom instructions to the Nios processor instruction set. Developers cn use custom instructions to implement complex processing tsks in single-cycle (combintoril) nd multi-cycle (sequentil) opertions. Additionlly, user-dded custom instruction logic cn ccess memory nd/or logic outside of the Nios system. Figure 1.3 shows block digrm of the instruction logic[7]. Figure 2.3 Custom Instruction Logic A complex sequence of opertions cn be reduced to single instruction implemented in hrdwre. This feture empowers developers to optimize their softwre inner loops for digitl signl processing (DSP), pcket heder processing, nd computtion- intensive pplictions. The Alter SOPC builder softwre provides grphicl user interfce (GUI) tht developers cn use to dd up to five of their own custom instructions to the Nios embedded processor.

24 Stndrd CPU Options Alter provides severl pre-defined instruction set extensions to increse softwre performnce. The MUL nd MSTEP instructions re implemented with dditionl hrdwre units. When you select either of these CPU options in the SOPC Builder, logic is dded to the rithmetic logic unit (ALU). For exmple, if user chooses to implement the MUL instruction, n integer multiply unit is dded utomticlly to the CPU's ALU to return 16-bit by 16-bit multipliction opertion in two clock cycles. This sme opertion performed using n itertive softwre routine would tke 80 clock cycles. Tble 1.2 [7] shows number of clock cycles for multipliction using hrdwre nd softwre multiplier. Multipliction Logic Elements Used Cycles Cycles None(softwre) MSTEP MUL Tble 2.2 Comprison of Different Nios processor Multipliers Additionlly, the Nios CPU includes n internl shift unit for executing logicl nd rithmetic shift instructions. The CPU uses fixed brrel-shifter logic tht executes ll shift opertions in two clock cycles.

25 16 Chpter 3 Multiple Input Multiple Output Systems nd Lttice Decoder This chpter explins the concept of multiple input multi output (MIMO). It lso explins the closest point serch lgorithm used s the chnnel decoder in MIMO receiver. 3.1 Multiple-input multiple output (MIMO) system Dt Processing Seril to prllel converter Dt Processing Dt Processing Dt Processing Figure 3.1 MIMO Trnsmitter RF Frontend Bsebnd Processor Decoder Figure 3.2 MIMO Receiver

26 17 The digrms shown bove re schemtic representtion of multiple input multiple output (MIMO) systems [4]. MIMO systems use multiple ntenns in both trnsmitters nd receivers Trnsmitter At trnsmitter side, the incoming seril strem of dt is first converted into M prllel strems. After de-multiplexing of seril dt, M prllel dt strems re processed nd trnsmitted using M ntenns Receiver decoder. The MIMO receiver hs three min prts RF-frontend, bsebnd processor nd (i) RF-frontend: It receives dt from N prllel ntenns nd converts nlog dt into digitl form. (ii) Bsebnd processor: It receives smples from RF- frontend, extrcts timing informtion nd chnnel informtion (chnnel mtrix coefficients). (iii) Decoder : The received signl y is given by y = Hx + noise where H is chnnel mtrix nd x is trnsmitted vector. The decoder computes the vector u ) using H nd y such tht u ) is closest to x. The resons for use of MIMO techniques re (i) (ii) To increse mximum dt rte To extend coverge

27 18 (iii) To serve lrge number users 3.2 Closest Point Serch in Lttices In severl communiction systems, the received signl is given by liner combintion of the trnsmitted dt symbols nd dditive noise. The input output reltion describing such chnnels cn be put in the form of the rel multiple-input multiple-output (MIMO) liner model y = Hx + v. In wireless communiction context, x, y, nd v re the trnsmitted, received, nd the dditive white Gussin noise vectors, wheres H contins the chnnel coefficients. Typiclly, the noise components re independent nd identiclly distributed zero-men Gussin rndom vribles with common vrince, nd the informtion signl (x) is uniformly distributed over discrete nd finite set, representing the trnsmitter codebook. Under such conditions nd ssuming H perfectly known t the receiver the mtrix H genertes lttice tht we denote s (H), the mximum-likelihood (ML) estimte u ) for x is obtined by minimizing the Eucliden distnce of y from the vlid lttice points.the closest point problem is: Given y nd lttice (H) with known genertor H, find the lttice vector u ) (H) tht minimizes the Eucliden distnce from y to u ) such tht x u ) x u Where. denotes the Eucliden norm. In chnnel coding, the closest point problem is referred to s decoding. In communiction theory, lttices re used for both modultion nd quntiztion. If lttice is used s code for the Gussin chnnel, mximumlikelihood decoding in the demodultor is closest point serch. A common pproch to

28 19 the generl closest point problem is to identify certin region in m R within which the optiml lttice point must lie, nd then investigte ll lttice points in this region, possibly reducing its size dynmiclly. Up to now there re two typicl lttice decoding lgorithms. One is the Pohst strtegy bsed lgorithm developed by Viterbo nd Boutros (VB) [6], nd the other is the Schnorr-Euchner strtegy bsed lgorithm pplied by Agrell, Eriksson, Vrdy, nd Zeger (AV) [1]. The VB method tries to find lttice points inside sphere of given rdius. AV method divides the lttice into hyperplnes nd strts the serch for the closet point in the nerest hyperplne. Both lgorithms hve high complexities in most prcticl situtions. The AV lgorithm is climed to be fster thn the VB lgorithm t speedup fctor vrying from 2 to 8 [1]. In ddition, to serch the closest lttice point to the received signl within sphere, the rdius of the sphere C must be specified in the VB lgorithm nd the choice of C is very crucil to the serch speed of the lgorithm. Herein, we ddress the closest point lgorithm by using AV Conceptul Description of Closest Point Serch Algorithm Let H be the chnnel coefficient mtrix nd y be the received vector. The bsic steps of AV lgorithm to find vector u ) re s follow: 1. Decompose H into H = GQ where G is the lower tringulr mtrix nd Q is the orthogonl mtrix. The stndrd method to chieve such decomposition is the QR decomposition. The QR decomposition decomposes given mtrix A into Q nd R where Q is the orthogonl mtrix nd R is the upper tringulr mtrix. The G is the lower tringulr mtrix while R is the upper tringulr mtrix, T G = R

29 20 2. Find 1 G 1 = G nd x = 1 T yq 3. Find u ) ) by using G1 nd x 1 ( u = DECODE( x 1, G1) ) such tht the vector u ) H is closest to the trnsmitted signl x. In the beginning the function DECODE ( x1, G1) initilize k = n, bestdistnce = 8. It finds e k = x1g 1, u = round e ) nd orthogonl distnce k ( kk b e u G kk k =. After finding 1kk currentdistnce by using b it enters into either stte A, stte B or stte C depending on the currentdistnce. It enters into stte A if currentdistnce = bestdistnce nd k? 1. It enters into stte B if currentdistnce < bestdistnce nd k = 1. It enters into stte C if currentdistnce =bestdistnce. In stte A it finds ek 1 = ek bg1k, orthogonl distnce nd moves down in lyers. In stte B it stores lttice point uk into u nd mkes bestdistnce= currentdistnce. It lso finds currentdistnce nd moves one step up in hierrchy of lyers. In stte C if k = n then it stop serching otherwise finds currentdistnce nd moves one step up in hierrchy of lyers. In order to work, ll the digonl elements of the G 1 must be positive. If they re not positive, we hve to mke them positive explicitly.

30 21 Chpter 4 Algorithms This chpter explins in detil different lgorithms such s Strssen mtrix inversion method, QR decomposition using Householder mtrix, finding squre root nd decoding lgorithm (prt of closest point serch lgorithm) used in this thesis work. 4.1 Decoder Algorithm Decode(H, x) Input: n n n lower-tringulr mtrix H with positive digonl elements, nd n n- 1 dimensionl vector x to decode in the lttice ( H ). H h11 h21 =. hn1 h h n h 0. 0 nn x = ( x1. x2... xn ) Output: n n-dimensionl vector u ) 1 such tht u ) H is lttice point tht is closest to x.

31 22 Define n = size of H Define bestdist = bestdist represents current distnce Define k = n, stop = 0 k represent distnce to exmined lyer Define vector dist of size k, dist k = 0 dist represents distnce of lttice point to corresponding lyer Define mtrix e of size n n e is used to compute u k e k = xh u k = kk e, y = e u kk h kk k, step k = sgn*(y) u represents exmined lttice point k step represents offset to next lyer k newdist = dist + k 2 y N stop=1 Is newdist < bestdist? Y exit N N Is k = 1 Stte A Stte B Stte C Y Y Figure 4.1 Flow Chrt of Decoding Algorithm

32 23 Stte A e k 1, i = e ki yh ki for i = 1,.k - 1 k = k 1 u k = kk e, dist k = newdist y = ekk u h kk k, step k = sgn*(y) Figure 4.2 Flow Chrt of Stte A of Decoding Algorithm Stte B u k = k ) u = u, k = k +1 bestdist = newdist ekk u u k + stepk, y = h step = step + sgn* ( step ) k kk k k Figure 4.3 Flow Chrt of Stte B of Decoding Algorithm

33 24 Stte C Is k = n? stop = 1 u k = k k k = k +1 u + step, y = k ekk u h step = step + sgn* ( step ) k kk k k Figure 4.4 Flow Chrt of Stte C of Decoding Algorithm In this lgorithm, k is the dimension of the sublyer structure tht is currently being investigted. In stte A this lgorithm performs three steps: 1. finding k dimensionl lyer 2. finding distnce to lyer 3. fter finding distnce expnd lyer into ( k -1) Stte B is invoked when the lgorithm hs successfully moved down ll the wy to the zero-dimensionl lyer (tht is, lttice point) without exceeding the lowest distnce. In this stte this lgorithm store lttice point s output nd updte the lowest distnce. Stte C is invoked when distnce to exmined lyer is greter thn lowest distnce. In this stte this lgorithm checks condition to stop the serch. If condition to stop is not meet thn it moves up one step in hierrchy of lyer.

34 25 The opertion sgn*(z) returns: sgn*(z) = -1 if z = 0 = 1 if z > 0 [z] = integer closet to z i.e. [2.4] = 2 nd [2.6] = 3 In hrdwre [z] cn be implemented in following wy. Suppose z is mplified by p where S p = 2. If S -1 bit of z is 0 then reset S-1 to 0 bits of z S s zeros. If S -1 bit z is 1 then p = 2. If S -1 bit of z is 1 then reset S-1 to 0 bits of z s zeros nd dd S 2 to z. 4.2 A geometric view of the squre root There re two fcts concerning the squre of n integer tht re useful in the inverse process of finding the squre root. The first concerns the number of digits. If 0 < < 10 then 0 < 2 < 100, if 10 < < 100 then 100 < 2 < , if 100 < < 1000 then < 2 < , nd so on. The point to see here is tht the squre of n integer hs either twice s mny digits s the integer itself, or one less thn twice s mny. So, since 9,409 hs 4 digits its squre root hs 2 digits, nd the squre root of the 13 digit number 3,871,696,594,290 hs 7 digits. The second fct concerns the "geometry" of squring number. Consider, for exmple, the squre of 249 so the geometric object to consider is squre with side of length 249 units. Write 249 s then the squre cn be seen s

35 26 Figure 4.5 Geometric view of the squre of three digit number The squre of 249 is 200x (200x40) + 40x40 + 2(240x9) + 9x9 = Now to find the squre root of n integer you need first to determine the number of digits there will be. Let us find the squre root of Since hs 5 digits, the squre root of will hve 3 digits. A squre of 3 digit number is divided into 7 prts s shown in the digrm Figure 4.6 Geometric view of the squre of three digit number

36 27 To find the squre root of divide the number in group of two s nd strt with the group of digits nerest to the left (in this cse 6). This represents the squre of. We know tht the lrgest perfect squre less tht 6 is 4, nd tht the squre root of 4 is 2. Since 2 must be plced in the hundreds position, we cn sy = 2*100. The re of region 1 is 200x200 = We then subtrct this re from the totl re of By looking t the digrm we relize tht next we should remove the res of the two regions whose sides re nd b (region 2 nd 3). To find the length of b we must estimte the quotient of by 400. The 400 is rrived t by reclling tht two regions, ech of which hs length of 200, would hve n overll length of 2(200) = 400. The quotient of by 400 is pproximtely 60. However looking gin t our digrm we relize tht besides region2 nd 3, we lso must subtrct n re of b x b (region 4). Since 2 x 200 x 60 = we re left with only 9, but we need to subtrct b x b which is 60 x 60 = Thus we reduce our estimte of b to 50, nd plce 5 in the tens position of the squre root clcultion. Two rectngles (region 2 nd 3), ech 200 units by 50 units, hve totl re of squre units. Subtrcting from leves Agin, going bck to the digrm we note tht the re (region 4) of b x b tht must be subtrcted is now 50 x 50 = Subtrcting from leves

37 28 Returning to the digrm we note tht next we must subtrct the res of the two regions which hs length of + b = 250 units ech. The unknown quntity c cn now be estimted by the quotient of by is rrived by plcing the two regions together to rrive t rectngle with length 2 x 250 = 500. The quotient of by 500 is pproximtely 3. Plce 3 in the units position of the squre root clcultion nd subtrct the sum of the res of regions 5 nd 6, which is 2 x 250 x 3 = Subtrcting from leves 9. From the digrm the region 7 is the only region not subtrcted so fr nd its re is c x c = 3 x 3 = 9. Subtrcting 9 from our previous reminder leves us with reminder of 0. Thus the squre root of is 253. The Squre root Algorithm: Input: positive integer x. Output: root = x rounded towrd zero. w = [1, 10,100 ] w represents weight ssocited with number Divide number x into groups of two d = no of digits in root ( no of groups) i = d-1 i is used index of w Find p such tht p = first group ( left most) p represents perfect squre q = SQRT ( p ) A figure continued on next pge

38 29 A C N Is d = 1? root = q n = x w i 2 root Y root = q EXIT i = i - 1 dd = root 2 quotient = round ( n dd ) quotient = round( quotient -w i ) wi N done = 0 Is quotient = 0? Y done = 1 Is done = 0? Y B 2 m = n (( dd quotient) + quotient N ) Is m = 0 N done = 1 n = m root = root + quotient Y quotient = quotient w i figure continued on next pge

39 30 B d = d -1 C Y Is d 1 N return root nd exit Figure 4.7 Flow Chrt of Squre root Algorithm In this lgorithm we need to find number of digits (d) in squre root of given number (x). This cn be implemented s follow: d = 2 if 0 x 99 d = 3 if 100 x 9999 d = 4 if x The function SQRT ( p ) in bove lgorithm returns q s follow: q = 9 if p > 80 q = 8 if p > 63 nd p 80 q = 7 if p > 47 nd p 63 q = 6 if p > 35 nd p 47 q = 5 if p > 24 nd p 35

40 31 q = 4 if p > 15 nd p = 24 q = 3 if p > 8 nd p = 15 q = 2 if p > 3 nd p = 8 q = 1 if p > 0 nd p = 3 q = 0 if p = Strssen Mtrix Inversion Method Suppose mtrix C is the inverse of mtrix A. If the size of A is N N, the size of C is lso N N. In Strssen method the mtrix A is divided into four sub mtrix A 11, A 12, A 21, A 22 in such wy tht number of rows in A 11 equl to number of columns in A 21. A A = A A A C nd C = C C C Let A =.. M P.. N M.. MM PM.. NM 1P.. MP PP.. N P N.. MN PN.. NN A 11, A 12, A 21, A 22 given by A 11 =.. M M.. MM A 12 = 1.. P MP N MN A 21 = P.. N P M.. NM A 22 =.. PP NP P N.. NN

41 32 where M = 2 N if N = even M = round N 2 if N = odd P = M + 1 Strssen Mtrix Inversion Algorithm: Input: N N mtrix A Output: N N mtrix C such tht C = A 1 Divide A into four sub mtrix A 11, A 12, A 21, A 22 R1 = A 1 11 R2 = A 21 R1 R3 = R 1 A12 R4 = A 21 R3 R5 = R4 A22 X figure continued on next pge

42 33 X R6 = R 5 1 C 12 = R3 R6 C 21 = R6 R2 R 7 = R3 C 21 C11 = R1 R7 C 22 = R6 Figure 4.8 Flow Chrt of Strssen Mtrix Inversion Algorithm

43 Reduction of Strssen Mtrix Inversion lgorithm for 4 4 lower tringulr mtrix If mtrix is lower tringulr, it s inverse is lso lower tringulr. Let A nd C re inverses of ech other. A = C = c c c c c c c c c c A 11 = A 12 = A 21 = A 22 = ) R 1= A 11 1 R1 = 1 d where d1 = ) R2 = A 21 R1 R2 = d R2 = d 1 r r r r where r r r r = = = = * * * * * * ) R3 = 0 ( Q 12 = 0) 4) R4 = 0 ( Q R3 = 0)

44 35 5) R5 = - A 22 ( Q R4 = 0) 33 0 = ) R 6 = R5 1 = 1 d where d2 = ) C 12 = 0 ( Q R3 = 0) 8) C 21 = R6 R2 C 21 = 1 d d1 r r r r = 1 d 2 * d1 h h h h where h h h h = = = = * r * r 11 * r * r * r * r ) R7 = 0 ( Q R3 = 0) 10) C 11 = R1 ( Q R7 = 0) C 11 = 1 d ) C 22 = - R6 C 22 = 1 d The inverse C of 4 4 lower tringulr mtrix A is given by C C = C C C 12 22

45 36 22 d1 21 C = d1 h11 d1* d2 h21 d1* d d1 h12 d1* d2 h22 d1* d d2 43 d d2 where d1 = d2 = h h h h 11 = 44 r11 12 = 44 r12 21 = 43 r11 33 * r21 22 = 43 r12 33 *r22 r 11 = * * 21 r = *11 r r 21 = * 22 = * QR decomposition of mtrix The mtrix A cn be decomposed into A = QR Here R is upper tringulr mtrix, while Q is orthogonl mtrix, tht is, T QQ = I w here T Q is the trnspose mtrix of Q. The stndrd lgorithm for the QR decomposition involves successive Householder trnsformtions An pproprite Householder mtrix

46 37 pplied to given mtrix cn zero ll elements in column of the mtrix situted below chosen element. Thus we rrnge for the first Householder mtrix Q 1 to zero ll elements in the first column of A below the first element. Similrly Q 2 zeroes ll elements in the second column below the second element, nd so on up to Qn 1Thus R n 1 Q = Q... 1 Q A 1 ( Qn 1... Q1 ) = Q1... Q 1 = n Householder Mtrix The Householder trnsformtion is often described in terms of multipliction by mtrix known s Householder mtrix. A Householder mtrix hs the form H 2 T = I WW where W is column vector. The formtion of the Householder mtrix to reduce to zero vector X from position k to position n is summrized in the following lgorithm: Given n n-dimensionl vector X nd n index k such tht 1 k n 1 find vector W so tht the mtrix H 2 T = I WW reduces positions k+1,, n of vector X to zero, so the vector HX hs the form [ Z, Z... 2 ZK,0,0, Set Wi = 0 for i =1,,k-1. 1 ] T 2. Find g = X k +... X n Find s = g ( g + X ) 4. Set W k 2 k ( X k + sgn( X = s k ) g

47 38 X i 5. Set Wi = for i = k+1,,n s QR Decomposition Algorithm: Input: n n n mtrix A Output: n n upper tringulr mtrix R nd n n orthogonl mtrix Q. k = 1, B = A, R = 0 BB mx = MAX( A kk A( k 1) k,..., + A ) nk Akk, A( k+1) k.... A mx nk 2 kk Sum = A + A + 2 ( k 1) k... Ank 2 S = SIGN( Sum, Akk ) A = S + kk A kk C = S k A kk d k = mx S AA figure continued on next pge

48 39 AA j = k + 1 S... A 1 = Akk Akj + A( k+ 1) k A( k + 1) j + nk A nj T S1 = C k A = A T A pk pj pk p vries from k to n j = j 1 Y Is j= n? N k = k 1 BB Y Is k< n? CC N figure continued on next pge

49 40 CC Y R ii = d i, x = 1 i vries from 1 to n N R xy = A xy y vries from x + 1 to n x = x + 1 Y Is x = n? Q = BR 1 N exit Figure 4.9 Flow Chrt of QR Decomposition Algorithm In the bove lgorithm opertion MAX(p1,p2...pn) finds bsolute vlue of p1,p2...pn nd then return mximum bsolute vlue e.g. MAX (-2.1,1.0) returns 2.1. The opertion SIGN ( M, N) returns y s follow: y = M if N > 0 y = -M if N < 0

50 41 Chpter 5 Prototyping of Closest Point Serch Algorithm This chpter explins how to prototype the closest point serch lgorithm on the Alter system-on-chip (Strtix EP1S10F780C6). 5.1 Why system-on-chip The MIMO prototyping is chllenging becuse of the complexity of the system. The lrge complexity of AV lgorithms needs to be prtition over DSP nd FPGAs. It lso requires the presence of interfce drivers to support intercommuniction between DSP, FPGAs. By using system-on-chip we cn develop microprocessor bsed system, hrdwre logic nd driver to communicte between microprocessor bsed system nd hrdwre logic on the sme chip. The min gol is to develop pltform for prllel execution of the preprocessing unit nd the lttice decoder, therefore improving the overll performnce nd decoding rte (Mbps) of the MIMO chnnel decoder. 5.2 Prototyping Closest Point Serch Algorithm We cn divide the closest point serch lgorithm into two prts 1) preprocessing nd 2) decoding. Preprocessing contins QR decomposition of chnnel mtrix nd mtrix inversion while decoding contins serch of vector in mtrix.

51 42 QR involves opertions like finding squre-root, floting point multipliction, division. FPGAs re not suitble for QR decomposition nd mtrix inversion. These opertions re performed by using NIOS embedded processor in the FPGA. If we nlysis AV lgorithm in detils, it is found tht there re three different sttes A, B, C. For given k (lyer index) stte A performs clcultions for k-1 lyer, while sttes B, C perform clcultions for lyer k. It mens tht dt for stte B nd C re not depended on dt from stte A. Becuse serch procedure cn jump to either stte B or C fter performing ste A nd no dt dependency of stte B, C on stte A, we cn strt stte B nd C in prllel with stte A. We cn ccept or reject the output from stte B or C depending on result of stte A. If current stte is C, we cn strt nother stte C in prllel with first stte C. Depending on the result of first C; we cn ccept or reject the output of second stte C. Such prllelism cnnot be chieved by using microprocessor so we use FPGAs to model decoder. The following digrm shows rchitecture of closest point serch lgorithm. Stte A NIOS Microprocessor Bsed System Hrdwre Controller Stte B Stte C Stte C Figure 5.1 Hrdwre rchitecture of lttice decoder

52 43 Controller is the most importnt prt of the lttice decoder. It is used to control dt between Stte A, B, C nd NIOS microprocessor bsed system Interfce between Nios microprocessor bsed system nd Controller redy redy Nios Microprocessor Bsed System send dt send dt Controller Figure 5.2 Interfce between Controller nd NIOS Microprocessor Bsed System C code for NIOS System. Loop: VHDL code for Controller... process( redy) Put dt on bus Activte redy signl red dt Wit for send signl ctivte send signl Go to loop.. End Loop; end process;

53 44 NIOS microprocessor bsed system computes QR nd R inversion nd trnsfer Q nd R mtrix to the controller. NIOS microprocessor bsed system trnsfer one row of Q nd R mtrix t time. When it is redy to trnsfer the dt, it ctivtes the redy signl. This redy signl is in sensitivity list of process of controller so it triggers the process. The process in controller red the dt nd ctivte send signl. The send signl is used to interrupt the NIOS microprocessor bsed system so tht it cn send next dt Interfce between Stte A, B, C nd Controller Controller Strt A Redy Dt strt B Redy Dt Strt Redy Dt Strt Redy Dt Stte A Stte B Strt C1 Redy Dt Strt C2 Redy Dt Strt Redy Dt Strt Redy Dt Stte C1 Stte C2 Figure 5.3 Interfce between Controller nd Stte A, B, C

54 VHDL Code Structure of Controller for Interfce with Stte A, B, C: rchitecture of controller is k := n CURRENT_STATE <= A STATE_CHANGE <= 0. begin P1: process ( CURRENT_STATE) begin If ( CURRENT_STATE = A) then put dt on bus for stte A, B, C1 nd strt them wit for result from stte A store dt from stte A from result of stte A check wht is next stte fter A store or discrd result form B, C1 depending on stte A end if If ( CURRENT_STATE = C) then put dt on bus for stte C1, C2 nd strt them wit for result from stte C1 store dt from stte C1 from result of stte C1 check wht is next stte fter C1 store or discrd result form C2 depending on stte C1

55 46 end if STATE_CHANGE <= 1 end process P1 P2: process (STATE_CHANGE) begin if ( new distnce < best distnce ) then CURRENT_STATE <= A else CURRENT_STATE <= C end if end process P2 end rchitecture

56 47 Chpter 6 Results This chpter gives the experimentl results obtined for both the preprocessing nd decoding prt of the MIMO decoder. 6.1 Results of Pre-processing Prt The pre-processing prt is executed on Nios microprocessor bsed system which runs t frequency of 50MHz on the Strtix EP1S10F780C6 device. Using the Division custom instruction, the mximum frequency is 50MHz Results of Division The tble 6.1 compres number of clock cycles required to perform division using Nios microprocessor without hrdwre divider nd with hrdwre divider. Nios microprocessor with divider uses divider s custom instruction ttched to Nios CPU.

57 48 b c = b Number of cycles With divider 31,111 1, With divider -31,111 1, Without divider 31,111 1, Without divider -31,111 1, Tble 6.1 Comprison of Nios Processor with & without divider to perform division Tble 6.1 clerly shows division is 1.6.times fster on Nios microprocessor with divider thn on Nios microprocessor with divider Results of Squre root The tble 6.2 compres number of clock cycles required to find squre root of integer (rounded towrd zero) using squre root lgorithm explined in 3.2 nd C lnguge sqrt function. A Round( ) Number of cycles using C lnguge sqrt function Number of cycles using squre root lgorithm , , , , ,40, , Tble 6.2 Comprison of sqrt function in C lnguge nd squre root lgorithm

58 49 The tble 6.2 shows tht squre root lgorithm explined 4.2 in is fster thn sqrt C lnguge function. The reson is tht sqrt function uses floting point opertion (execution of floting point opertion on Nios fixed point processor tkes more cycles) nd squre root lgorithm explined in 4.2 uses hrdwre multiplier nd divider Results of Strssen Mtrix Inversion Method The tble 6.3 shows number of cycles required to invert 4 4 nd 8 8 lower tringulr mtrix using Strssen method. It clerly shows tht mtrix inversion using divider is lmost 3.5 times fster thn inversion without divider. Mtrix size Number of cycles using hrdwre divider Number of cycles without divider , ,755 17,820 Tble 6.3 Number of cycles required to invert 4 4 nd 8 8 lower tringulr mtrix using Strssen method Results of QR Decomposition of mtrix The tble 6.4 shows number of cycles required to perform QR decomposition of 4 4 mtrix. It shows tht use of divider, squre root lgorithm speed up QR decomposition of mtrix.

59 50 Mtrix size Number of cycles Number of cycles Number of cycles with multiplier with multiplier nd with multiplier, divider only divider nd squre root lgorithm ,508 19,307 6,929 Tble 6.4 Number of cycles required to perform QR decomposition of 4 4 mtrix Results of preprocessing prt decoding The tble 6.5 shows number cycles required to perform pre processing prt of Mtrix size Number of cycles 4 4 9, ,587 Tble 6.5 Number of cycles required to perform pre processing prt of decoding 6.2 Results of Decoding Prt Stte A, B, C of decoder nd controller to controller prllelism of A, B, C re developed using VHDL nd simulted using Aldec simultor. 18 clock cycles re required to complete stte A nd 9 clocks cycles re required to complete both stte B nd C. The mtlb nd C version of decoder re lso developed. The result from mtlb nd VHDL re mtched.

60 51 In order to test decoder we ssumed received signl is [-1,-3, 1, 1] nd chnnel mtrix H some rndom number H = Given n exmple, we set up the SNR s 20db. In this cse, the number of itertions to perform serch opertion in Mtlb is 9 nd serch procedure goes through following sequence of sttes. Itertion Stte A A A B A C C C C Tble 6.6 Sequence of stte in mtlb Itertion Stte A A A A C C Prllel stte B C C Tble 6.7 Sequence of stte in VHDL In VHDL we cn strt two sttes t the sme time so in itertion 3 sttes A nd B re executed t the sme time, similrly in itertion 4 stte A nd C, in itertion 5 sttes A nd C. In itertion 6 stte C tkes 2 cycles insted of 9 becuse t tht time k = M.

61 52 If we consider tht ll stte executes in sequence insted of prllel like mtlb, thn totl number of cycles required to complete serch opertion for this cse re s follow: 18 4 (number of times A come) (number of times B come) (number of times C come 1) + 2 (number of cycles for lst C) = 110 cycles Totl number of cycles to complete serch opertion if sttes re executed in prllel is s follow: = 83 cycles Becuse of prllelism we cn sve = 27 cycles for this cse. The bit rte of decoder is: (frequency bits_per_dimension N ) (totl number of cycles) N = 4 for 4 - ntenn system bits_per_dimension = 2 Totl number of cycles in cse of prllel rchitecture is 83 nd mximum frequency is 54 Mhz so bit rte in cse of 4.85 Mbits/secons. The sequentil decoder tkes 3571 cycles on Nios microprocessor bsed system which runs t 50 Mhz so in this cse dt rte is 0.11 bits/seconds.

62 Synthesis Result Trget FPGA Alter Strtix EP1S10F780C6 Totl logic elements 5,671/10,570 Totl pins 203/426 Totl memory bits 669,696/970,448 Totl DSP blocks 24/48 Totl PLL 1/6 Tble 6.8 Synthesis results of MIMO Lttice Decoder with Preprocessing Prt 6.3 Conclusion In this thesis work, the prllel rchitecture of lttice decoder is presented. The preprocessing prt of decoder hs been implemented on Nios microprocessor bsed system. The prllel rchitecture of decoder hs been simulted nd synthesized on FPGA nd its performnce is verified with softwre simultion. For the cse we considered in section 6.2, prllel rchitecture of decoder is 1.25 times fster thn sequentil rchitecture nd it is bout 43 times fster its implementtion on Nios microprocessor bsed system which runs t 50 Mhz, The dt rte of prllel rchitecture (for the cse in 6.2) is 5.2 Mbits/second which higher thn dt rte 0.11 Mbits/second.