IMPLEMENTATION OF TEMPLATED DSA FOR VIA LAYER PATTERNING AT THE 7 NM NODE. IMEC, Kapeldreef 75, B-3001 Leuven, Belgium 2

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1 IMPLEMENTATION OF TEMPLATED DSA FOR VIA LAYER PATTERNING AT THE 7 NM NODE Roel Gronheid 1, Jan Doise 1,2, Joost Bekaert 1, Boon Teik Chan 1, Ioannis Karageorgos 1,2, Julien Ryckaert 1, Geert Vandenberghe 1,Yi Cao 3, Guanyang Lin 3, Mark Somervell 4, Germain Fenger 5, Daisuke Fuchimoto 6 1 IMEC, Kapeldreef 75, B-3001 Leuven, Belgium 2 Katholieke Universiteit Leuven, Department of Electrical Engineering (ESAT), Kasteelpark Arenberg 10, B-3001, Leuven, Belgium 3 Merck Performance Materials, Kapeldreef 75, B-3001 Leuven, Belgium 4 Tokyo Electron America, Inc., 2400 Grove Boulevard, Austin, TX 78741, USA 5 Mentor Graphics (Belgium), Livornostraat 7 bus 4, B-1060 Brussels, Belgium 6 Hitachi High-technologies Corp., Hitachinaka, Ibaraki, Japan ABSTRACT In recent years major advancements have been made in the directed self-assembly (DSA) of block copolymers (BCP). Insertion of DSA for IC fabrication is seriously considered for the 7nm node. At this node the DSA technology could alleviate costs for double patterning and limit the number of masks that would be required per layer. At imec multiple approaches for inserting DSA into the 7nm node are considered. One of the most straightforward approaches for implementation would be for via patterning through templated DSA (grapho-epitaxy), since hole patterns are readily accessible through templated hole patterning of cylindrical phase BCP materials. Here, the pre-pattern template is first patterned into a spin-on hardmask stack. After optimizing the surface properties of the template the desired hole patterns can be obtained by the BCP DSA process. For implementation of this approach to be implemented for 7nm node via patterning, not only the appropriate process flow needs to be available, but also appropriate metrology (including for pattern placement accuracy) and DSA-aware mask decomposition are required. In this paper the imec approach for 7nm node via patterning will be discussed.. Keywords: Directed Self-Assembly, grapho-epitaxy, templated DSA flow, implementation, via patterning, cylinder phase block copolymer 1. INTRODUCTION Directed Self Assembly (DSA) is a rapidly maturing technology for advanced patterning for semi-conductor applications. DSA is based on the self-assembling properties of block copolymer materials, it offers a low-cost route to very dense and regular patterns. DSA will therefore need to be combined with traditional lithography techniques to 1) define the position where the patterns of interest are formed and (depending on the DSA implementation method) 2) define cuts and/or blocks to generate the more irregular structures that are typical for IC device layers. Several approaches for DSA have been proposed to define regular line/space patterns [1-4], line/space patterns with some irregular nature [5, 6], regular hexagonal hole patterns [7, 8], or more irregular and sparser hole patterns [9, 10]. DSA can thus be regarded as a chemical resolution enhancement technique. Similar to optical (off-axis illuminations, proximity correction, etc.) or process based (litho-etchlitho-etch, sidewall spacer patterning, etc.) resolution enhancement techniques, DSA will thus require specific design rules for implementation in patterning of real designs. In this paper it will be explored how templated hole patterning may be applied for defining the via1 layer in an N7 (or 7nm technology node) test design. The required process optimization will be described as well as considerations for design decomposition. It will be demonstrated that in order to make best use of

2 the patterning potentials of DSA for via layer definition, the arrangements of vias needs to be constrained by a set of relatively simple design rules. It is expected that the area penalty imposed by these rules will be minimal. 2.1 Materials and process 2. EXPERIMENTAL For template generation, spin-on carbon (SOC) HM710 and spin-on glass (SOG) ISX304 from JSR Micro are used with vendor recommended process conditions. Negative tone development photoresist AN02 from FUJIFILM is patterned on this stack using an ASML NXT:1950i ArF immersion scanner. The illumination conditions depend on the pre-pattern of interest, but in most typical cases, moderate off-axis illumination conditions are used (1.2NA, annular illumination, o/ i = 0.8/0.6). The resist patterns are transferred into the SOC using a TEL Tactras dry etch system and the SOG is removed (unless otherwise noted) using 0.5% HF on a TEL CELLESTA wafer clean system. Subsequently an appropriate brush from the EMD Performance Materials AZEMBLY series is applied, baked and rinsed on a TEL CLEAN TRACK ACT 12 system. Finally, a cylindrical phase poly(styrene-block-methyl methacrylate) (PS-b-PMMA, AZEMBLY PME585) BCP with a pitch of 37nm from EMD Performance Materials is coated and annealed. The PMMA cores are removed using a wet process on a TEL CLEAN TRACK ACT 12 or TEL CLEAN TRACK LITHIUS ProZ system. All pattern transfer studies were run on a TEL Tactras dry etch system. Wafers were analyzed using a Hitachi CG-4000 or CG-5000 top-down CD SEM. Robust Edge Detection (RED) software from Hitachi was used for image analysis. 3. RESULTS AND DISCUSSION 3.1 Templated DSA process The process flow for the templated DSA process has been described previously [9] and is schematically depicted in Figure 1. Briefly, a negative tone photoresist is patterned on an SOC/SOG stack. The resist pattern is transferred into the hardmask stack by dry etch. The photoresist is fully removed during the SOC opening. At this stage the BCP coating may be directly applied. From here onwards we will refer to this option as Flow #1. Alternatively, the SOG may be removed using diluted HF followed by spin coating of a brush material. After a grafting bake and solvent rinse, the brush will preferentially functionalize either the sidewalls of the template or the substrate at the bottom. For this different reactive groups of the brush are available. Furthermore the composition of the brush is varied to make it either more or less hydrophobic. In the further discussion we will consider 2 options for the brush. One which is moderately hydrophobic and preferentially grafts to substrate at the bottom of the template. This will be referred to as Flow #2. The other is a more hydrophobic materials which preferentially grafts to the sidewalls. This will be referred to as Flow #3. Figure 1. Schematic overview of the templated DSA process flow.

3 The surface energies will not only impact the 3-dimensional structure of the BCP inside the template [11] but also play a role on the preferred template dimension for commensurability with the BCP pitch. This is schematically illustrated in Figure 2. After dry etch, a template will typically be relatively hydrophobic. In the case of PS-b-PMMA this means that the minority PMMA block will preferentially wet both the bottom surface and the sidewalls of the template (left). By applying Flow #2 the bottom of the template can be made neutral, resulting in a more ideal vertical cylinder formation (middle). By making the sidewalls sufficiently hydrophobic, the wetting properties may be reversed, resulting in majority (PS) block wetting sidewalls (Flow #3). In this situation (right) the template CD for achieving commensurability is vastly smaller than for Flow #1 and #2. We will see that the latter flow has significant benefits for design decomposition and achievable pattern density. However, it should be noted that the definition of the pre-patterns for Flow #3 is more challenging from lithographic as well as etch perspective. For pattern transfer of a templated hole process, a neutral bottom surface is expected to be beneficial to avoid formation of a meniscus. Surface energy control of the bottom while maintaining PMMA (in case of Flow #2) or PS (in case of Flow #3) wetting sidewalls is thus crucial for a robust templated process. Figure 2. Schematic representation of arrangement of BCP material in template as a function of template surface energy properties and geometry. Flow #1 and #2 are compared for performance of their process window. An example for definition of hole doublets is given in Figure 3. The process window is based on formation of open holes as judged from top-down SEM imaging. It is observed that the open hole rate is a function of template area and fill. Interestingly, the exact shape of the template is relatively unimportant for reliable formation of the hole-doublet. These structures are formed from in pre-patterns that vary from relatively elongated to almost circular. The area (or volume) of the template is most determining for pattern definition. It should be noted here that the geometry of the pre-pattern does impact the placement of the two holes within the template. In practice, this will put additional constraints on the usable template geometries in order to maintain control over positional accuracy. Initial data indicates that the sensitivity of Flow #2 to variations in the template pre-pattern dimensions are significantly smaller than for Flow #1. However, the impact of metrology noise on the placement accuracy data is presently unclear. The SOG strip results in a significant loss of SEM contrast after the full BCP processing, making the SEM-based edge detection of the template noisy. This effect hampers the accuracy of the placement accuracy data, especially for Flow #2 and #3. Besides template geometry, also the BCP fill level impacts the open hole rate of the templated DSA process. The templated fill is defined as the local BCP film thickness in the template. Since the BCP reflows from on top of the template into the holes, the fill level is a function of various parameters, including nominal BCP coating thickness, local pattern density [9, 12] and annealing conditions. Ideally, the fill level should be determined from 3D profile analysis after BCP anneal, but we have developed a quick method for estimating template fill from top-down SEM images [13]. It is clear from Figure 3 (left) that the fill has significant impact on the process window for Flow #1. This is attributed to the 3-dimensional character of the BCP profile for this Flow. In the case a meniscus is present, a thicker film will at some point result in a PS skin layer being formed on top (this approaches the morphology of a parallel cylinder). From top-down SEM imaging this results in a closed hole. By contrast, Flow #2 is much more robust to the fill level and significant overfilling of the template (evidenced by complete disappearing of the contour of the pre-pattern) may be observed before the DSA holes disappear.

4 This result is in accordance with the more straight cylinders that are formed for this flow due to the neutral character of the substrate (cfr Figure 2, middle). Figure 3. Schematic depiction of process windows as a function of template geometry and BCP fill level for Flow #1 (left) and Flow #2 (right). The proposed difference in 3-dimensional character for Flows #1 and #2 is supported by results from pattern transfer studies with these flow (Figures 4 and 5). Here the templated DSA process is executed on a stack of 80nm of SiO 2 and 20nm of SiN x. After BCP and wet development, the BCP holes are first transferred into the nitride hardmask and next into the oxide layer. Process optimization has been done on meniscus opening and nitride etch, but no specific optimization has been attempted for the oxide opening. At optimal fill levels (Figure 4) all holes are well defined for the cases of Flow #1 as well as Flow #2. The CD uniformity for Flow #1 is slightly worse compared to the case of Flow #2, but the results are statistically quite close. The oxide layer has been slightly underetched (as can be seen from the x-sectional images), but overall pattern definition looks acceptable in this stage of the development. The situation changes when a neighboring pattern with slightly lower pattern density is inspected (Figure 5). The higher BCP fill level in this case results in many closed holes for Flow #1, whereas the holes for Flow #2 are still well defined. Figure 4. Pattern transfer results for Flow #1 and #2 at optimal pattern density for the BCP film thickness and annealing conditions.

5 Figure 5. Pattern transfer results from the same wafers as from Figure 4, but now at slightly lower pattern density. Finally, the impact of PS versus PMMA wetting sidewalls has been evaluated by comparing Flows #2 and #3 (Figure 6). The primary difference between these flows is in the nature of the brush. Flow #2 uses a quite neutral brush that preferentially grafts to the SiO 2-like substrate that results from the final etch step in the template fabrication process. Flow #3 on the other hand uses a PS-wetting brush that kinetically favors grafting to the SOC sidewall. Under the employed process conditions a relatively low grafting density to the substrate occurs that makes it close to neutral while a higher grafting density on the sidewalls makes them PS-wetting. As a consequence the commensurability of the pre-pattern changes. For Flow #1 proper holes for the single hole shrink case are formed at a template CD that closely matches 2 * BCP pitch. In this case Flow #3 gives uncontrolled DSA hole formation. When the CD is decreased close to 1*L 0 the holes in Flow #2 are closed (note that overfilling makes the templates poorly visible). In the case of Flow #3 the templates are now also overfilled, but the DSA holes are open and clearly present in the expected locations. Optimization of the BCP film thickness will likely further improve the pattern definition for this flow. Finally, we point out that the added confinement that is provided by the smaller guide template in the PS-wetting scheme will likely have a positive impact on the placement accuracy. Detailed analysis of this is ongoing. Figure 6. DSA results for Flow #2 (middle row) and #3 (bottom row) for 2 different CDs of the pre-pattern template (top).

6 3.2 DSA pre-pattern design for the V1 layer Next, we consider application of the templated DSA process for hole patterning for the application to the V1 layer of a representative N7 layout. Starting from the capabilities of the templated DSA process in our hands it was decided to restrict the pattern types to singlets, doublets and linear triplets. In our experience, the pre-pattern templates that allow formation of a BCP arrangement that is a subset of the naturally preferred hexagonal array is most robust for DSA processing. This can for examples be observed from Figure 7 where the linear templates all are capable of definition of well-defined hole patterns, but the rectangular L-shaped pre-pattern is not. Furthermore, we will restrict the maximum number of holes per template to 3, since the placement error is expected to rapidly increase for more aggressive frequency multiplication. In addition, simulations indicate that the straightness of the PMMA cylinders is insufficient for more than 3 DSA holes within a linear template [12]. These considerations restrict the available templates to singlets, doublets, linear triplets and perfect triangles. The latter however do not occur in our design and are therefore not considered. Figure 7. Pattern definition for templated DSA for a variety of pre-pattern shapes. A representative N7 design clip, stripped to only show M1, V1 and M2 is depicted in Figure 8 (left). The default design rules in the imec N7 vehicle employ an M1 pitch of 42nm and an M2 pitch of 32nm. This specific design requires lithoetch^5 in order to pattern it with traditional ArF multiple patterning. When we consider V1 patterning with DSA, we have to decide how to arrange the pre-patterns to enable the target via layout. In order to do this we impose three additional design rules. First, when the pitch between 2 neighboring vias is >95nm it is assumed that they can be optically resolved and will thus use separate templates from the same photo. Second, the spacing between the edges of neighboring templates needs to be >45nm. Third, the center-to-center distance between neighboring holes within a template needs to be <50 nm in order to resolve them with the DSA process. We have observed that the quality of DSA patterns at larger dimensions rapidly deteriorates. Especially the latter design rule limits the applicability of DSA to this specific clip, since holes that are place on the diagonal of the grid are at a distance of 52nm and therefore need separate templates that need to be exposed in separate exposures. In addition, the large pre-pattern dimensions for the process with PMMA-wetting sidewalls results in violations of the spacing requirement even in case of a three color decomposition. In this specific example a 4-color decomposition is required for the case of PMMA-wetting sidewalls (middle) and a 3-color decomposition for the case of the PS-wetting sidewalls (right). Figure 8. Representative N7 design clip stripped to only show M1, V1 and M2 layers (left). The V1 layer requires quadruple DSA in case of the PMMA-wetting sidewall process and triple DSA in case of the PS-wetting sidewall process.

7 Next, it has been attempted to make the design from Figure 8 more DSA-friendly by varying the M1 and M2 pitches. Figure 9 shows the foundry N7 curve, where the blue line represents different operating points with identical area requirements. We will consider the case where the M1 pitch is relaxed from 42nm to 56nm, while the M2 pitch is tightened from 32nm to 24nm. Figure 9. N7 design curve displays various options for M1 and M2 pitch. Tightening the M2 pitch, while relaxing the M1 pitch opens interesting perspectives for DSA (Figure 10). At the M1 pitch of 56nm, each 2nd column can be comfortably resolved. As a consequence, the coloring exercise can be simply done based on the column number, where odd columns get one color and even column numbers the other. Next, the tighter M2 pitch allows to make much better use of the resolution capabilities of the DSA process. The tightest pitch of 24nm will not occur in the design, but 2* the M2 pitch will occur. The only design conflicts now occur for vias that are positioned at 3* the M2 pitch of a neighboring via on the same column. These will need to be repositioned, but it is expected that this may be feasible with minimal area penalty. Figure 10. The altered N7 design allows for much simpler DSA decomposition and paves the road for a 2-color option. It should be noted that the exercise above only considers patterning of the V1 layer. In practice, the implication of such design alterations on all layers above and below should naturally be considered. The above example mainly serves to illustrate that the selection of pitches is important in making the design DSA friendly. Regarding the cost comparison between a standard LE^N process and a DSA process, it should be noted that not only the number of mask layers should be considered. Since a single DSA cycle consist in fact of the sequence litho-etch-dsa-etch, this sequence should be repeated at least twice in the example above. The cost benefit of one fewer mask layer is therefore diminished by the

8 additional cost of the DSA process itself and the extra etch step. A cost study is ongoing at imec to get better insight into this. 3.3 DSA-compatible interconnect VIAs Vx layers Next we focused on the development of a DSA-friendly template for the interconnect VIA layers in N7. Based on our templated-via flow results, we limit the DSA-compatible VIA patterns to only singlets, doublets or triplets (Figure 7). In order to make these VIA patterns compatible with circuits and use the minimum number of multi-dsa steps, we examine the following options: A) Use of a Predefined Checkerboard Grid (PCG) for the VIA layer patterning. The PCG enforces the VIA placement in specific, predetermined available grid positions, while blocking the rest. The arrangement of these available positions form a checkerboard pattern in the grid. An example of the VIA PCG rule is shown in Figure 11. Figure 11. Predefined Checkerboard Grid (PCG) Using the PCG rule, the number of possible VIA patterns and VIA pitches is reduced, which simplifies a lot the DSAcompatible pattern matching and coloring (color = different lithography step). B) Use of different BCP material for each patterning step. The combination of different BCP materials increases the pitch range of doublets and triplets, which adds more flexibility to DSA-compatible pattern matching, as illustrated in Figure 12. This applies only in the case of multiple LE-DSA steps, which is the case we currently focus on. Particularly, we are focusing on designs which are compatible with (LE-DSA)^2 and (LE-DSA)^3 (or just DSA2, DSA3). Figure 12. Combination of BCP materials in multi-dsa C) Group VIAs in clusters and define DSA solutions for each cluster. Grouping of VIAs is essential in order to reduce the complexity of the VIA patterns after place and route of the design. In our approach we use a fixed rectangular region of VIA grid points (4x4, 5x5, 6x6, etc...) as the basic grid block, then we set a number of Basic/Primary VIA Cluster Patterns (PCPs) for this block and we create a library with DSA solutions for each PCP.

9 The choice of the size of the basic block depends on technology parameters, like the VIA half pitch distance on the grid, the minimum metal area allowed and the lithography resolution. For example, if we assume a 26nm grid and 193i lithography with >90nm center-to-center VIA printability, we can define this block as 4x4 because: a) after five or more grid points in the horizontal or vertical axes there is no color conflict, b) if we assume a minimum wire length of >52nm (due to the minimum metal area rule) and a fully occupied block (with VIAs), then the placement of another VIA on the first available horizontal or vertical position outside this block is forbidden. If another VIA is needed near this block, it should be placed on the second available position (in the horizontal and vertical axes), which is two grid points further (due to the PCG option). Theoretically, this block represents the highest density block that can exist in our VIA layer. Figure 13. Theoretical highest density block in a 26nm grid and DSA3 solution This block would need at least seven (!) Litho-Etch steps for 26nm grid and 193i (only the upper-left, bottom-right VIAs could use the same color), while DSA could reduce it to only three LE-DSA steps. The PCPs are defined as the Cluster Patterns (CPs) from which all the rest of the CPs can be derived or are compatible. For example, the 4-VIA PCPs are defined as the CPs that give all the combinations of 4-VIA patterns in a 4x4 grid area, when rotated, mirrored and/or shifted. Figure 14 shows PCP examples for the 26nm grid. Figure 14. PCP examples in 26nm grid and the cases where DSA3 is not sufficient Note that if we target for DSA3 in the above example and use two BCP materials, BCP1 for the diagonal doublets/triplets and BCP2 for the horizontal/vertical, most of the PCPs can be easily resolved. There are only two PCPs that are incompatible with configuration A and three with configuration B. In this regard, configuration A seems more convenient.

10 According to our previous assumptions, when there is a high density cluster (5, 6, 7 or 8VIA) it is more likely that it will be isolated (from a coloring conflict point of view). The low density clusters (4VIA or lower), on the other hand, can easily be resolved with DSA2 (with only few exceptions), allowing the extra color to be used for cluster abutting. 4. CONCLUSIONS Templated DSA for via patterning has been shown to be a promising technique for introduction at the N7 node. Typically DSA allows to use 1 fewer mask for patterning a typical via layer. This comes of the expense of some extra DSA-specific processing. Specifically use of PS-wetting sidewall scheme (or more generally for other BCP systems than PS-b-PMMA: a majority block wetting sidewall scheme) is crucial for allowing sufficiently small pre-pattern templates. Detailed cost of ownership studies are ongoing to estimate whether the cost benefit is sufficient. However, when the design can be made DSA friendly it will in most cases be possible to avoid another mask. Furthermore, the cost benefit of DSA will rapidly increase with shrinking dimensions. For Vx patterning with metal pitches below 32nm the difference between LE^N and templated DSA quickly goes up to 4 mask sets! Remaining challenges for introduction of DSA into manufacturing still exist. Specifically placement accuracy, defectivity and development of robust pattern transfer processes require attention. However, no major roadblocks are expected. REFERENCES [1] C.-C. Liu, C. J. Thode, P. A. Rincon Delgadillo, G. S. W. Craig, P. F. Nealey, R. Gronheid J. Vac. Sci. Technol. B 29 (2011) 06F203. [2] P. A. Rincon Delgadillo, R. Gronheid, C. J. Thode, H. P. Wu, Y. Cao, M. Neisser, M. Somervell, K. Nafus, P. F. Nealey J. Micro/Nanolith. MEMS MOEMS 11 (2012) [3] P. Rincon Delgadillo, M. Suri, S. Durant, A. Cross, V. R. Nagaswami, D. Van Den Heuvel, R. Gronheid, P. Nealey J. Micro/Nanolith. MEMS MOEMS 12 (2013) [4] D. B. Millward, G. S. Lugani, R. Khurana, S. L. Light, A. Niroomand, P. D. Hustad, P. Trefonas, S.-W. Chang, C. N. Lee, D. Quach Proc SPIE 9054 (2014), 90540M. [5] R. Gronheid, I. Pollentier, T. Younkin, M. Somervell, K. Nafus, J. Hooge, B. Rathsack, S. Scheer, P. Rincon Delgadillo, P. Nealey Addressing the Challenges of Directed Self Assembly Implementation 2011 International Symposium on Lithography Extensions Oct , 2011, Miami, Florida. [6] G. S. Doerk, J. Y. Cheng, C. T. Rettner, S. Balakrishnan, N. Arellano, D. P. Sanders Proc SPIE 8680 (2013), 86800Y. [7] R. Gronheid, A. Singh, T. R. Younkin, P. Rincon Delgadillo, P. Nealey, B. T. Chan, K. Nafus, A. Romo Negreira, M. Somervell Proc SPIE 8682 (2013), 86820A. [8] A. Singh, B. T. Chan, Y. Cao, G. Lin, R. Gronheid Proc SPIE 9049 (2014), 90492F. [9] R. Gronheid, J. Bekaert, V.-K. Murugesan Kuppuswamy, N. Vandenbroeck, J. Doise, Y. Cao, G. Lin, S. Sayan, D. Parnell, M. Somervell Proc SPIE 9051 (2014), 90510I. [10] X. Chevalier, C. Nicolet, R. Tiron, A. Gharbi, G. Chamiot-Maitral, K. Jullian, P. Pimenta-Barros, M. Argoud, J.-L. Peyre, R. Van Spaandonk, G. Fleury, G. Hadziioannou, C. Navarro Proc SPIE 9049 (2014), 90490Y. [11] N. Laachi, T. Iwama, K. T. Delaney, B. Kim, R. Bristol, D. Shykind, C. J. Weinheimer, G. H. Fredrickson Proc SPIE 9049 (2014), 90491M. [12] G. Fenger, A. Burbine, J.A. Torres, Y. Ma, Y. Granik, P. Krasnova, G. Vandenberghe, R. Gronheid, J. Bekaert Proc SPIE 9235 (2014), 92351X. [13] J. Doise et al to be published.