The Evolving Semiconductor Technology Landscape and What it Means for Lithography. Scotten W. Jones President IC Knowledge LLC

Transcription

1 The Evolving Semiconductor Technology Landscape and What it Means for Lithography Scotten W. Jones President IC Knowledge LLC

2 Outline NAND DRAM Logic Conclusion 2

3 NAND Linewidth Trend 2D to 3D For approximately 15 years 2D NAND had the tightest lithographic pitches and fastest scaling path (contacted poly pitch shown). Due to device issues 2D scaling became too difficult to continue. 3D has now replaced 2D and scales by layers instead of lithographic dimensions. The most difficult 3D feature to produce is the channel hole due to high aspect ratio and it is ~100nm and growing with generation. NAND Critical Dimension Trend 3

4 3D NAND Fabrication 1. CMOS fabrication some of the CMOS may be under the array requires interconnect under the array. 2. Memory array formation single string or string stacking. String stacking repeats layer deposition and channel hole etch with single channel hole fill. 3. Interconnect Memory array masks Channel 1 stair step mask for each 8 to 10 layers (may be going to 3) 1 or 2 slot masks Via mask Clear out masks Layers and strings Memory array string formation (Samsung/Toshiba) 4

5 3D NAND Mask Counts As 3D NAND scales mask counts will grow due to: Increased adoption of CMOS under the array? More masks for stair step until 3 mask solution is used. String stacking to control stress and aspect ratio. Mask counts on the right are shown for Intel-Micron and Samsung as the two major approaches. NAND Mask Counts Versus 3D Layers and Companies [1] [1] IC Knowledge Strategic Cost Model 2017 revision 05 5

6 NAND Bit Density Trend The transition from 2D NAND to 3D is enabling the continuation in bit density scaling by using the third dimension. Bit density is the number of gigabits of memory on the die divided by the die size. Multiple points for the same company in the same year represent multi-level cell (2 bits/cell) and tri-level cell (3 bits/cell). NAND Bit Density 6

7 DRAM Minimum Pitch Trend The plot on the right shows the minimum pitch trends for DRAM. The smallest pitch is shown for each company, word line for Micron and active for Samsung and SK Hynix. DRAM nodes are now defined the smallest half-pitch. SADP = self aligned double patterning, SAQP = self aligned quadruple patterning. DRAM Minimum Pitches 7

8 DRAM Scaling Issues DRAM capacitors are fabricated at the limits of mechanical stability (see figure on the right). A titanium nitride storage node is formed that the dielectric layer and top plate are deposited over. Higher K value dielectrics have lower band gaps and therefore higher leakage. DRAM scaling has become an optimization battle between achieving a minimum capacitance value, minimizing leakage and optimizing the peripheral circuitry. CC = kkεεεε tt dd kk = dddddddddddddddddddd cccccccccccccccc εε = pppppppppppppppppppppp A = area tt dd =dielectric thickness Capacitance Formula Band Gap Versus K Titanium Nitride Storage Node 8

9 DRAM Mask Counts DRAM Mask Count Trend. The mask counts are based on our analysis of Samsung DRAM parts through the 18nm node (1x) and our projection for the 15nm node (1y). DRAM Mask Counts [1] [1] IC Knowledge Strategic Cost Model 2017 revision 05 9

10 DRAM Bit Density Bit density is die capacity in Gb divided by die size in mm 2. Looking at the individual companies it can been seen that bit density growth is flattening out. DRAM Bit Density 10

11 Logic Pitch Trends 11

12 Contacted Poly Pitch CPP Scaling Challenges Assuming a 5nm fin silicon thickness limit (due to mobility collapse), the gate length limit for a Trigate FinFET is ~16nm and for horizontal nanowire (HNW) ~13nm [1]. Shrinking contacts increase contact resistance. Thinner spacer increases capacitance. TSMC Actual/Forecast L G = gate length t SP = spacer thickness W C = contact width Node Device CPP L G t SP W C 16 FF FF FF FF HNW ? 10 CCCCCC = LL GG + 2tt SSSS + WW CC Actual Dimensions [2] Node CPP L G t SP W C [1] J.P. Colinge, p 313, SISPAD (2014), [2] K.-I. Seo, et. al. VLSIT (2015),R. Xie, et.al IEDM (2016) 12

13 Gate All Around (GAA) At 3nm recent imec work suggests that FinFETs are viable but every scaling booster option is required and nanosheets offer more margin. Nanowires provide the best electrostatics, FinFETs provide the best drive current, nanosheet width can tune the trade-off. Effective channel width (Weff). Weff Planar (1 side gate) Weff = W FinFET Weff (3 side gate) = 2Fh + Fw Nanosheet (4 side gate) Weff = 2NSth + 2NSw Nanowire, FinFET and nanosheet relative performance 13

14 Logic 2D to 3D Scaling CFETs stack nfets and pfets to provide scaling without requiring a lithographic shrink. CFETs with many layers can even relax lithographic scaling. 2 deck CFET 14nm 10nm 7nm 5nm 3.5nm 2.5nm 1.75 nm 1.25 nm Approach Device FF FF FF FF HNS CFET CFET CFET Fin pitch (nm) Contacted poly pitch (nm) Minimum metal pitch (nm) Tracks Decks Scaling factor NA

15 Logic Mask Count Trend Mask count shown for a foundry following the roadmap outlined on the previous slide. The 7nm projection is for first generation 7nm processes that are optical only. EUV enters use for second and third generation 7c (EUV for contacts and 1x vias) and 7+(EUV for contacts, 1x vias and 1x metal) processes. For 3.5nm and 2.5nm EUV is used for some single exposures and some cuts/blocks with optical SAQP. The mask projections stop after 3.2 because 3.3 and 14.7 process flows have not been entered into our models yet. Logic Mask Counts [1] [1] IC Knowledge Strategic Cost Model 2017 revision 05 15

16 Conclusion NAND is transitioning from 2D lithography driven processing to 3D etch and deposition driven processing. Pitches are relaxed from 2D values and unlikely to get tighter in the future. Mask counts will grow due to string stacking. DRAM scaling is capacitor limited and facing fundamental physical limits. It isn t currently clear whether there is a path forward after the next few nodes. The most promising next generation replacement for DRAM is some form of MRAM, but MRAM faces its own scaling issues. Logic is continuing to scale lithographically but fundamental limits on 2D shrinks are looming. CFETs offer a possible 3D scaling path that could result in relaxed lithographic dimensions analogous to what has happened with 3D NAND. 16