PS Midterm 2. Pipelining

Transcription

1 PS idterm 2 Pipelining

2 Seqential Landry 6 P idnight Time T a s k O r d e r A B C D Seqential landry takes 6 hors for 4 loads If they learned pipelining, how long wold landry take?

3 Pipelined Landry: Start work ASAP 6 P idnight Time T a s k O r d e r A B C D Pipelined landry takes 3.5 hors for 4 loads

4 Total Time for Eight Instrctions class fetch Register read operation access Register write Total time Load word 2 ns ns 2 ns 2 ns ns 8 ns Store word 2 ns ns 2 ns 2 ns 7 ns R-type 2 ns ns 2 ns ns 6 ns Branch 2 ns ns 2 ns 5 ns R-type instrctions: add, sb, and, or, slt

5 The Five Stages of the Load Instrction Cycle Cycle 2 Cycle 3 Cycle 4 Cycle 5 Load Ifetch Reg/Dec Eec em Wr Ifetch: Instrction Fetch Fetch the instrction from the Instrction emory Reg/Dec: Registers Fetch and Instrction Decode Eec: Calclate the memory address em: Read the data from the emory Wr: Write the data back to the register file

6 Single Cycle, ltiple Cycle, vs. Pipeline Clk Cycle Cycle 2 Single Cycle plementation: Load Store Waste Cycle Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle Clk ltiple Cycle plementation: Load Ifetch Reg Eec em Wr Store Ifetch Reg Eec em R-type Ifetch Pipeline plementation: Load Ifetch Reg Eec em Wr Store Ifetch Reg Eec em Wr R-type Ifetch Reg Eec em Wr

7 Why Pipeline? Sppose instrctions are eected The single cycle machine has a cycle time of 45 ns The mlticycle and pipeline machines have cycle times of ns The mlticycle machine has a CPI of 3.6 Single Cycle achine 45 ns/cycle CPI inst = 45 ns lticycle achine ns/cycle 3.6 CPI inst = 36 ns Ideal pipelined machine ns/cycle ( CPI inst + 4 cycle drain) = 4 ns Ideal pipelined vs. single cycle speedp 45 ns / 4 ns = 4.33 What has not yet been considered?

8 Single Cycle path IF: Instrction Fetch ID: Instrction decode / Register file read EX: Eecte / address calclation IF: emory access WB: Write back PC 4 ress Instrction emory Registers ra rb rw bsw bsa bsb Sign etent Shift left 2 Eqal r. ot emory in

9 Pipelined Version of the path IF/ ID ID/ EX EX / E E / WB 4 PC ress Instrction emory ra rb rw Registers bsw [5-] [2-6] [5-] bsa bsb Sign etent Shift left 2 Eqal r. ot emory in

10 An Eample to Clarify Pipelining Since many instrctions are simltaneosly are eecting in a single cycle datapath, it can be difficlt to nderstand. The following code will be eamined: lw $, 2($) sb $, $2, $3 Time (clock cycles) I n s t r. O r d e r lw $,2($) sb $,$2,$3 CC CC 2 CC 3 CC 4 CC 5 CC 6 CC 7 em Reg em Reg em Reg em Reg

11 Clock lw $, 2($) Instrction fetch IF/ ID ID/ EX EX / E E / WB 4 PC ress Instrction emory ra rb rw Registers bsw [5-] [2-6] [5-] bsa bsb Sign etent Shift left 2 Eqal r. ot emory in

12 Clock 2 sb $, $2, $3 Instrction fetch lw $, 2($) Instrction decode IF/ ID ID/ EX EX / E E / WB 4 PC ress Instrction emory ra rb rw Registers bsw [5-] [2-6] [5-] bsa bsb Sign etent Shift left 2 Eqal r. ot emory in

13 Clock 3 sb $, $2, $3 Instrction decode lw $, 2($) Eection IF/ ID ID/ EX EX / E E / WB 4 PC ress Instrction emory ra rb rw Registers bsw [5-] [2-6] [5-] bsa bsb Sign etent Shift left 2 Eqal r. ot emory in

14 Clock 4 sb $, $2, $3 Eection lw $, 2($) emory IF/ ID ID/ EX EX / E E / WB 4 PC ress Instrction emory ra rb rw Registers bsw [5-] [2-6] [5-] bsa bsb Sign etent Shift left 2 Eqal r. ot emory in

15 Clock 5 sb $, $2, $3 emory lw $, 2($) Write Back IF/ ID ID/ EX EX / E E / WB 4 PC ress Instrction emory ra rb rw Registers bsw [5-] [2-6] [5-] bsa bsb Sign etent Shift left 2 Eqal r. ot emory in

16 Pipelined path with Control Signals PCSrc IF/ ID ID/ EX EX / E E / WB PC 4 ress Instrction emory RegWr ra rb rw Registers bsw [5-] [2-6] [5-] bsa bsb Sign etent Shift left 2 Src 6 Control RegDst Eqal op Branch r. ot emory in emrd emwr emtoreg

17 An Eample to Clarify Pipelined Control Let s look at what s happing in the pipeline for the following program. lw $, 2($) sb $, $2, $3 and $2, $4, $5 or $3, $6, $7 add $4, $8, $9 Code does not have any data, control, or strctral hazard.

18 IF: lw $,2($) IF/ ID ID/ EX EX / E E / WB Control WB WB EX WB PC 4 ress Instrction emory Clock RegWr ra rb rw Registers bsw [5-] [2-6] [5-] bsa bsb Sign etent Shift left 2 Src Eqal Control op RegDst Branch r. ot emory in emrd emwr emtoreg

19 IF: sb $,$2,$3 ID: lw $,2($) IF/ ID ID/ EX EX / E E / WB lw WB Control EX WB WB PC 4 ress Instrction emory Clock 2 X 2 X RegWr ra rb rw Registers bsw [5-] [2-6] [5-] $ bsa $X bsb Sign etent 2 X Shift left 2 Src Eqal Control op RegDst Branch r. ot emory in emrd emwr emtoreg

20 IF: and $2,$4,$5 ID: sb $,$2,$3 EX: lw $,2($) IF/ ID ID/ EX EX / E E / WB sb WB Control EX WB WB PC 4 ress Instrction emory Clock X X RegWr ra rb rw Registers bsw [5-] [2-6] [5-] $2 bsa $3 bsb Sign etent X X $ 2 Shift left 2 Src Eqal Control op RegDst Branch r. ot emory in emrd emwr emtoreg

21 IF: or $3,$6,$7 ID: and $2,$4,$5 EX: sb $,$2,$3 E: lw $,2($) IF/ ID ID/ EX EX / E E / WB and WB Control EX WB WB PC 4 ress Instrction emory Clock X X 2 RegWr ra rb rw Registers bsw [5-] [2-6] [5-] $4 bsa $5 bsb Sign etent X X 2 $2 $3 Shift left 2 Src Eqal Control op RegDst Branch r. ot emory in emrd emwr emtoreg

22 IF: add $4,$8,$9 ID: or $3,$6,$7 EX: and $2,$4,$5 E: sb $,$2,$3 WB: lw $ IF/ ID ID/ EX EX / E E / WB or WB Control EX WB WB PC 4 ress Instrction emory Clock X X 3 RegWr ra rb rw Registers bsw [5-] [2-6] [5-] $6 bsa $7 bsb Sign etent X X 3 $4 $5 2 Shift left 2 Src Eqal Control op RegDst Branch r. ot emory in emrd emwr emtoreg

23 Single emory is a Strctral Hazard Time (clock cycles) I n s t r. O r d e r Load Instr Instr 2 Instr 3 Instr 4 em Reg em Reg em Reg em Reg em em Reg em Reg Reg em Reg em Reg em Reg Detection is easy in this case! (right half highlight means read, left half write)

24 Soltion 3: Stall Time (clock cycles) I n s t r. O r d e r Load Instr Instr 2 nop Instr 3 Instr 4 em Reg em Reg em Reg em Reg em Reg em Reg bbble bbble bbble bbble em bbble bbble bbble bbble bbble bbble Reg em Reg em Reg em Reg

25 Control Hazard Soltions Predict: gess one direction then back p if wrong Predict not taken I n s t r. O r d e r Beq Load Time (clock cycles) em Reg em Reg em Reg em Reg em Reg em Reg pact: clock cycle per branch instrction if right, 2 if wrong (right - 5% of time) ore dynamic scheme: history of branch (- 9%)

26 Hazard on r Problem: r cannot be read by other instrctions before it is written by the add. add r, r2, r3 sb r4, r, r3 and r6, r, r7 or r8, r, r9 or r, r, r

27 Hazard on r: Dependencies backwards in time are hazards I n s t r. O r d e r Time (clock cycles) IF ID/RF EX E WB add r,r2,r3 sb r4,r,r3 and r6,r,r7 or r8,r,r9 or r,r,r

28 Hazard Soltion: Forward reslt from one stage to another I n s t r. O r d e r Time (clock cycles) IF ID/RF EX E WB add r,r2,r3 sb r4,r,r3 and r6,r,r7 or r8,r,r9 or r,r,r or instrction is OK if define read/write properly

29 Forwarding (or Bypassing): What abot Loads Dependencies backwards in time are hazards Time (clock cycles) IF ID/RF EX E WB lw r,(r2) sb r4,r,r3 Can t solve with forwarding: st delay/stall instrction dependent on loads

30 Hazards Previos eample shows s how independent instrctions that do not se the reslts calclated by prior instrctions are eected. This is not the case with real programs. Let s look at the following code seqence. sb $2, $, $3 and $2, $2, $5 or $3, $6, $2 add $4, $2, $2 sw $5, ($2) The last for instrctions are all dependent on the register $2 of the first instrction. Assme that register $2 had the vale of before the sbtract instrction and -2 afterwards.

31 Hazards (Cont ) CC CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 The vale of $2: / sb $2, $, $3 and $2, $2, $5 or $3, $6, $2 add $4, $2, $2 sw $5, ($2)

32 Hazard Detection & Forwarding It is possible to detect data hazard and then forward the proper vale to resolve the hazard. When an instrction tries to read a register in its EX stage that an earlier instrction intends to write in its WB stage. This is the case between sb-and instrction below: sb $2, $, $3 and $2, $2, $5 This hazard can be detected by simply checking: EX/E.RegisterRd = ID/EX.RegisterRs = $2

33 Hazard Detection & Forwarding (Cont ) Another hazard is between sb-or instrctions: sb $2, $, $3 and $2, $2, $5 or $3, $6, $2 This hazard can be detected by simply checking: E/WB.RegisterRd = ID/EX.RegisterRt = $2 There is no data hazard between sb-add and sb-sw instrctions.

34 Smmary of Hazard Conditions a. EX/E.RegisterRd = ID/EX.RegisterRs b. EX/E.RegisterRd = ID/EX.RegisterRt 2a. E/WB.RegisterRd = ID/EX.RegisterRs 2b. E/WB.RegisterRd = ID/EX.RegisterRt This actally refers to destination field of an instrction. It is rd field in R-type instrctions and rt field in I-type instrctions. in the EX stage chooses the correct one, therefore, EX/E and E/WB pipeline registers store this information as a rd field (EX/E.RegisterRd and E/WB.RegisterRd). Since some of the instrctions (i.e. sw, beq) do not write to register file, the above policy is inaccrate. Consider the following code seqence: sw $, ($5) add $3, $, $2 EX/E.RegisterRd = ID/EX.RegisterRs $ = +$5 This problem can be solved simply by checking RegWr signal.

35 Smmary of Hazard Conditions (Cont ) Another problem: What happens if $ is sed as a destination register? A non-zero vale wold not be forwarded. Therefore, hazard detection shold be the following: EX hazard: if (EX/E.RegWr and (EX/E.RegisterRd = ) and (EX/E.RegisterRd = ID/EX.RegisterRs)) ForwardA= if (EX/E.RegWr and (EX/E.RegisterRd = ) and (EX/E.RegisterRd = ID/EX.RegisterRt)) ForwardB= E hazard: if (E/WB.RegWr and (E/WB.RegisterRd = ) and (E/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA= if (E/WB.RegWr and (E/WB.RegisterRd = ) and (E/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB=

36 Smmary of Hazard Conditions (Cont ) Consider the following seqence: add $, $, $2 add $, $, $3 add $, $, $4... In this case, the reslt is forwarded from E stage becase the reslt in the E stage is the more recent reslt than the reslt in WB stage. Ths, the control for the E hazard: E hazard: if (E/WB.RegWr and (E/WB.RegisterRd = ) and (EX/E.RegisterRd = ID/EX.RegisterRs) and (E/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA= if (E/WB.RegWr and (E/WB.RegisterRd = ) and (EX/E.RegisterRd = ID/EX.RegisterRt) and (E/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB=

37 Smmary of Hazard Conditions (Cont )

38 The Pipelined path with Forwarding ID/ EX WB EX / E Control WB E / WB IF/ ID EX WB PC emory Registers IF/ID.RegisterRs Rs emory IF/ID.RegisterRt Rt IF/ID.RegisterRt IF/ID.RegisterRd Rt Rd EX/E.RegisterRd Forwarding nit E/WB.RegisterRd

39 Signed mediate Enhancement

40 Hazards and Stalls Program eection order (in instrctions) Time (in clock cycles) CC CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 lw $2, 2($) Forwarding does not solve the problem. We need a hazard detection nit. and $4, $2, $5 and instrction needs to be stalled one cycle. or $8, $2, $6 add $9, $4, $2 slt $, $6, $7

41 Hazard Detection The control for the hazard detection nit is: if (ID/EX.emRd and ((ID/EX.RegisterRt = IF/ID.RegisterRs) or (ID/EX.RegisterRt = IF/ID.RegisterRt))) stall the pipeline Checks if the instrction is a load

42 Hazards and Stalls (Cont ) Program eection order (in instrctions) Time (in clock cycles) CC CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 CC lw $2, 2($) and $4, $2, $5 Reg Reg Dm Reg or $8, $2, $6 add $9, $4, $2 Bbble slt $, $6, $7 and and or instrctions repeat in CC4 what they did in CC3

43 The Pipelined path with Forwarding and Hazard Detection Unit IF/IDWrite Hazard detection nit ID/EX.emRead ID/ EX WB EX / E WB E / WB PCWrite IF/ ID Control EX WB PC emory Registers IF/ID.RegisterRs Rs emory IF/ID.RegisterRt Rt IF/ID.RegisterRt IF/ID.RegisterRd Rt Rd EX/E.RegisterRd IF/ID.RegisterRt Forwarding nit E/WB.RegisterRd

44 Branch Hazards Program eection order (in instrctions) r. 4 beq $, $3, 7 Time (in clock cycles) CC CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 44 and $2, $2, $5 48 or $3, $6, $2 52 add $4, $2, $2 72 lw $4, (5)$7 Actally, the nmber of instrctions needs to be flshed can be redced from 3 to instrction (shown in the following slide) when the direction of branch is mispredicted.

45 path for Branch (inclding HW to flsh the pipeline) 4 + IF/ ID Hazard detection nit Sign_e & shift left 2 Control + ID/ EX WB EX EX / E WB E / WB WB PC emory Registers = IF/ID.RegisterRs Rs emory IF/ID.RegisterRt Rt IF.Flsh IF/ID.RegisterRt IF/ID.RegisterRd Rt Rd EX/E.RegisterRd IF/ID.RegisterRt Forwarding nit E/WB.RegisterRd

46 Qestion

47 Qestion 2

48 Answer 2

49 Qestion 3

50 Answer 3