Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs

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1 Design, Automtion nd Test in Europe, DATE 98, Pris, Frnce, Ferury 23-26, 998 Self-Adjusting Output Dt Compression: An Efficient BIST Technique for s V. N. Yrmolik Computer Systems Deprtment Belrussin Stte University of Informtics nd Rdioelectronics, Minsk, Belrus S. Hellernd, H.-J. Wunderlich Division of Computer Architecture University of Stuttgrt Germny Astrct After write opertions, BIST schemes for s relying on signture nlysis must compress the entire memory contents to updte the reference signture. This pper introduces new scheme for output dt compression which voids this overhed while retining the enefits of signture nlysis. The proposed technique is sed on new memory chrcteristic derived s the modulo-2 sum of ll ddresses pointing to non-zero cells. This chrcteristic cn e djusted concurrently with write opertions y simple EXOR-opertions on the initil chrcteristic nd on the ddresses ffected y the chnge. Introduction High density memories constitute n integrl prt of most present dy micro-electronic systems. To gurntee relile storge of dt, prticulrly in systems for sfety criticl pplictions, efficient test procedures re indispensle. Besides production testing, periodic mintennce testing is especilly importnt for memories to del with the prolem of dt retention, e. g. checking for dt losses fter power-off conditions or during run-time. Moreover, frequent opertions on the memory contents require on-line or periodic consistency checks. When memories re emedded in lrger integrted circuits, such s microprocessors or digitl communiction devices, conventionl techniques for externl memory testing cn no longer e pplied due to the limited ccessiility of the memories. To solve this prolem, nd lso to reduce the long testing times inherent to conventionl externl testing, numer of theoreticl nd prcticl uilt-in selftest (BIST solutions hve een proposed in the pst [-5, 7, -3, 6, 8]. This work ws supported y BMBF-Grnt WEI-X23.2. This pper ddresses the prolem of periodic consistency checking for emedded memories. The proposed strtegy is sed on the BIST rchitecture sketched in Figure. The test pttern genertor produces predetermined sequence of memory ddresses, nd the corresponding sequence of dt is fed into the output dt compressor, the finl stte of which represents chrcteristic of the memory contents. For the initil correct memory contents reference chrcteristic C is lerned this wy on chip nd sved in specific loction [4]. The sme procedure is repeted periodiclly, nd the respective chrcteristics re compred to C to revel inconsistencies. The test pttern genertor cn lso e used to generte the dt to e written into the memory for the production test. In this mode stndrd lgorithms my e pplied which re not considered within the frmework of this pper [6, 8]. Test Pttern Genertor Figure : ddresses Memory dt Block digrm of self-testing memory. Output Dt Compressor Since the descried technique checks the memory offline, there is certin ltency of error detection compred to conventionl on-line checking schemes [5]. But this is more thn outweighed y much smller re overhed nd simpler design. In [4] checking scheme sed on the rchitecture of Figure hs een proposed relying on signture nlysis for output dt compression. It hs een demonstrted y the uthors tht this kind of BIST rchitecture offers some very importnt dvntges, whereof the most vlule re: low re overhed, rther unffected ccess time during norml opertion, nd high fult coverge due to the low proility of lising errors [3, 9]. The min disdvntge, however, is the necessity to

2 2 djust the lerned signture fter write opertions. Updting the lerned signture requires to run through complete cycle of the test pttern genertor nd thus repeting the complete initil lerning phse. In this pper, we propose new scheme for output dt compression which voids this overhed while retining the dvntges of schemes relying on lerned signtures. It is sed on new chrcteriztion of the fult free memory contents nd cn esily e djusted during write opertions, which elimintes the repeted lerning phses of previous pproches nd significntly reduces the test time. It will e shown tht the scheme is prticulrly suitle for Ds, lthough it cn e efficiently implemented for vrious types of memory. The chievle test qulity is the sme s for schemes using conventionl signture nlysis: the proility of lising errors is 2 -k, where k denotes the length of the memory chrcteristic. The sic concepts of the proposed technique re introduced in Section 2 for it-oriented s well s for wordoriented s, complete BIST rchitecture is descried in Section 3. 2 A Self-Adjusting Chrcteristic for s In the following chrcteristic for fult free s is introduced which cn esily e djusted concurrently with write opertions. The updted chrcteristic is otined s comintionl function of the initil chrcteristic nd the ddresses ffected y the chnge. The sic principles of the proposed pproch will e explined in Section 2. for it-oriented s, the generliztion to wordoriented memories is descried in Section Bit-Oriented Memories As illustrted in Figure 2, the proposed reference chrcteristic C of the correct initil memory contents is defined s the modulo-2 sum of ll ddresses pointing to cells contining, nd it will therefore e clled modulo-2 ddress chrcteristic throughout the pper. ddress Figure 2: dt C = Modulo-2 ddress chrcteristic for it-oriented s. As shown in Figure 3, during BIST test pttern genertor (n LFSR with primitive feedck polynomil or counter, e.g. produces ll possile ddresses in n ritrry order. The output dt compressor determines the modulo-2 sum of ll ddresses corresponding to, nd if C = holds, the memory is considered s fult free. Figure 3: TPG test ptterns Output Dt Compressor C ddresses Comprtor pss/fil dt register Memory BIST sed on the modulo-2 ddress chrcteristic. The compressor circuit, which is shown in more detil in Figure 4, simply hs to perform itwise EXOR-opertions on ddresses controlled y the vlue stored in the dt register. Figure 4: ddress lines = = = FF FF FF dt & clock Output dt compressor sed on the modulo-2 ddress chrcteristic. In cse of write opertions, the reference chrcteristic must e djusted to the new chrcteristic C new, which is otined y modulo-2 ddition of ll ddresses with

3 3 chnges from to nd modulo-2 sutrction (which is equivlent to modulo-2 ddition of ll ddresses with chnges from to. More specificlly, ltering the contents of single cell corresponds to the modulo-2 ddition of the cell ddress to the initil chrcteristic C. In prticulr, this implies tht the compressor circuit of Figure 4 is lso cple of djusting the reference chrcteristic during write opertions in system mode ( detiled description of the complete implementtion with BIST will e given in Section 3. To summrize the sic concepts of the proposed pproch more formlly let the memory e represented y n rry M[,, m] with ddress spce A = {,, m}, nd let A := { " A M[] = } denote the set of ll memory ddresses pointing to entries. With " A representing the itwise modulo-2 sum of the inry representtion of ll ddresses in A,, the initil chrcteristic is otined s C = " A, nd the new reference chrcteristic fter write opertion t specific ddress * is given y new ( old new old C C * M * M *. = # [ ] [ ] Besides the simple mechnism of mpping chnges in memory to chnges in the chrcteristic, the proposed scheme hs numer of dditionl dvntgeous properties: All single errors re detectle nd dignosle, since if only single errors re ssumed, the expression C CTEST provides the ddress of the fulty memory cell. 2 All doule errors re detectle, since in this cse C CTEST corresponds to the sum of two ddresses r nd s, nd r $ s implies C C $. TEST 3 As shown elow, output dt compression sed on the modulo-2 ddress chrcteristic is equivlent to seril signture nlysis nd the proility of lising errors is thus estimted y 2 %k, where k denotes the length of the chrcteristic. Property 3 is n immedite consequence of the following oservtion. Oservtion: Let &(X " GF(2[X] e primitive polynomil of degree k, nd let & % k ( X : = X & ' ( X * denote the reciprocl polynomil. An LFSR with feedck polynomil & % (X nd initil stte (,,, genertes the sme stte trnsition sequence (in reverse component order s the LFSR with feedck polynomil &(X counting ckwrd from (,,,. The exmple shown in Figure 5 exploits this oservtion to verify property 3 for 7-it. A conventionl BIST is implemented using 3-it LFSR with primitive feedck polynomil &(X = + X + X 3 s test pttern genertor nd seril signture nlyzer with the reciprocl feedck polynomil & % (X = + X 2 + X 3. With n ll-zero initil stte the signture register does not chnge its contents efore the first cell contining is ddressed. The new contents is (,,, nd s the remining memory cells only contin entries, the signture nlyzer works like n utonomous LFSR with initil stte (,, for the rest of the test procedure. Since & % (X is the reciprocl of &(X, this implies tht the signture nlyzer siclly ehves like the test pttern genertor counting ckwrd from (,, (with reversed component order, thus the finl signture is (,, nd corresponds exctly to the ddress of the memory cell with entry. test ptterns TPG ddresses dt signture Figure 5: Correspondence etween signture nlysis nd modulo-2 ddress chrcteristic. If the contins more thn one non-zero entries, then similrly the signture is otined s modulo-2 sum of ll ddresses (in reversed component order corresponding to memory cells with contents. In generl the correspondence etween the modulo-2 ddress chrcteristic nd signture nlysis is descried y the following theorem which ws proven in [9, 7]. Theorem : Let M e it-oriented memory with m = 2 k - cells, &(X " GF(2[X] primitive polynomil of degree k, nd let A + GF(2 k \ {} contin the memory SA

4 4 ddresses pointing to entries. Furthermore, for = (,, k- " GF(2 k let r := ( k-,, denote the vector with components in reversed order. Then BIST using test pttern genertor with feedck polynomil &(X, seril signture nlyzer with feedck polynomil & % (X, initil sttes (,,, nd (,, for the test pttern genertor nd the signture nlyzer, respectively, nd test length of m is chrcterized y the fult free signture S = " A The theorem remins true, when the numer of memory cells is m < 2 k -, nd the initil stte of the test pttern genertor is selected, such tht the finl stte is (,,,. This implies tht for ny memory BIST sed on the modulo-2 ddress chrcteristic there exists n equivlent BIST configurtion sed on signture nlysis with primitive feedck polynomil, nd consequently the sme test qulity is gurnteed. In contrst to signture nlysis, however, the proposed scheme is cple of updting the reference chrcteristic fter write opertions in one step. This enormous gin in time (s mentioned efore, updting the reference signture in conventionl scheme requires to run through complete cycle of the test pttern genertor, is pid y only little hrdwre overhed. As explined ove, the proposed output dt compressor for n m-it memory cn e implemented using log 2 m EXOR-gtes nd one AND-gte. 2.2 Extension to word-oriented s r., - flip-flops,, log 2 m - The scheme for output dt compression introduced in the previous section cn esily e pplied to wordoriented s. As illustrted in Figure 6, for this purpose the word-oriented is considered s it-oriented memory with ddresses of the form ( w,, where w denotes the word ddress nd the it position within the word. Anlogous to Section 2. the memory cn then e modeled s two-dimensionl rry M[ m, n] with ddress spce A = {,, m} {,, n} nd -spce A := {( w, " A M[ w, ] = }. The reference chrcteristic C for the initil correct memory contents is determined s C, = ( ( w, " A where the modulo-2 sum of ddress pirs is defined y ( w, ( w, = ( w w,. w, word ddress Figure 6: it position Bit-oriented representtion of word-oriented. To clculte the corresponding chrcteristic during BIST n LFSR or counter genertes ll word ddresses in n ritrry order. For ech fixed word w* with ddress w* the modulo-2 sum of ll ddresses ( w*, pointing to entries is computed in one step, i. e. with A (w* denoting { M( w*, = } prtil chrcteristic Cw* w*, " A ( w* = ( is determined y comintionl circuit. This wy, cn e derived s CTEST Cw w,,.. m.. m " A ( w = = ( w w which is just the sum of ll it ddresses contining. To design n output dt compressor ccomplishing this tsk, it is crucil to derive n efficient implementtion for the prtil chrcteristic C w*. As introduced ove Cw* w*, w*,. " A ( w* " A ( w* " A ( w* * = ( = ' ( / It is esily verified tht w* = w*, " A ( w * if the numer of ones in w* is odd, nd " A ( w* w* yields the ll-zero vector, if the numer of ones in w* is even. Consequently, the first component of C w* cn e implemented s F # w* = " A ( w* w*, where F is function which determines the prity of the word w*. Since the it ddresses within the word w* re represented y inry l-it vectors, l log 2 n, =, -

5 " A ( w* is otined y itwise EXOR-opertions,, " A ( w* " A ( w* " A ( w* = ' l ( / K, * i with denoting the i-th component of,,. i. l. As i only it-ddresses with = cn contriute to the i-th sum " A ( w* it is sufficient to implement functions F i which count (modulo 2 the numer of ones t ll the ddresses with this property. The second component of C w* is then derived s = ( F F,, l " A ( w* i, K, Figure 7 shows n exmple for memory consisting of seven 4-it words. word ddress lines = = = = it positions dt register where A diff (w* := { M[ w*, ] old $ M[ w*, ] new }. As one cn esily verify, to ccomplish this tsk it is sufficient to feed the output dt compressor of Figure 7 with the difference-word M[ w* ] old M[ w* ] new. Concerning the hrdwre cost for the word-oriented cse, it cn e shown tht the EXOR-tree for implementing the functions F,, F l requires t most j ( 2 %. j. l EXOR-gtes. Overll, the output dt compressor of Figure 7 cn e implemented using, log 2 m- + l flipflops, log 2 m l. j. l j ( 2, % EXOR-gtes, nd AND-gte. Tle summrizes the hrdwre cost for some exmple configurtions of wordoriented s. # Words (m Wordlength (n # Flip- Flops # EXOR- Gtes # AND- Gtes F F F 2 = = = & = = FF FF FF FF FF clock Tle : Hrdwre overhed for the proposed output dt compressor. The length of chrcteristic is k : log m log n =, - +, - 2 2, nd the proility of lising errors for word-oriented % k 2 2 s is 2 2 %, log m = - %, log n-. Figure 7: Output dt compressor for word-oriented s. To djust the reference chrcteristic C in cse of write opertion t specific word-ddress w*, ll it positions hve to e determined with M[ w*, ] old $ M[ w*, ] new, nd the prtil chrcteristic C w* must e djusted to Cw new * = Cw old * ( w*,, " A ( w* diff 3 The BIST rchitecture In this section, complete BIST rchitecture sed on the proposed scheme for output dt compression is descried for Ds. The digrm in Figure 8 shows the necessry BIST equipment in shded locks. The BIST control unit distinguishes etween three min phses: During n initiliztion phse the reference chrcteristic C hs to e determined y running through complete cycle of the test pttern genertor TPG, which my e implemented s mximum period LFSR or counter. The output dt compressor is reset to the ll-zero vector t the eginning of this phse, nd

6 6 TPG Address Register M U X Decoder row ddress column ddress Memory Cells select c Refreshment Register run_bist init BIST Controller Switch Mtrix Test Register Dt Register I/O 2-input EXOR-Gtes c 2 MUX reset enle Output Dt Compressor enle enle C Comprtor pss/fil Figure 8: D with BIST. t the end of this phse the otined reference chrcteristic in the flip-flops of the output dt compressor is written to the register C. If pproprite test ptterns hve een written into the memory, C lso represents the outcome of strt-up test. 2 During system opertion C hs to e updted fter every write opertion. As explined is Section 2.2 this implies tht for ech write opertion the difference, i.e. the itwise EXOR of the old nd the new memory entry hs to e determined. Therefore, key issue in implementing the proposed BIST pproch is to ensure ckup of the old memory entry t low hrdwre nd performnce penlty. The est method to chieve this gol, of course, depends on the memory orgniztion. Here it is ssumed, tht refreshment lgorithm for the dynmic is used which writes the complete row contining the word trgeted y write request to the refreshment register efore loding the new word from dt register. In this cse the old memory entry cn e trnsferred from the refreshment register to the test register vi the switching mtrix. The updted reference chrcteristic now contined in the flip-flops of the output dt compressor is lso written to the register C. 3 During BIST, the test pttern genertor produces ll possile ddresses, nd the test chrcteristic is determined in the sme wy s the reference chrcteristic C during the initiliztion phse. However, during BIST the enle signl for register C is kept zero, such tht finlly oth chrcteristics C nd cn e compred to provide the test result t the output of the comprtor. The BIST controller hs to relize two loops, one for initiliztion nd one for BIST, nd hs to control the write opertion within two clock cycles. One counter of

7 7, - length log 2 m, two flip-flops, nd some comintionl logic re sufficient for implementing these three modes, one of which hs two sttes. In ddition to this, we need four n-it registers C,, TPG, nd Test Register, nd some comintionl logic. Prototype implementtions show n re requirement of the entire BIST equipment in the order of n-it registers nerly independent of the memory size. The BIST hrdwre is not plced within the dtpth nd the ddress logic, nd there is no time penlty for red ccesses. In strightforwrd implementtion of write ccesses there my e one dditionl clock ltency, s the old contents of the refreshment register must e written into the test register efore the new vlue of the dt register cn e cptured y the register. This ltency is voided, if the refreshment register on the one side nd the test nd dt registers on the other side work on different clock phses. They my even work on the sme phse, if the refreshment register hs two ports nd the switch mtrix is douled. 4 Conclusions In this pper we hve proposed new method for the uilt-in test of memory consistency. In contrst to methods known so fr, reference signture is not computed y scnning the entire memory periodiclly, ut y djusting it dynmiclly. The reference vlue of the fult free contents of the is computed s modulo-2 ddress chrcteristic, nd new technique for output dt compression hs een presented sed on this chrcteriztion. It hs een shown tht the sme test qulity is chieved s y conventionl pproch sed on signture nlysis. But compred to conventionl signture nlysis schemes n enormous gin in time is chieved t only slightly higher hrdwre costs. 5 References V. C. Alves, M. Nicolidis, P. Lestrt, nd B. Courtois: Built-in Self-Test for Multi-Port s; Proceedings IEEE Interntionl Conference on Computer-Aided Design, ICCAD-9, Novemer 99, pp S. Brgllo, F. Corno, P. Prinetto, M. Sonz Reord: Testing Switching Memory in Telecommuniction System; Proceedings IEEE Interntionl Test Conference, Wshington, DC, Oct. 995, pp P. H. Brdell, W. H. McAnney, nd J. Svir: Built-In Test for VLSI: Pseudorndom Techniques; New York: John Wiley & Sons, H. Cheung, S. K. Gupt: A BIST Methodology for Comprehensive Testing of with Reduced Het Dissiption; Proceedings IEEE Interntionl Test Conference, Wshington, DC, Oct. 996, pp B. Cockurn, Y.-F. N. St: Synthesized Trnsprent BIST for Detecting Scrmled Pttern-Sensitive Fults in s; Proceedings IEEE Interntionl Test Conference, Wshington, DC, Oct. 995, pp R. Dvid, A. Fuentes, nd B. Courtois: Rndom Pttern Testing Versus Deterministic Testing of s; IEEE Trns. on Computers, Vol. C-38, No. 5, My 989, pp R. Dekker, F. Beenker, nd L. Thijssen: Relistic Built-In Self-Test for Sttic s; IEEE Design & Test of Computers, Vol. 6, No., Fe. 989, pp A. J. Vn de Goor: Testing Semiconductor Memories, Theory nd Prctice; Chichester: John Wiley & Sons, O. Keichi, M. Nicolidis, V. N. Yrmolik: Exct Alising Computtion for BIST; Proceedings IEEE Int. Test Conference, Wshington, DC, Oct. 995, pp K. Kinoshit, K. K. Sluj: Built-In Testing of Memory Using n On-Chip Compct Testing Scheme; IEEE Trnsctions on Computers, Vol. C-35, No., Octoer 986, pp K. T. Le, K. K. Sluj: A Novel Approch for Testing Memories Using Built-In Self-Testing Technique, Proceedings IEEE Interntionl Test Conference, Wshington, DC, 986, pp B. Ndeu-Dostie, A. Silurt, nd V. K. Agrwl: Seril Interfcing for Emedded-Memory Testing; IEEE Design & Test of Computers, Vol. 7, No. 2, April 99, pp M. Nicolidis: Trnsprent BIST for s; Proceedings IEEE Interntionl Test Conference, Bltimore, MD, Oct. 992, pp P. Olivo, M. Dlpsso: Self-Lerning Signture Anlysis for Non-Voltile Memory Testing; Proceedings IEEE Int. Test Conference, Wshington, DC, Oct. 996, pp T. R. N. Ro, E. Fujiwr: Error-Control Coding for Computer Systems; Englewood Cliffs, NJ: Prenctice Hll, Inc., N. Skshit et l.: A Built-in Self-Test Circuit with Timing Mrgin Test Function in Git Synchronous D; Proceedings IEEE Interntionl Test Conference, Wshington, DC, Oct. 996, pp V. N. Yrmolik: Anlysis of Signture Testility of Digitl Circuits; Automtion nd Remote Control, Mrch 99, pp Y. You, J. P. Hyes: A self-testing dynmic chip; IEEE JSSC, Ferury 985, pp