Analog Behavior Refinement in System Centric Modeling

Size: px

Start display at page:

Download "Analog Behavior Refinement in System Centric Modeling"

Patricia Singleton
6 years ago
Views:

1 Analog Behavior Refinement in System Centric Modeling Yaseen Zaidi, Christoph Grimm and Jan Haase Institute of Computer Technology Vienna University of Technology

2 The Motivation System level analog modeling possible with SystemC AMS: Executable specification AMS semantics Models of computations e.g. Timed Data Flow (TDF) Synchronization of MoCs of different domains Constant stepping fast simulation But need hooks for immediate refinement to utilize: Granularity supported by HDLs and HDLs/AMS Dedicated analogsolvers Fine/variable stepping Synchronization Yaseen Zaidi Institut für Computertechnik / TU Wien 2/11

$Abstract modeling SCA_TDF_MODULE(prefi_ac) { sca_tdf_in<double> in; sca_tdf_out<double> out; sca_sctdf_in<bool> xgain; // parameters double prefi_fc; //cut off freq double prefi_g0; //gain!$

3 Abstract modeling SCA_TDF_MODULE(prefi_ac) { sca_tdf_in<double> in; sca_tdf_out<double> out; sca_sctdf_in<bool> xgain; // parameters double prefi_fc; //cut off freq double prefi_g0; //gain!xgain double prefi_g1; //gain xgain // filter model sca_ltf_nd ltf_1; //filter inst sca_vector<double> A, B; //coeffs sca_vector<double> S; //states void init() { //filter coeffs B(0) = 1.0; A(0) = 1.0; A(1) = 1.0/(2.0*M_PI*prefi_fc);} void processing() { double tmp=ltf_1(b,a,s,in.read()); if (xgain.read()) ()) out.write(tmp * prefi_g1); else out.write(tmp * prefi_g0);} SCA_ CTOR(prefi _ ac) { // defaults prefi_fc = 1.0e6; prefi_g0 = 2.74; prefi_g1 = 2.74 * 2.2;} }; Yaseen Zaidi Institut für Computertechnik / TU Wien 3/11

4 System AMS can access and synchronize external simulators view classes solver classes TDF models TDF solver linear networks linear DAE solver linear DAEs other means other simulators DE modelling SC_METHOD SC_THREAD sc_signal< > synchronization Synchronization using TDF solver Discrete event simulator kernel Yaseen Zaidi Institut für Computertechnik / TU Wien 4/11

5 The Methodology Client Server SystemC kernel Synchronization Layer Solver Layer MATLAB, HDL, HDL- AMS, Verilog A, SPICE, other solvers AMS Extensions Executable Specification Digital MoCs TDF MoCs { ports, attributes(), read(), sig_proc(), write(), comm(), cosim wrapper } Software MoCs S o c k e t TCP/IP S o c k e t IUS, FastSPICE (UltraSIM) and Spectre solvers TCL I/f SPICE HDL-AMS HDL HDL TB IUS I/f HDL2C & C2HDL SHARED LIBRARY P L I Server program OS IPC C_Wrapper() read() load sim script fork() exec() call Cadence simulator write() Yaseen Zaidi Institut für Computertechnik / TU Wien 5/11

6 Execution of Cadence suite

7 Simulate various ADCs and DACs in HDLs/AMS Use VPI for Verilog and VHPI for VHDL model access Example system Yaseen Zaidi Institut für Computertechnik / TU Wien 7/11

8 Cosimulation instance in SystemC AMS specification SCA_TDF_MODULE(ad_converter) { sca_tdf::sca_in<double> in_tdf; sca_tdf::sca_out<sc_int<12> out_de;.. char *out_token_stream; token void processing() { token_collection = format_and_queue(in_tdf.read()); out_token_stream = cadence_cosim(token_collection);.. out_de.write<static_cast<sc_int<12> td tti t i t > format(out_token_stream);} ttk t )} } Yaseen Zaidi Institut für Computertechnik / TU Wien 8/11

9 Calling Cadence solver and C access of simulation child_pid_ncelab = vfork(); execv("ncelab", " amsfastspice", " propspath", "prop.cfg", "bench_a2d_12bit", " snapshot", "worklib.bench_a2d_12bit"); b ") child_pid_ncsim = vfork(); execv("ncsim", " input", "@tcl_script", " status", " analogcontrol", "acf.scs", "worklib.bench_a2d_12bit:behav", "+loadvhpi", "VHDL2C_DLL", "inst=:bench_a2d_12bit", "+start=0", "+stop=62"); Yaseen Zaidi Institut für Computertechnik / TU Wien 9/11

10 Conclusion SystemC AMS TDF semantics while suited for high level analog modeling can assist in cosimulation with refined models of HDLs AMS Synchronization layer allows connections of specialty simulators e.g. Spectre and FastSPICE A client (SystemC AMS) and server (Cadence) topology realized C/UNIX calls control of Cd Cadence simulation Access of simulation objects is made using standardized procedural interfaces (VPI/VHPI) Yaseen Zaidi Institut für Computertechnik / TU Wien 10/11

11 Thank you Yaseen Zaidi Institut für Computertechnik / TU Wien 11/11

Analog Behavior Refinement in System Centric Modeling

Analog Behavior Refinement in System Centric Modeling Author 1 Author 2 Author 3 Affiliation Organization Address emails ABSTRACT SoC designs consisting of analog, digital, mixed signal, RF and software