Question 5 (SP07 Final M1): Do You Remember?

Transcription

1 Question 5 (SP07 Final M1): Do You Remember? Decode the binary numbers into MIPS instructions with proper register names ( $s0, $t0, etc.).if there are any memory addresses, represent them in hex. Address 32 bit Binary Instruction Type (R, I, J) MIPS Instruction w/args 0xAFFFFFF xAFFFFFFC xB xB whatever... whatever ori $v0, $0, 0x61C 0xB whatever... whatever jr $ra You can replace the first instruction with a new instruction and save 2 clock cycles on a single cycle non delayed branch MIPS machine. What is it (in MIPS)? Careful!

2 Q5: MIPS Sleuth (15 points) SID: mystery, a mysterious MIPS function outlined below, is written without proper calling conventions. mystery calls a correctly written function, random, that takes an integer i as its only argument, and returns a random integer in the range [0, i - 1] inclusive. 1 mystery: addiu $sp $sp addu $s0 $0 $0 8 move $s1 $a0 9 move $s2 $a1 10 loop: srl $t0 $s beq $t0 $s2 exit 12 subu $a0 $s2 $t0 13 jal random 14 sll $v0 $v addu $v0 $v0 $s0 16 addu $t0 $s1 $s0 17 addu $t1 $s1 $v0 18 lw $t2 0($t0) 19 lw $t3 0($t1) 20 sw $t2 0($t1) 21 sw $t3 0($t0) 22 addiu $s0 $s j loop 24 exit: ) Fill in the prologue and the epilogue of this MIPS function. Assume that random follows proper calling conventions, and that it may make its own function calls. You may not need all of the lines. 2) What operation does this function perform on an integer array? Assume that both the integer array and the length of the array are passed into the function. 3) Would this function work as expected if a string was passed into the function instead? Write down the line numbers of all lines of MIPS code that must be changed (if any at all), so that the function works correctly on strings. Do not write down any extraneous line numbers. 7/8

3 Question 4: Solve this MIPStery in C! (Sp14 MT1) mipstery: Convert the above MIPS function, mipstery, into a C function using as few lines as possible. The ischarinstr function returns 1 if the string ($a0) contains the character ($a1), and 0 otherwise. mipstery(, ) { int count = 0; return count; }

4 Q4: beargit redux (15 points) SID: From project 1, you may remember the function is_commit_msg_ok() that you needed to implement in C. Here is a simpler rendition where commit messages are deemed okay if and only if those nullterminated commit messages exactly match go_bears. Using the fewest number of empty lines possible, finish writing the code below. You are only allowed to use the registers already provided and registers $t0-3, and $s0-s2 (but you will not need all of them). Assume these registers are initialized to 0 before the call to ISCOMMITOK. const char* go_bears = "THIS IS BEAR TERRITORY!"; int is_commit_msg_ok(const char* msg, const char* go_bears) { for (int i = 0; msg[i] && go_bears[i]; i++) { if (go_bears[i]!= msg[i]) return 0; } if (!msg[i] &&!go_bears[i]) return 1; return 0; } ISCOMMITOK: $t0 ($a0) $t1 ($a1) COND: and addiu $a0 $a0 1 addiu $a1 $a1 1 EXIT: $t2 $t0 $t1 90 li $v0 1 FAILED: li $v0 0 END: 6/8

5 Question 3 : free at last, thank gosh we are free at last We wish to free a linked list of strings (example below) whose nodes are made up of this struct. Complete the code below; we have started you off with some filled in. You may use fewer lines, but do not add any. FreeLL:beq,, NULL_CASE jal FreeLL lw $a0 0($sp) jal free NULL_CASE:jr $ra

6 Question 4 (su13 q2) : MIPStifying (9 points, 20 minutes) Answer the questions below about the following MIPS function. Answer each part separately, assuming each time that mystery() has not been called yet. A. Which instruction (number) gets modified in the above function? B. Write an equivalent arithmetic (not logical) C expression to instruction 1. a0 = C. Which instruction field gets modified when mystery is called with $a0 = 3? D. How many times can mystery(2) be called before the behavior of mystery() changes? E. How many times can mystery(0) be called before the behavior of mystery() changes? F. A program calls mystery with the following sequence of arguments: 0, 1, 2, 3, 4, 5. What MIPS instruction gets stored in memory?

7 MIPS Reference Data Card ( Green Card ) 1. Pull along perforation to separate card 2. Fold bottom side (columns 3 and 4) together M I P S Reference Data CORE INSTRUCTION SET OPCODE FOR- / FUNCT NAME, MNEMONIC MAT OPERATION (in Verilog) (Hex) Add add R R[rd] = R[rs] + R[rt] (1) 0 / 20 hex Add Immediate addi I R[rt] = R[rs] + SignExtImm (1,2) 8 hex Add Imm. Unsigned addiu I R[rt] = R[rs] + SignExtImm (2) 9 hex Add Unsigned addu R R[rd] = R[rs] + R[rt] 0 / 21 hex And and R R[rd] = R[rs] & R[rt] 0 / 24 hex And Immediate andi I R[rt] = R[rs] & ZeroExtImm (3) c hex if(r[rs]==r[rt]) Branch On Equal beq I 4 PC=PC+4+BranchAddr (4) hex if(r[rs]!=r[rt]) Branch On Not Equal bne I 5 PC=PC+4+BranchAddr (4) hex Jump j J PC=JumpAddr (5) 2 hex Jump And Link jal J R[31]=PC+8;PC=JumpAddr (5) 3 hex Jump Register jr R PC=R[rs] 0 / 08 hex R[rt]={24 b0,m[r[rs] Load Byte Unsigned lbu I 24 +SignExtImm](7:0)} (2) hex Load Halfword R[rt]={16 b0,m[r[rs] lhu I 25 Unsigned +SignExtImm](15:0)} (2) hex Load Linked ll I R[rt] = M[R[rs]+SignExtImm] (2,7) 30 hex Load Upper Imm. lui I R[rt] = {imm, 16 b0} f hex Load Word lw I R[rt] = M[R[rs]+SignExtImm] (2) 23 hex Nor nor R R[rd] = ~ (R[rs] R[rt]) 0 / 27 hex Or or R R[rd] = R[rs] R[rt] 0 / 25 hex Or Immediate ori I R[rt] = R[rs] ZeroExtImm (3) d hex Set Less Than slt R R[rd] = (R[rs] < R[rt])? 1 : 0 0 / 2a hex Set Less Than Imm. slti I R[rt] = (R[rs] < SignExtImm)? 1 : 0 (2) a hex Set Less Than Imm. R[rt] = (R[rs] < SignExtImm) sltiu I b Unsigned? 1 : 0 (2,6) hex Set Less Than Unsig. sltu R R[rd] = (R[rs] < R[rt])? 1 : 0 (6) 0 / 2b hex Shift Left Logical sll R R[rd] = R[rt] << shamt 0 / 00 hex 1 ARITHMETIC CORE INSTRUCTION SET 2 OPCODE / FMT /FT / FUNCT (Hex) NAME, MNEMONIC FOR- MAT OPERATION Branch On FP True bc1t FI if(fpcond)pc=pc+4+branchaddr (4) 11/8/1/-- Branch On FP False bc1f FI if(!fpcond)pc=pc+4+branchaddr(4) 11/8/0/-- Divide div R Lo=R[rs]/R[rt]; Hi=R[rs]%R[rt] 0/--/--/1a Divide Unsigned divu R Lo=R[rs]/R[rt]; Hi=R[rs]%R[rt] (6) 0/--/--/1b FP Add Single add.s FR F[fd ]= F[fs] + F[ft] 11/10/--/0 FP Add {F[fd],F[fd+1]} = {F[fs],F[fs+1]} + add.d FR {F[ft],F[ft+1]} 11/11/--/0 FP Compare Single c.x.s* FR FPcond = (F[fs] op F[ft])? 1 : 0 11/10/--/y FP Compare FPcond = ({F[fs],F[fs+1]} op c.x.d* FR {F[ft],F[ft+1]})? 1 : 0 11/11/--/y * (x is eq, lt, or le) (op is ==, <, or <=) ( y is 32, 3c, or 3e) FP Divide Single div.s FR F[fd] = F[fs] / F[ft] 11/10/--/3 FP Divide {F[fd],F[fd+1]} = {F[fs],F[fs+1]} / div.d FR {F[ft],F[ft+1]} 11/11/--/3 FP Multiply Single mul.s FR F[fd] = F[fs] * F[ft] 11/10/--/2 FP Multiply {F[fd],F[fd+1]} = {F[fs],F[fs+1]} * mul.d FR {F[ft],F[ft+1]} 11/11/--/2 FP Subtract Single sub.s FR F[fd]=F[fs] - F[ft] 11/10/--/1 FP Subtract {F[fd],F[fd+1]} = {F[fs],F[fs+1]} - sub.d FR {F[ft],F[ft+1]} 11/11/--/1 Load FP Single lwc1 I F[rt]=M[R[rs]+SignExtImm] (2) 31/--/--/-- Load FP F[rt]=M[R[rs]+SignExtImm]; (2) ldc1 I F[rt+1]=M[R[rs]+SignExtImm+4] 35/--/--/-- Move From Hi mfhi R R[rd] = Hi 0 /--/--/10 Move From Lo mflo R R[rd] = Lo 0 /--/--/12 Move From Control mfc0 R R[rd] = CR[rs] 10 /0/--/0 Multiply mult R {Hi,Lo} = R[rs] * R[rt] 0/--/--/18 Multiply Unsigned multu R {Hi,Lo} = R[rs] * R[rt] (6) 0/--/--/19 Shift Right Arith. sra R R[rd] = R[rt] >>> shamt 0/--/--/3 Store FP Single swc1 I M[R[rs]+SignExtImm] = F[rt] (2) 39/--/--/-- Store FP M[R[rs]+SignExtImm] = F[rt]; (2) sdc1 I 3d/--/--/-- M[R[rs]+SignExtImm+4] = F[rt+1] FLOATING-POINT INSTRUCTION FORMATS FR opcode fmt ft fs fd funct FI opcode fmt ft immediate Shift Right Logical srl R R[rd] = R[rt] >> shamt 0 / 02 hex PSEUDOINSTRUCTION SET Store Byte sb I M[R[rs]+SignExtImm](7:0) = 28 NAME MNEMONIC OPERATION R[rt](7:0) (2) hex Branch Less Than blt if(r[rs]<r[rt]) PC = Label Store Conditional sc I M[R[rs]+SignExtImm] = R[rt]; Branch Greater Than bgt if(r[rs]>r[rt]) PC = Label 38 R[rt] = (atomic)? 1 : 0 (2,7) hex Branch Less Than or Equal ble if(r[rs]<=r[rt]) PC = Label M[R[rs]+SignExtImm](15:0) = Branch Greater Than or Equal bge if(r[rs]>=r[rt]) PC = Label Store Halfword sh I 29 R[rt](15:0) (2) hex Load Immediate li R[rd] = immediate Move move R[rd] = R[rs] Store Word sw I M[R[rs]+SignExtImm] = R[rt] (2) 2b hex REGISTER NAME, NUMBER, USE, CALL CONVENTION Subtract sub R R[rd] = R[rs] - R[rt] (1) 0 / 22 hex PRESERVED ACROSS Subtract Unsigned subu R R[rd] = R[rs] - R[rt] 0 / 23 hex NAME NUMBER USE A CALL? (1) May cause overflow exception $zero 0 The Constant Value 0 N.A. (2) SignExtImm = { 16{immediate[15]}, immediate } $at 1 Assembler Temporary No (3) ZeroExtImm = { 16{1b 0}, immediate } Values for Function Results (4) BranchAddr = { 14{immediate[15]}, immediate, 2 b0 } $v0-$v1 2-3 No and Expression Evaluation (5) JumpAddr = { PC+4[31:28], address, 2 b0 } (6) Operands considered unsigned numbers (vs. 2 s comp.) $a0-$a3 4-7 Arguments No (7) Atomic test&set pair; R[rt] = 1 if pair atomic, 0 if not atomic $t0-$t Temporaries No $s0-$s Saved Temporaries Yes BASIC INSTRUCTION FORMATS $t8-$t Temporaries No R opcode rs rt rd shamt funct $k0-$k Reserved for OS Kernel No I $gp 28 Global Pointer Yes opcode rs rt immediate $sp 29 Stack Pointer Yes J $fp 30 Frame Pointer Yes opcode address $ra 31 Return Address No Copyright 2009 by Elsevier, Inc., All rights reserved. From Patterson and Hennessy, Computer Organization and Design, 4th ed.

8 OPCODES, BASE CONVERSION, ASCII SYMBOLS MIPS (1) MIPS (2) MIPS opcode funct funct Binary Decimal Hexa- ASCII deci- mal Character (31:26) (5:0) (5:0) Hexa- Decimadecimal (1) sll add.f NUL 64 sub.f SOH A j srl mul.f STX B jal sra div.f ETX C beq sllv sqrt.f EOT D bne abs.f ENQ E blez srlv mov.f ACK F bgtz srav neg.f BEL G addi jr BS H addiu jalr HT I slti movz a LF 74 4a J sltiu movn b VT 75 4b K andi syscall round.w.f c FF 76 4c L ori break trunc.w.f d CR 77 4d M xori ceil.w.f e SO 78 4e N lui sync floor.w.f f SI 79 4f O mfhi DLE P (2) mthi DC Q mflo movz.f DC R mtlo movn.f DC S DC T NAK U SYN V ETB W mult CAN X multu EM Y div a SUB 90 5a Z divu b ESC 91 5b [ c FS 92 5c \ d GS 93 5d ] e RS 94 5e ^ f US 95 5f _ lb add cvt.s.f Space lh addu cvt.d.f ! a lwl sub " b lw subu # c lbu and cvt.w.f $ d lhu or % e lwr xor & f nor g sb ( h sh ) i swl slt a * 106 6a j sw sltu b b k c, 108 6c l d d m swr e e n cache f / 111 6f o ll tge c.f.f p lwc1 tgeu c.un.f q lwc2 tlt c.eq.f r pref tltu c.ueq.f s teq c.olt.f t ldc1 c.ult.f u ldc2 tne c.ole.f v c.ule.f w sc c.sf.f x swc1 c.ngle.f y swc2 c.seq.f a : 122 7a z c.ngl.f b ; 123 7b { c.lt.f c < 124 7c sdc1 c.nge.f d = 125 7d } sdc2 c.le.f e > 126 7e ~ c.ngt.f f? 127 7f DEL (1) opcode(31:26) == 0 (2) opcode(31:26) == 17 ten (11 hex ); if fmt(25:21)==16 ten (10 hex ) f = s (single); if fmt(25:21)==17 ten (11 hex ) f = d (double) 3 IEEE 754 FLOATING-POINT STANDARD (-1) S (1 + Fraction) 2 (Exponent - Bias) where Single Precision Bias = 127, Precision Bias = IEEE Single Precision and Precision Formats: MEMORY ALLOCATION STACK FRAME Stack $sp 7fff fffc hex $gp pc S Exponent Fraction S Exponent Fraction hex hex hex 0 hex Dynamic Data Static Data Text Reserved 4 IEEE 754 Symbols Exponent Fraction Object 0 0 ± ± Denorm 1 to MAX - 1 anything ± Fl. Pt. Num. MAX 0 ± MAX 0 NaN S.P. MAX = 255, D.P. MAX = Argument 6 Argument 5 Saved Registers Local Variables DATA ALIGNMENT Word Word Word Halfword Halfword Halfword Halfword Byte Byte Byte Byte Byte Byte Byte Byte Value of three least significant bits of byte address (Big Endian) EXCEPTION CONTROL REGISTERS: CAUSE AND STATUS B Interrupt Exception D Mask Code Copyright 2009 by Elsevier, Inc., All rights reserved. From Patterson and Hennessy, Computer Organization and Design, 4th ed. Higher Memory Addresses Stack Grows Lower Memory Addresses Pending U E I Interrupt M L E BD = Branch Delay, UM = User Mode, EL = Exception Level, IE =Interrupt Enable EXCEPTION CODES Number Name Cause of Exception Number Name Cause of Exception 0 Int Interrupt (hardware) 9 Bp Breakpoint Exception 4 Address Error Exception Reserved Instruction AdEL 10 RI (load or instruction fetch) Exception 5 Address Error Exception Coprocessor AdES 11 CpU (store) Unimplemented 6 IBE Bus Error on Arithmetic Overflow 12 Ov Instruction Fetch Exception 7 DBE Bus Error on Load or Store 13 Tr Trap 8 Sys Syscall Exception 15 FPE Floating Point Exception ASCII Character SIZE PREFIXES (10 x for Disk, Communication; 2 x for Memory) PRE- PRE- PRE- PRE- SIZE FIX SIZE FIX SIZE FIX SIZE FIX 10 3, 2 10 Kilo , 2 50 Peta milli femto- 10 6, 2 20 Mega , 2 60 Exa micro atto- 10 9, 2 30 Giga , 2 70 Zetta nano zepto , 2 40 Tera , 2 80 Yotta pico yocto- The symbol for each prefix is just its first letter, except µ is used for micro. $fp $sp MIPS Reference Data Card ( Green Card ) 1. Pull along perforation to separate card 2. Fold bottom side (columns 3 and 4) together