CPS 104 Final Exam. 2pm to 5pm Open book exam. Answer all questions, state all your assumptions, clearly mark your final answer. 1.

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1 CPS 104 Final Exam 2pm to 5pm Open book exam Answer all questions, state all your assumptions, clearly mark your final answer. Be sure you have all eight (8) pages of the exam. Write your name on each page of the exam. Read all questions and use your time accordingly. Good Luck! Name: 1. (30 pts) 2. (30 pts) 3. (30 pts) 4. (30 pts) 5. (30 pts) Total (150 pts) CPS 104 Final Exam 1

2 Question 1. (30 pts) Data Path Design a.) (20 points) Word addressable memory means that only words (32-bits) can be read/ written from/to the memory structure. Even with this restriction, some machines have instructions that want to read less than the full 32-bit word (e.g., load byte, load halfword). Modify the single cycle data path shown below to support load unsigned byte (lbu) and load unsigned halfword (lhu) from a word addressable memory. The six bit opcodes for lw, lbu, & lhu are 0x23, 0x24, 0x25, respectively. Clearly show and explain all modifications (including control signals) and any additional gates and/or circuits you use. Assume the bytes within a word are numbered 3210 (e.g., in the word 0xABCDEF01, byte 2 is CD), and half words are numbered 10. Figure Copyright Morgan Kaufmann 1998, All Rights Reserved CPS 104 Final Exam 2

3 Question 1. (continued) b.) (10 points) Fill in the control signal values in Table 1, below, for the respective memory load operations from part a. Add any additional control signals to the bottom of Table 1. The ALUOp0 and ALUOp1 signals control the ALU in the following manner. Note this is a subset of the ALU signals shown in the text book. ALU Operation ALUOp0 ALUOp1 A + B 0 0 A - B 0 1 A AND B 1 0 A OR B 1 1 TABLE 1. Fill in these control signals. Control Signal lw lhu lbu RegDst ALUsrc MemtoReg RegWr MemRd MemWr Branch ALUOp1 ALUOp0 CPS 104 Final Exam 3

4 Question 2. (30 pts) Datapath Control Consider the single clock cycle implementation of the MIPS processor shown in the diagram on page 2, but without your modifications. The ALUOp0 and ALUOp1 signals control the ALU in the following manner. Note this is a subset of the ALU signals shown in the text book. ALU Operation ALUOp0 ALUOp1 A + B 0 0 A - B 0 1 A AND B 1 0 A OR B 1 1 ExtOp = 0 means zero-extend and ExtOp = 1 means sign-extend. Show the control values for the following instructions: addi $s1, $s2, 0x20 beq $s1, $s2, (-64) sub $s1, $s2, $s2 TABLE 2. Fill in these control signals for the above instructions. Control Signal RegDst ALUsrc MemtoReg RegWr MemRd MemWr Branch Jump ExtOp ALUOp1 ALUOp0 addi beq sub CPS 104 Final Exam 4

5 Question 3. (30 points) Cache Memory Organization a.) (15 points) Draw a block diagram of a 16 kilobyte, 2-way set-associative cache with 32 byte blocks. Clearly show how an address from the CPU is used to determine if the block is resident. CPS 104 Final Exam 5

6 Question 3. (continued) b.) (15 points) Assume a 16 entry direct-mapped cache with 16 byte blocks and the initial contents of the TAG array shown below. 1.) Label each of the 10 memory accesses, that occur in the order shown on the bottom of the page, as a HIT or MISS, 2.) show the contents of the TAG array when execution is complete, and 3.) compute the cache miss ratio for the access sequence given. Each memory access is a byte address. Index TAG Initial TAG Final 0 0xFFFFF0 1 0xFFEA10 2 0x xAB14F0 4 0xA14F0B 5 0xBF x00001B 7 0x4AB02B 8 0x x xFFFFF0 11 0xA4110A 12 0x xBCD20F 14 0x00001A 15 0xFFF0A0 Memory Access Address Hit/Miss 0x00001AEC 0x000011EC 0xFFFFF0A0 0x x0BA12E10 0xA4110A48 0xFFFFF0A0 0xFFFFEB1C 0xA4110A40 0x000011E0 Miss Ratio = CPS 104 Final Exam 6

7 Question 4. (30 points) Virtual Memory a.) (7 points) What is fragmentation? b.) (8 points) Describe the basic operation of a TLB and its relationship to a Page Table. c.) (8 points) What is the difference between a page fault and a TLB miss? d.) (7 points) Assuming a virtual memory system with 4KB pages, what 24-bit physical address does the 32-bit virtual address 0x4A03FD12 map to, given the four entry fullyassociative TLB and it contents shown below? Acc Valid Virtual Physical rw 1 0x03FD1 0x123 rw 1 0x4A03F 0xAFC rw 1 0xA4032 0x81F rw 1 0xFD120 0x73C CPS 104 Final Exam 7

8 Question 5 (30 pts): Peripherals (I/O) a.) (15 pts) A program repeatedly performs a three step process: It reads in an 8-KB block of data from disk, does some processing on that data, and then writes out the result as another 8-KB block elsewhere on the disk. Each block is contiguous and randomly located on a single track on the disk. The disk drive rotates at 7200 RPM, has an average seek time of 6 ms, and has a transfer rate of 25MB/sec. The controller overhead is 1.5ms. No other program is using the disk or processor, and there is no overlapping of disk operation with processing. The processing step takes 15 million clock cycles, and the clock rate is 500 MHz. What is the overall speed of the system in blocks processed per second? b.) (15 points) List (i.e., no long description, sentence fragments are ok) the basic steps that occur within the processor and operating system to service an interrupt from one of several possible devices and to return to the interrupted program. CPS 104 Final Exam 8