AMIS CDNLive Paper: A DFII Based Place and Route Interface

Transcription

1 Table of Contents Chapter 1.0 Overview Chapter 2.0 Implementation Chapter 3.0 Digital Integration Form Chapter 4.0 To P&R Tab Chapter 5.0 From P&R Tab Chapter 6.0 Summary 1/17

2 Introduction Chapter 1: Overview AMI Semiconductor (AMIS) mixed-signal design engineers need an easy way to Place and Route (P&R) simple, small (less than 100k gates) digital blocks and chips from within their design environment (i.e. Cadence DFII). Due to cost and training requirements, the solution must minimize interaction with the P&R tool. This paper discusses a DFII based user interface created to allow mixed-signal design engineers easy access to Nano Encounter DBS via generated scripts. Additionally, planned enhancements are discussed in the last chapter. Benefits The P&R interface assists the user in gathering, formatting and constraining the data necessary for P&R. It abstracts the tasks to a level which allows the user to focus on the aspects of the P&R process most applicable to their designs, while allowing additional user customizing of scripts when necessary. Special attention is also paid to mixed-signal needs, such as floorplanning and multiple power domain assignment/verification. Time-to-market is improved, since formal hand-offs to a dedicated P&R group are eliminated for simple blocks or chips. For more complicated blocks and chips, the interface assists the designer in formatting and packaging data for hand-off to a dedicated P&R group. Cost NanoEncounter DBS was chosen as the P&R tool, since most mixed-signal designs are under 300k gates and therefore do not need hierarchical P&R treatment. By utilizing WAN licenses, all design centers are enabled with P&R capabilities. A script based (i.e. batch) interface was chosen to minimize Encounter usage and eliminate GUI training requirements. Guiding the engineer through P&R via a targeted GUI and generated scripts also allows P&R of basic blocks/chips, without requiring a dedicated P&R engineer or extensive Encounter knowledge. Limited floorplanning and visualization can be performed via Virtuoso XL. 2/17

3 Chapter 2: Implementation SKILL was chosen as a natural implementation language, since the interface would be used in the DFII environment. In addition, Perl scripts are used for netlist manipulation (i.e. removing supply pins, adding supply pins). The SKILL code generates the user interfaces (see chapter 3) and scripts for each task (i.e. netlist import/export, running Encounter/Conformal). The SKILL code also controls the data flow (i.e. where design data is located, how it s formatted, how it travels from one tool to the next, etc.). This allows new tools and flows to be implemented and enforced via a common, familiar user interface. The main GUI controls design tasks from synthesis to final verification. The tasks are divided into four tabs: Initial Verification, To Place&Route, From Place&Route and Final Verification. However, this paper will be limited to the P&R functionality described by the To Place&Route and From Place&Route tabs. The following chapters describe the form and applicable tabs in more detail. Implemented data checking includes netlist/script/library existence verification, inconsistent data (e.g. project setup voltage vs. cell library voltage) and stale data (e.g. verifying that layout views are older than abstract LEF). The generated user interfaces guide the engineer through completing the necessary tasks in their required order, while giving the user access to the most common switches for easy customization. To accommodate easy transitions from DFII to the command line environment, XTerm buttons are provided on each form, which launch a terminal in the relevant run directory. All interface settings are saved in a cell.setup file, allowing one or more engineers to resume previous sessions. However, by design, it does not allow multiple engineers to use different settings for tasks operating on the same cell. 3/17

4 Chapter 3: Digital Integration Form The top half of the form (figure 1) contains tools and settings that feed the functions found in the lower (tabbed) half of the form. The pull-down menus at the top of the form represent optional tasks associated with the other tab functions. They are divided by function: Window, Tools, Utilities, and AMIS Help. The Design context info box designates the operational cell with its associated constraints and directory structure. Functionality of the top half of the form is described in more detail in the next sections, while the relevant tabs on the bottom half of the form are discussed in the next two chapters. Figure 1 (note: print to see full resolution): Window Menu: The Window menu currently contains Close, which will close the Integration window. Tools Menu: The Tools menu organizes various custom tools used during the circuit design process to prepare data for use in this integration environment. Pad Tools, IP Tools, Check Cell and Create Abstract are custom tools created by AMIS, which allow the designer to create the top level schematic, including pad ring, add any necessary digital or analog IP, check that all custom cells are ready for P&R and generate usable abstracts respectively. Utilities Menu: Utilities are optional tasks which can operate across multiple tabs. The Job utility monitors tasks executed from the integration tool, allowing the user to kill any stalled tasks. The Batch utility allows batch execution of any/all tasks called in the integration form, along with user created post-processing scripts. This use model allows the user to initially setup and run the tasks from the tabs. After initial setup, as changes are made to the design data, the tasks can be executed in batch mode, reproducing and verifying the design steps. AMIS Help Menu: The AMIS Help menus link to context sensitive help in the user guide and methodology flow diagrams. 4/17

5 Design context info The Design context info box (figure 2) lists settings which affect all tabs beneath the box, such as the design/cell being addressed, corresponding constraints and relevant run directory functions. Design Setup sets the DFII context Path to cds.lib, Library, Top Cell, and CellView (see next section). Constraints opens an interface to create/add SDC files and manage PVT points. These constraints feed the functions and script generators found on the other tabs. The Get button invokes the global function indicated (e.g. Xterm, clean or logs) in the cell specific run directory indicated. This allows the user to easily switch to a command line interface, check logs or delete all files in the directory indicated. Figure 2: Constraints Form: This form (figure 3) allows the user to import or generate the SDC Files, used during STA and P&R. Process voltage temperature (PVT) information is not included in the SDC files, since it is set according to library and automatically inserted in STA and P&R scripts. PVT for the SC Library and Pad Library may be set via the associated tables. Metals allows the user to limit the number of metals used during P&R. The Ports button opens a form (see next section) to allow the user to edit port information, generating the SDC file listed in the Mode Template. The Edit button can be used to add constraints not covered by the template. Existing SDC files can be loaded via the Load button and then be manually edited to remove PVT data via the Edit button. The Add button adds the Import SDC file to the verification list. Figure 3: 5/17

6 Port Constraints Form: This form (figure 4) allows the user to edit parameters associated with each pin. The Update button gets the pins from the DFII cell symbol, enters defaults (i.e. type, load, delay, related clock) for new pins, and lists the pin name, direction and properties for each pin. The Modify button changes the current values associated with the selected pins to the values at the bottom of the form, according to the Type selected (a - is placed in irrelevant fields). Get Tester Load and Get buf Load/Drive enters the characterized load from the listed ATE or selected standard cell buffer pin load (respectively) in the Load column edit box. Upon completion (i.e. Window->Save/Close), the form will create the SDC file listed on the Constraints Form Mode Template. For signal ports (i.e. ports with Type set to signal), loading, delay, and related virtual clock information is implemented in the SDC file. Supply pins are not included in the SDF file. A set_case_analysis statement is created for pin types clear and set. For clock pins, both a clock and a virtual (related) clock are created with the specified parameters (load and delay are irrelevant). Other information, such as generated clocks, embedded test pins and false paths can be added to the SDC file manually. Figure 4: 6/17

7 Chapter 4: To Place&Route Tab Figure 5: This tab (figure 5) automates the hand-off from design to P&R. Export Netlist exports the Verilog netlist and generates Liberty loading models for each custom cell. Check Design runs both standard and AMIS customized logical checks for any architecture issues. STA runs static timing analysis on the pre-layout netlist, using the SDC files listed in the Constraints form. Scan insertion integration is not currently available (hence the greyed out Insert Scan, LEC and STA buttons), but should be performed after export, before pre-layout STA. Automating scan insertion, along with JTAG and ATPG, will be added as an enhancement. The P&R Requirements button invokes a form to setup P&R constraints. Those constraints can then be sent to either the Central P&R team or directly to Encounter for batch P&R, in the case of a simple circuit. The later case is similar to running P&R, along with the tasks on the From P&R tab, but is not recommended for blocks or chips needing significant floorplanning or complicated CTS. To accommodate more complicated blocks/chips, Tar for Transfer uses tar and gzip to create an archive file intended to be handed off from remote design centers to Central P&R (or CAD for bug evaluation). View Report allows the user to verify there were no issues during the creation of the archive file. Netlist export and P&R requirements are discussed in more detail next. 7/17

8 Logic Export Form: This form (figure 6) exports the Verilog netlist (via si) and creates Liberty files (for custom cells with AmisCustom views), used by STA and Encounter. It also creates a custom.vams netlist, which can be referenced as a Verilog simulation library in the appropriate simulator. The custom.vams contains either Verilog models, if they were available during IP or pad import (using the corresponding AMIS import tools), or empty (i.e. skeleton) modules if no model was imported. Figure 6: Note: An AmisCustom view has a property bag containing pin information (i.e. pin loading, type, etc.) for each custom block (i.e. memory, analog, pad) in DFII. It also acts as a stopping view for the Verilog netlister and an identification view for semi-automated abstract generation and power extraction. Update Cell List searches the schematic hierarchy for Amis- Custom views and then returns the library, cell and category for each custom cell it finds. Vlog Options controls the netlisting view/stop lists. The XTerm button opens an xterm in the associated run directory. Check Cells runs a series of checks to verify that DFII cell views (i.e. symbol, schematic, layout, AmisCustom) are consistent for P&R. Results of the check can be viewed via View Report. 8/17

9 P&R Requirements Form: This form (figure 7) allows the user to input P&R constraints at either the digital block or chip level. The entered information can then be either transferred to Central P&R (via the Tar for Transfer button on the To Place&Route tab), or used to run NanoEncounter DBS in batch mode (batch mode not recommended for chip level P&R or digital blocks requiring complex floorplanning/cts). The form is divided, according to the associated aspects of P&R, into five tabs ( Spare Cell, Boundary, Placement, Routing, and Encounter ). Each tab is described in the next sections. Figure 7: Spare Cell (JIC) Tab: This tab allows the user to add spare cells or Just In Case logic to the netlist before P&R. Spare Cell List: shows the cells currently chosen to be added to the netlist as JIC. Tieoff cell shows whether the spare cell inputs will be tied high or low (outputs float). The JIC netlist is automatically generated and added into the main netlist by pressing Build JIC. The Browse button will open a list of cells to choose. Add appends the listed Cell and associated Quantity to the Cell List. Likewise, Remove deletes the selected cell from the Cell List. JIC From Encounter lists the available spare cells found in the Encounter database (for ECOs). 9/17

10 Boundary Tab: This tab (figure 8) allows the user to set basic boundary related parameters. Constrain core by specifies the core perimeter of the block or chip by either Aspect Ratio or X / Y. Note: If X and Y dimensions are used, the Aspect Ratio is ignored. The die dimensions are core dimensions + IO to Core spacing + pads (if applicable). button can be used to append the settings to the list. Likewise, blockages selected in the list can be removed via the Remove button. Similarly, the Remove All button may be used to delete the entire Blockage list. Figure 8: Pin Placement can be taken from either the Pad Tools (if chip level) or the cell s Virtuoso layout_fp view. If neither are available, an Encounter pin template can be generated in either sequence (i.e. order based) or location (i.e. X/Y) format. The Edit button allows the user to fine tune the pin file, if necessary. Note: If no file is listed, pins will be auto-placed, during P&R. Placement and/or metal blockage can be added to the Obstructions area of the form. The Blockage List shows the current blockages that will be set for Encounter P&R. If a layout view exists, containing blockage (i.e. metal1, 2, etc. or BNDRY layer for placement), the blockage locations can be automatically extracted from the DFII layout view and entered into the Blockage List via Get Blockage (all metal and BNDRY rectangles in the layout will be extracted as blockage). To manually add a new blockage, set the applicable Metal (i.e. all, none, metal1, metal2, etc.) blockage and check the Placement box if standard cells should not be placed in the box described by the coordinates llx through ury (e.g. lower left X location and upper right Y location respectively). Once the type of blockage and bounding box have been set, the Add Since Placement blockage eliminates standard cell rows in the specified bounding box, it can be used to create non-rectangular (i.e. rectilinear) digital block boundaries. For example, if a T shape is desired, add placement blockage to the lower left corner and lower right corner of the rectangular digital block (power bussing will follow the remaining standard cell rows). Note: Row Select is calculated as the center of the specified X/Y boundary when the Generate from X/Y boundary button is pressed. This specifies a point to select a remaining standard 10/17

11 cell row, allowing the supply bussing to follow the created rectilinear boundary created by Placement blockage. If the X/Y point shown conflicts with Placement blockage (i.e. in the case of a U shape), enter a point not contained by any Placement blockage bounding box. Placement Tab: The Abstract Instance box (figure 9) shows all macro instances in the design. If the design only contains standard cell logic, this box will be empty. The modifiable fields associated with this box allow the user to floorplan each instance relative to another instance or core boundary area. The Update button extracts the custom block instances from the design (designated via AmisCustom view), while the Modify button changes the current values listed to the new values selected at the bottom of the form. Quad sets the quadrant (e.g. Top Right, Bottom Left, etc.) of the Reference Object (e.g. Top_Core_Boundary or Abstract Instance ) Corner set. Xsp sets the spacing offset in the X direction (i.e. how much space will be between the Abstract Instance and Reference Object ). Likewise, Ysp sets the spacing offset in the Y direction. Orient sets the Abstract Instance urination (e.g. R0 = no rotation, R90 = 90 degree rotation, MX = mirror X, MY270 = mirror Y and rotate 270 degrees). Group sets the group number of the Abstract Instance. Set multiple instances to the same group if the associated supply bussing should surround the entire group, rather than individual instances (make sure they all share the same supply buses). Note: Relative floorplan assumes a single anchor for each group (i.e. only one instance referencing a core boundary per group) and no reference loops (i.e. instance1 references instance2, which references instance1). Alternately, absolute locations can be specified by checking the Reference X,Y box and entering associated X and Y coordinates before pressing the Modify button. Plus, if any listed blocks are placed in a VirtuosoXL layout_fp view, Get Coordinates can import the locations ( Gen from Source in VirtuosoXL should be used to create the abstract instances). Figure 9: Level Shifter Setup creates the code necessary to place level shifters on power domain boundaries. Level shifters can be either manually inserted in the source schematic or automatically inserted by Encounter. Generate creates the listed Level Shifter Template. The template is set for a high voltage default domain, containing the 11/17

12 entire chip or block (i.e. including pads and analog, if present) and a low voltage cut domain (i.e. standard cell sub-block). The template places level shifters in the standard cell cut domain. The default/cut domain conditions and level shifter placement conditions can be modified as necessary via Edit. Domain Cut lists the bounding box of the power domain to be cut from the default power domain. Assign Instances lists the hierarchical names of the instances to be included in the new power domain created by Domain Cut. Routing Tab: This tab (figure 10) lists special considerations given to both power and signal nets. In mixed-signal design, multiple power domains are common, so care must be taken to insure that cell and pad supplies get routed correctly, per the schematic. Unfortunately, netlisting (both export and import) is a common place for supply information to be lost or modified. In contrast, Extract Power extracts the power connections directly from DFII schematic database, creating the power assignment Encounter Script. View Trace views the extracted power trace report, which summarizes the supply connections. Later (after post-layout netlist import), power is re-extracted and compared to the pre-layout results. The Net Options list shows the net names that need special consideration (i.e. either shielding or hand routed). The Route column specifies if the net will be shielded or exempt from auto-routing (i.e. routed by hand). If the net is routed, the Shields column shows the shield supplies to be placed on either side of the specified net. Add appends the entered Net Name, Route and Shields to the Net Options list. Likewise, the Remove button deletes any selected nets from the list. Figure 10: The Core Supply (updated by Extract Power ) box shows all supplies in the design. The Update button gets the supplies, while the Modify button changes the width of the selected supplies. Enter 0 for supplies that should not be routed as rings around their associated cells. IO to Core Spacing defaults to offset (5u) + LVDD + LVSS + spacing (1u/supply), which the user can override. 12/17

13 Encounter Tab: This tab (figure 11) is the interface to Encounter via script generation and batch mode execution. Uniquify Netlist runs an Encounter script which makes all modules unique. Localize Encounter Libraries copies all libraries to the encounter directory and updates the paths in the Config File to facilitate tar for transfer to anyone not in the local project environment. CTS SDC sets which SDC file mode should be used for CTS in the Config File. The Scan SDC file is recommended, since it is usually worst case for clock tree balancing. However, in some cases topology may dictate otherwise. This value can be set to none, if CTS should not be performed. The Config File also sets the Encounter libraries, netlist, IO placement file, and floorplan dimensions. The Generate buttons create the file listed from the form settings and project setup. The associated Edit... buttons invoke a text editor to view or modify the listed file. Guide or Timing Closure Guide). The documentation is provided to users needing to go beyond the common switch settings provided in the command file. If Metal ECO is selected, an ECO script will be created. The script imports the new data, but reuses the previous floorplan, placement and routing information. The script will also Route Supplies (if checked), substitute JIC logic and re-route the modified signal nets where necessary (if checked). Backup Db for ECO should be ran before an ECO is actually performed, in case the pre-eco design is needed again (revert, using Restore pre-eco Db ). For all level ECOs, modify the original SOCE Command File as necessary and re-run. Figure 11: The Encounter Command File Tasks control the steps included in the SOCE Cmd File (i.e. floorplanning, placement, optimization, CTS, routing, etc.). If the design context is set to the top (i.e. pad) level, Add Pad Ring Fillers can be selected. If Nanoroute is not routing well (e.g. designs with less than 4 metals), Use Wroute will switch to Wroute. The Default All, Set All and Clear All apply the stated functions to all command file task boxes. If only intermediate steps are selected (i.e. Route Nets without Floorplan or Place ), the previous design will be loaded, rather than initializing a new database. SOCE Help invokes a PDF viewer for the selected Cadence documentation (i.e. Encounter Command Reference, User View DRC and View LVS allow the user to view the results of Encounter s internal physical verification (i.e. not 13/17

14 final signoff quality) to determine if there were any issues with the P&R. Figure 12: Run Quick APAR (figure 12) operates Encounter in batch mode, using the specified Config File and Cmd File. The form also controls which tasks will be performed after P&R (i.e. DFII import, LEC, STA, PEC). Once the user chooses which tasks to run by selecting the appropriate check boxes, the Apply button will run those tasks. Upon completion, the user may review the task outputs, using the associated buttons (i.e. Open Layout, View Report, etc.). All tasks on this form can also be performed manually via the From Place&Route tab. The Select All and Clear All buttons select and clear all tasks, respectively. Note: If tasks are selected that feed other selected tasks (i.e. Extract RC and Run STA/SDF or Run NanoEncounter and any other task), the batch run becomes blocking (i.e. nothing else is executed until the initial tasks complete). 14/17

15 Chapter 5: From Place&Route Tab This tab (figure 13) is intended to be the primary interface for the hand-off back from Central P&R. The tasks listed are identical to the Quick (Batch) APAR tasks listed previously. Conformal integration via the LEC form is discussed in greater detail next. Figure 13: Import Layout streams in (via PIPO) the GDS created by Encounter, creating a layout view for the DFII database top cell. PIPO Options gives access to the stream in options. Open Layout opens the Virtuoso layout view created by Import Layout. Check Design runs both standard and AMIS customized logical checks for any architecture issues induced by P&R. LEC performs a Logical Equivalence Check between the pre and post-layout netlists. STA runs static timing analysis on the post-layout netlist and creates an SDF file from the SPEF file generated by Extract RC. Import Verilog brings the netlist back into the DFII database as structural_post and netlist_post views (via ihdl). The _post view names allow the user to revert to the original schematics by deleting these views via Undo Import. They also allow the netlisting view lists to stay current by automatically picking the _post view if available. Backup pre-eco will copy _post DFII views to _preeco views (used before beginning an ECO). Restore Pre-ECO copies the _preeco views back to _post and then deletes the _preeco views. Power Equival. Check re-runs Extract Power to verify pre/post P&R power equivalency. The results can be reviewed via View Report. 15/17

16 Logic Equivalence Check (LEC) Form: This form (figure 14) interfaces with the Cadence Conformal tool to prove logic equivalence between two Verilog netlists (either pre/post synthesis or pre/post place and route). LEC is performed after P&R, to verify that only gates were sized and buffers modified (i.e. inserted/deleted/sized) via clock tree synthesis (CTS) and timing optimization. If scan chains are reordered, logic equivalence will be affected in scan mode. OK invokes Conformal and executes the listed LEC Script. XTerm opens an xterm in the run directory. If Use GUI is checked, the Conformal GUI will be invoked after an initial LEC is performed. View Report allows the user to verify that the LEC was successful. Generate creates the command file shown in the box labeled LEC Script, while Edit invokes the default editor to edit the LEC Script in special cases where additional commands need to be used (i.e. when scan chains have been reordered). Figure 14: 16/17

17 Chapter 6: Summary This paper has outlined a solution for providing a cost effective P&R interface to mixed-signal designers. Several AMIS production devices have used the user interface to floorplan, place, CTS, and route digital blocks in minutes, rather than preparing a formal handoff and then waiting for days for a central P&R group to queue the design and return the finished product. Thus, employing this interface has improved time-to-market without significantly increasing tool cost. Tool Enhancements In the future, moving from the CDB database to OpenAccess (OA) should remove LEF (for abstract and technology descriptions) from the flow, since Encounter can use the technology and abstract views from the DFII library. script generation are locked in SKILL structures. This information could be made accessible to both the DFII and shell based design environments. This would allow designers in either environment to share information, making collaboration and true mixed-signal design easier. Schematic net attributes to guide P&R (e.g. unrouted, first routed, shielded, and variable width/spacing) could be added to DFII, which would be useful for both Encounter and CCAR. Support for multiple pad libraries could also be added, but would need to allow for multiple pad heights and their associated fillers too. Virtuoso Chip Editor (VCE) looks promising for enhanced floorplanning (e.g. pre-routing and supply ring floorplanning) and visualization (e.g. floorplan and violation viewing), since it runs on OA natively (i.e. reading/writing the same database as Encounter). VirtuosoXL could provide this function too, once it understands route constructs. Ultimately, if Encounter eventually understands polygons, chip finishing (i.e. cleaning up routes, modifying supply busing, adding spare cap, etc) could be done in either environment. Methodology Enhancements Currently, files (i.e. SDC, scripts, netlists) are available to the netlist based (i.e. shell or command line) environment. However, the relation of those files to the design settings that control 17/17