Al Yanes / President / PCI-SIG

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2 PCI Express: Delivery Bandwidth fr OCP Al Yanes / President / PCI-SIG

3 Click PCI-SIG t edit Snapsht Master title style Organizatin that defines the PCI Express (PCIe ) I/O bus specificatins and related frm factrs member cmpanies lcated wrldwide Creating specificatins and mechanisms t supprt cmpliance and interperability. BOARD OF DIRECTORS Australia Austria Belgium Brazil Bulgaria Canada China Czech Republic Denmark Finland France Germany Hng Kng Hungary India Ireland Israel Italy Japan Malaysia Nrway Russia Singapre Slvak Republic Suth Krea Sri Lanka Sweden Switzerland Taiwan The Netherlands Turkey United Kingdm United States Cpyright 2018 PCI-SIG - All Rights Reserved 3

4 Click PCI Express t edit Master 4.0 title style PCI-SIG cntinues its slid reputatin f delivering lw cst, high-perfrmance, lw-pwer specificatins fr multiple applicatins and markets. PCI Express 4.0 Specificatin (16GT/S) Finalized and published Octber 2017 Includes new perfrmance enhancements Maintains psitin as the intercnnect f chice fr the expansive strage market and the backbne fr the fast grwing clud ecsystem Cpyright 2018 PCI-SIG - All Rights Reserved 4

5 Click PCI Express t edit Master 4.0 title style PCIe 4.0 Key Functinal Enhancements Lane Margining at the Receiver - Allws systems t determine hw clse t the edge each lane is perating Expanded Tag and Credits Allws bth tags/credits t service devices fr future usage 10 bit Extended Tags supprt upt 1024 transactins Scaled Flw Cntrl supprts larger credits PCIe 4.0 Electrical Maintains backward cmpatibility with installed base f PCIe devices Limited channel reach: apprx. 12 ne cnnectr (including 4 add-in card) Lnger channels require retimers r lwer lss channel PCIe 4.0 Adptin Numerus vendrs have 16GT/s PHYs in silicn Majr IP vendrs ffering 16GT/s cntrllers Dzen 16GT/s slutins at a recent PCI-SIG Cmpliance Wrkshp Several member cmpanies have exhibited 16GT/s dems Cpyright 2018 PCI-SIG - All Rights Reserved 5

6 Click Pwer t Efficient edit Master Perfrmance title style Delivers Scalable Perfrmance Width scaling: x1, x2, x4, x8, x12, x16, Frequency scaling: Five generatins 2.5 and 5 GT/s with 8b/10b encding 8 and 32 GT/s with 128b/130b encding Lw Pwer (Active/Idle) Rich set f Link and Device States L0s, L1, L1-substates, L2/L3 D0, D1, D2, D3_ht/cld Platfrm-level pwer ptimizatin hks: Dynamic Pwer Allcatin, Optimized Buffer, Flush Fill, Latency Tlerance Reprting Active pwer 5pJ/b, Standby pwer: 10uW/Lane Vibrant ecsystem with IP Prviders Cpyright 2018 PCI-SIG - All Rights Reserved 6

7 Click PCI Express t edit Master 4.0 Channels title style Lnger Channel Shrt Channel Add In Card Retimer Rt Cmplex Chip Basebard ruting <10 AC Cap End t end lss target ~= 28 db Rt Package lss ~= 5 db Add-in Card Package lss ~= 3 db Ttal Add-in Card ~= 8.0 db Cnnectr < 1 db Cpyright 2018 PCI-SIG - All Rights Reserved 7

8 Click Frm t Factrs edit Master fr PCI title Express style BGA M.2 U.2 2.5in CEM Add-in-card (aka SFF-8639) 16x20 mm ideal fr small and thin platfrms 42, 80, and 110mm lengths, smallest ftprint f PCI Express (PCIe ) cnnectr frm factrs, use fr bt r fr max strage density 2.5in makes up the majrity f SSDs sld tday because f ease f deplyment, htplug, serviceability, and small frm factr Single-Prt x4 r Dual-Prt x2 Add-in-card (AIC) has maximum system cmpatibility with existing servers and mst reliable cmpliance prgram. Higher pwer envelpe, and ptins fr height and length Surce: Intel Crpratin Cpyright 2018 PCI-SIG - All Rights Reserved 8

9 SRIS (Separate Refclk Independent SSC Architecture) Click t edit Master title style Challenge: PCIe specificatin did nt supprt independent clck with SSC SATA* cable ~ $.50 PCIe cables include reference clck > $1 fr equivalent cable PCIe base specificatin 3.0 ECNs apprved Requires use f larger elasticity buffer Requires mre frequent insertin f SKIP rdered set Requires receiver changes (CDR) Secnd ECN updates Mdel CDRs SRIS will create a number f new frm factr pprtunities fr PCIe OCuLink* Lwer cst external/internal cabled PCIe Next-generatin f PCI-SIG cable specificatin Cpyright 2018 PCI-SIG - All Rights Reserved 9

10 Click RAS Features t edit Master title style PCIe architecture supprts very high-level set f Reliability, Availability, Serviceability (RAS) features All transactins prtected by CRC-32 and Link level Retry, cvering even drpped packets Transactin level time-ut supprt (hierarchical) Well defined algrithm fr different errr scenaris Advanced Errr Reprting mechanism Supprt fr degraded link width / lwer speed Supprt fr ht-plug Cpyright 2018 PCI-SIG - All Rights Reserved 10

11 NVM Express TM Driving PCIe SSDs in Data Center Click t edit Master title style Surce: Frward Insights Q1 15 Cpyright 2018 PCI-SIG - All Rights Reserved

12 Click PCI Express t edit Master 5.0 Specificatin title style PCI Express 5.0 Specificatin 32GT/S NRZ: Applicatins such as artificial intelligence, machine learning, gaming, visual cmputing, strage and netwrking High-end netwrking slutins (i.e. 400Gb Ethernet and dual 200Gb/s InfiniBand slutins) Acceleratr and GPU attachments fr high-bandwidth slutins Cnstricted frm factr applicatins that cannt increase width and need higher frequency t achieve perfrmance Cntinued use f L1 Sub-states t cnstrain pwer cnsumptin during transmissin idle perids Cpyright 2018 PCI-SIG - All Rights Reserved 12

13 Click Ethernet t edit Evlutin Master title style Cpyright 2018 PCI-SIG - All Rights Reserved 13

14 Click GPUs t and edit PCIe Master Bandwidth title style Open Cmpute Prject s Olympus Hyperscale GPU Acceleratr chassis Flexible PCIe tplgy GPGPU-t-Hst via high-bw PCIe links Peer-t-peer withut Hst interactin GPGPU peer-t-peer via NVLink GPGPU peer-t-peer t IB NICs via x16 PCIe Surce: Open Cmpute Prject Cpyright 2018 PCI-SIG - All Rights Reserved

15 Click PCIe t 5.0: edit Near Master Future title style Timeline fr PCIe 5.0 specificatin by 1H/2019 Changes limited t primarily speed upgrade Prtcl already supprts higher speed via extended tags and credits Existing PHYs in the industry already run at 28GHz / 56GHz Specificatin prcess enhanced t accelerate develpment PCIe 5.0 versin 0.5 released Q Max pad t pad lss target is expected t be arund 35 db Fcus n cnnectr studies Pre-encding t reduce DFE burst errrs SRIS ptentially mandatry EIEOS definitin at 32 GT/s change t sequences f 32 nes and zers PCIe 5.0 versin 0.7 target release April 2018 Cpyright 2018 PCI-SIG - All Rights Reserved 15

16 Click PCIe t 5.0 edit Delivering Master title 32GT/s style Supprts 400Gb Ethernet Slutins 400Gb = 50GB 50GB in bth directins Full duplex 128/130 bit encding with 1.5% verhead x16 ~64GB/s sufficient t supprt 400Gb Ethernet slutins (64GB > 50 GB) Ttal Full Duplex = ~128GB CEM cnnectr targeted t be backwards cmpatible fr add-in cards Targeted Release in 1H 2019 RAW BIT RATE LINK BW BW/ LANE/WAY TOTAL BW X16 PCIe 1.x 2.5GT/s 2Gb/s 250MB/s 8GB/s PCIe 2.x 5.0GT/s 4Gb/s 500MB/s 16GB/s PCIe 3.x 8.0GT/s 8Gb/s ~1GB/s ~32GB/s PCIe GT/s 16Gb/s ~2GB/s ~64GB/s PCIe GT/s 32Gb/s ~4GB/s ~128GB/s Cpyright 2018 PCI-SIG - All Rights Reserved 16

17 Click PCI-SIG t edit Histry Master title style Cpyright 2018 PCI-SIG - All Rights Reserved 17

18 Click Summary t edit Master title style PCIe technlgy cntinues t evlve t exceed industry bandwidth requirements PCIe 5.0 with 32GT/s ideal fr artificial intelligence, machine learning, gaming, visual cmputing, strage and netwrking Grwing need fr increased bandwidths in GPUs attachments and acceleratrs Cpyright 2018 PCI-SIG - All Rights Reserved 18

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