PCIe Compliance Updates

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Click t edit Master title style PCIe Cmpliance Updates Richard

2 Click Disclaimer t edit Master title style The infrmatin in this presentatin refers t specificatins still in the develpment prcess. This presentatin reflects the current thinking f varius PCI-SIG wrkgrups, but all material is subject t change befre the specificatins are released. PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 2

4 Click PCI Express t edit Master 4.0 Time title Frame style Test Specificatins Cnfig Test Specificatin Rev 0.3 Wrk Grup Apprved Link/Transactin Test Specificatin Rev 0.3 Wrk Grup Apprved System Firmware (BIOS) Test Specificatin Rev 0.3 Wrk Grup Apprved Electrical Test Specificatin Rev 0.3 Wrk Grup Apprved Retimer Test Specificatin 0.3 Wrk Grup Apprved Integratr's List Pre-FYI testing was dne in April and will cntinue until fficial FYI status is reached FYI testing targeting late 2017 Official testing targeting middle 2018 PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 4

6 PCIe 4.0 Electrical Tests Under Develpment Click t edit Master title style Tx signal quality test at 16GT/s End f channel eye diagram Tx preset equalizatin test at 16GT/s Preset 0 Preset GT/s receiver test Stressed eye receiver lpback test Link equalizatin handshaking at 16GT/s Tx starts with crrect preset requested thrugh prtcl Tx respnds t prtcl changes and adjusts Rx crrectly adjusts the link Tx and perates with a stressed eye All 2.5/5.0/8.0GT/s Testing Still Required fr 4.0 Integratrs List fr a 16GT/s Capable Device PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 6

7 PCIe 4.0 (Add-in Card) Tx Signal Quality Test at 16 GT/s Click t edit Master title style Real Time Scpe (5dB package) DUT Nminal 1.0 db cable t scpe 0.7 db PCIe Cnnectr Add in Card CBB Variable ISI Bard (including cable) Nminal 10.3 db trace 3.0 db (3.0 ) CBB Tx trace PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 7

8 PCIe 4.0 (Add-in Card) Tx Signal Quality Test at 16 GT/s Click t edit Master title style Channel Setup Add-in Card plugs int CBB -> Variable ISI Bard -> Scpe 20dB at 8GHz f additinal lss (including package embedding) Pwer n CBB Scpe bandwidth is 25GHz 5dB package mdel embedded n scpe Tggle DUT t transmit 16GT/s Cmpliance Pattern 1ms pulse f 100MHz clck signal int Rx Lane0 Capture 2.0M UI wavefrm fr every Tx EQ Preset Wavefrms pst prcessed using SigTest Time Dmain CDR algrithm used t recver clck Behaviral Rx Equalizatin applied Eye width & Eye E-12 Each lane must pass SigTest analysis fr at least ne Tx EQ Preset EW > 0.3UI (with TBD adjustment due t lack f crss-talk, etc. in test fixtures) EH > 15mV (with TBD adjustment due t lack f crss-talk, etc. in test fixtures) PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 8

9 PCIe 4.0 (System) Tx Signal Quality Test at 16 GT/s Click t edit Master title style CLB Nminal 1.0 db cable t scpe Real Time Scpe (3dB package) 2.0 db (2.0 ) CLB Tx trace Variable ISI Bard (including cable) Nminal 2.0 db trace System DUT PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 9

10 PCIe 4.0 (System) Tx Signal Quality Test at 16 GT/s Click t edit Master title style Channel Setup CLB plugs int system -> Variable ISI Bard -> Scpe 8dB at 8GHz f additinal lss (including package embedding) Pwer n System Scpe bandwidth = 25GHz 3dB package mdel embedded n scpe Tggle DUT t transmit 16GT/s Cmpliance Pattern 1ms pulse f 100MHz clck signal int Rx Lane0 Capture 2.0M UI wavefrm fr every Tx EQ Preset Wavefrms pst prcessed using SigTest Ref clck captured with data wavefrm and used fr clck recvery Behaviral Rx Equalizatin applied Eye width & Eye E-12 Each lane must pass SigTest analysis fr at least ne Tx EQ Preset EW > 0.3UI (with TBD adjustment due t lack f crss-talk, etc. in test fixtures) EH > 15mV (with TBD adjustment due t lack f crss-talk, etc. in test fixtures) PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 10

11 PCIe 4.0 (Add-in Card) Rx Stressed Eye Calibratin at 16GT/s Click t edit Master title style CLB CLB Variable ISI Bard (including cable) Nminal 2.0 db trace Nminal 1.0 db cables t scpe Real Time Scpe (3dB package) 0.7 db cnnectr 2.0 db CLB Tx trace matched acrss all lanes Nminal 1.0 db cable frm signal generatr BERT Scpe CBB 3.0 db CBB Rx trace matched acrss all lanes Variable ISI Bard (including cable) Nminal db trace PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 11

12 PCIe 4.0 (Add-in Card) Rx Stressed Eye Calibratin at 16GT/s Click t edit Master title style Calibrate Swing & Tx EQ Presets Setup - SMA cable frm BERT t Scpe Swing calibrated t 800mV differential Calibrate vltage levels fr Preset 0-9 Calibrate Rj & Sj Setup - SMA cable frm BERT t Scpe Rj 1ps RMS (clck pattern used) Sj 0.1UI (16GT/s cmpliance pattern used) Channel Setup BERT -> Variable ISI -> CBB -> CLB -> Variable ISI -> Scpe 27 30dB at 8GHz f additinal lss (including 3dB package embedding) Calibrate DMI & CMI DMI 14mV (End f 27dB Channel) CMI 150mV (End f 27dB Channel) Channel Selectin Increase channel lss frm 27 t 30dB Find channel where the eye width/height is clsest t target withut drpping belw Must use Optimal Tx EQ Preset which is the Preset which gives the largest eye area Eye Width & Eye Height Calibratin Optimal Tx EQ Preset is used with final channel Adjust Sj, DMI, & Swing until eye width/height (measured with SigTest) targets are achieved EW = /- 0.5ps EH = 15mV +/-1.5mV PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 12

13 PCIe 4.0 (Add-in Card) Rx Stressed Eye Test at 16GT/s Click t edit Master title style Nminal 1.0 db cable t errr detectr 0.2 db SMP t 2.92 mm Adapter Add-in Card DUT 0.7 db cnnectr 3.0 db CBB Rx trace matched acrss all lanes Nminal 1.0 db cable frm signal generatr 3.0 db CBB Tx trace matched acrss all lanes CBB Variable ISI Bard (including cable) Nminal 15.3 db trace PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 13

14 PCIe 4.0 (System) Rx Stressed Eye Calibratin at 16GT/s Click t edit Master title style BERT Scpe Variable ISI Bard (including cable) Nminal 3.0 db trace CLB Nminal 1.0 db cable t scpe 4.0 db CLB Rx trace matched acrss all lanes 0.7 db cnnectr Real Time Scpe (5dB package) Variable ISI Bard (including cable) Nminal 10.3 db trace 3.0 db CBB Tx trace matched acrss all lanes CBB PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 14

15 PCIe 4.0 (System) Rx Stressed Eye Calibratin at 16GT/s Click t edit Master title style Calibrate Swing & Tx EQ Presets Setup - SMA cable frm BERT t Scpe Swing calibrated t 800mV differential Calibrate vltage levels fr Preset 0-9 Calibrate Rj & Sj Setup - SMA cable frm BERT t Scpe Rj 1ps RMS (clck pattern used) Sj 0.1UI (16GT/s cmpliance pattern used) Channel Setup BERT -> Variable ISI -> CLB -> CBB -> Variable ISI -> Scpe 27 30dB at 8GHz f additinal lss (including 5dB package embedding) Calibrate DMI & CMI DMI 14mV (End f 27dB Channel) CMI 150mV (End f 27dB Channel) Channel Selectin Increase channel lss frm 27 t 30dB Find channel where the eye width/height is clsest t target withut drpping belw Must use Optimal Tx EQ Preset which is the Preset which gives the largest eye area Eye Width & Eye Height Calibratin Optimal Tx EQ Preset is used with final channel Adjust Sj, DMI, & Swing until eye width/height (measured with SigTest) targets are achieved EW = /- 0.5ps EH = 15mV +/-1.5mV PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 15

16 PCIe 4.0 (System) Rx Stressed Eye Test at 16GT/s Click t edit Master title style Nminal 1.0 db cable frm signal generatr CLB 0.2 db SMP t 2.92 mm Adapter Nminal 1.0 db cable t errr detectr Variable ISI Bard (including cable) Nminal 3.0 db trace 4.0 db CLB Rx trace matched acrss all lanes 2.0 db System Tx trace matched acrss all lanes DUT System PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 16

17 Click Link Equalizatin t edit Master Tests title style Tests Required fr 8GT/s & 16GT/s Requires prtcl-aware test equipment LeCry PERT used Keysight BERT recently apprved thrugh SEG Tx link equalizatin respnse test Use prtcl-aware test equipment t request a Tx equalizatin change Check that the DUT respnds and sets its Tx t the crrect preset within required time perid Measurement f DUT Tx dne by ging t lpback and sending cmpliance pattern D this check fr all presets Rx link equalizatin Calibratin the same as standard Rx test Start with a nn-ptimal Tx equalizatin setting (P7 r P8) Allw DUT t request fr equalizatin adjustments Place DUT int lpback Mnitr bit stream fr errrs PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 17

18 Cmpliance Prgram Overview Click t edit Master title style PCIe 4.0 Test Prgram Under Develpment PCIe 3.0 Integratrs List testing (started April 2013) Tests fr 2.5, 5, 8 GT/s maximum data rates Card Electrmechanical (CEM) frm factr nly FYI testing underway fr SFF-8639/U.2 Devices can get n Integratr s List if tested separately as CEM w/adapter M.2 (Scket 3) under develpment PCI, PCI-X, PCIe 1.x retired as f Jan 1, 2013 PCIe 2.0 testing cntinues until 4.0 fficially cmmences 2.5 and 5 GT/s testing will cntinue as part f 3.0/4.0 prcess PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 18

19 PCIe 3.0 Cmpliance Prcess Click t edit Master title style Wrkshps PCI-SIG Specs PCI-SIG Specs Describes Device Requirements 3.0 Base and CEM specs C&I Test Spec C&I Test Specs Define Test Criteria based n spec requirements Test Definitins Pass/Fail Criteria Test Tls And Prcedures Test H/W & S/W Validates Test Criteria Cmpliance Interperability Predictable path t design cmpliance Same prcess as 1.x, 2.x PASS FAIL Clear Test Output Maps Directly t Test Spec PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 19

20 PCIe 3.0 Cmpliance Test Overview Click t edit Master title style Physical Layer 3.0 CLB and CBB fixtures Add receiver and link equalizatin testing New Sigtest Reference CTLE+DFE Test Channel Embedding New Clck Tl Prvides clck phase jitter test t 3.0 base specificatin PLL Bandwidth Cnfiguratin Space Updated PCIeCV fr new fields and capabilities Link & Transactin Layer Run existing 2.0 tests at 8GT/s fr 3.0 8GT/s capable devices New tests cvering link equalizatin and ther new features Platfrm Cnfiguratin Run existing tests at 8GT/s New tests fr Test Specs Available PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 20

21 Cmpliance Wrkshp: Overview Click t edit Master title style Usually annunced 2 mnths in advance Registratin clses 3 weeks prir fr dmestic, and 4 weeks prir fr internatinal N n-site registratin!!!! Testing is dne using the standard CEM frm factr Others under develpment Passing at a wrkshp is the nly way t be listed n the PCI-SIG Integratrs List Pass all gld suite tests Pass interperability testing PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 21

22 Cmpliance Wrkshp: Interperability Testing Click t edit Master title style Systems get rms Add-in cards travel rm t rm Switches run bth paths Gal: demnstrate interperability between prducts 80% passing rate required fr eligibility fr PCI-SIG Integratrs List Demnstrate that the link can train and perate at the highest cmmn link speed supprted PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 22

PCIe 3.0 Required Electrical Tests Click t edit Master title style Tx signal quality test at all supprted link speeds (similar t 2.0 prcedure) PLL bandwidth 5.

24 PCIe 3.0 Required Electrical Tests Click t edit Master title style Tx signal quality test at all supprted link speeds (similar t 2.0 prcedure) PLL bandwidth 5.0GT/s selectable de-emphasis test Tx preset equalizatin test 8.0GT/s receiver test Link equalizatin handshaking Required Tx adjustments Requesting link partner t adjust if needed Detailed test equipment specific test prcedures fr Tx and Rx testing available at PCI-SIG website PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 24

26 Click PCIe t Prtcl edit Master Testing title style DUT Transactin Layer Link Layer Physical Layer Test Cntrl sftware running n platfrm r Device Under Test (DUT) initiates test traffic Prtcl Test Card FPGA USB RAM PGM PTC mnitrs and acts n that traffic Checking prtcl Injecting errrs PCI Express PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 26

0 PTC used 3.0 - Agilent 3.0 PTC r LeCry 3.

27 Click PCI Express t edit Master PTCstitle style x16 mechanically, x1 electrically Agilent r LeCry 2.0 PTC used Agilent 3.0 PTC r LeCry 3.0 PTC used PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 27

28 PCIe Link / Transactin Cmpliance Tests Click t edit Master title style Described in Link Layer Test Spec and Transactin Layer Test Spec Merged test spec fr 3.0 Speed requirement Must be run at highest supprted link speed Tests (frm 1.x) Reserved fields Device ignres them NAK respnse Device will resend after receiving NAK Replay Timers Device will resend packet if n respnse Replay Cunt Device will resend multiple times when n respnse Link Retrain Device will retrain if cntinued n respnse Replay TLP rder Device replays TLPs in prper rder Bad CRC Device detects, drps, and lgs (DLLPs & TLPs) Undefined packet Device ignres Bad Sequence Number Device detects, drps, and lgs Duplicate TLP Device returns data nce Request Cmpletin Issue UR fr cnfig requests nt supprted PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 28

29 Test Name Click PCIe t 3.0 edit Prtcl Master Tests title style Descriptin 5GT/s selectable de-emphasis testing FYI fr 2.0, required fr 3.0 Link Equalizatin Prtcl Lpback (infrmative, implemented) Functin Level Reset Latency Tlerance Requests Verifies DUT respnds t Tx EQ adjustment requests Enables receiver electrical testing Only fr endpints that supprt FLR Check that upstream prt sends prperly frmed LTR requests Link Partner Enters/Exists Cmpliance Mde (infrmative) SKP Prcessing (infrmative) L1 fr D3 state ECRC Reserved Bit Test Verify the DUT attempts link training Verify DUT can prcess a variety f SKPs Verifies DUT requests L1 entry when it ges t D3 Generates crrect ECRC Extensin f 2.0 test fr 3.0, add reserved bit mnitring PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 29

31 Platfrm Click t edit BIOS Master Testing title style Prtcl Test Card Can Represent Any Hierarchical Multi-Device Tplgy Device Decdes All Type 0 and Type 1 Cnfiguratin Cycles All BIOS testing run using 3.0 PTC at wrkshps PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 31

32 Click PCIe t BIOS edit Test Master title style Multiple Functins per device Different BAR cmbinatins I/O, Mem, 64bit Varius size requests Prefetchable, nn-prefetchable Bridges With Resurce Requests ASPM Cnfiguratins Optin ROMs Varying sizes Different fr each device functin Shrinkable, remvable Cmplex Multiple Switch and Bridge Tplgies 2.0 updates: Use 3.0 PTC N functinal changes since 1.1 Run at 5.0GT/s as FYI PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 32

33 Click 3.0 BIOS t edit Tests Master title style New capabilities present in devices (ACS, IOV, etc ) Max paylad size All functins f a multi-functin device are set t the same max paylad size Cmmn clck test Cmmn clck cnfig bit shuld be set t the same n bth sides f the link Slt Pwer Test Cnfigure x16 slts with >25W ASPM ptinality (new fr 3.0) Only enable ASPM (L0s r L1) if bth sides supprt it VC mapping TC mapped t nly ne VC Clck pwer management Shuld nt be enabled n CEM frm factr Review the test spec fr details! Full PCIe 3.0 Bis Tests Available at Wrkshps PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 33

Cnfiguratin Tests Diagram Click t edit Master title style System

RAM PGM Add in Card Test Add In Card Under Test FPGA USB RAM PGM +

35 Cnfiguratin Tests Diagram Click t edit Master title style System Test (YI nly) System Under Test + Any Cmpliant Add In Card FPGA USB RAM PGM Add in Card Test Add In Card Under Test FPGA USB RAM PGM + Any Cmpliant System Cmmercially available gld system used fr 2.0 and 3.0 testing Cpyright 2015, PCI-SIG, All Rights Reserved PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 35

36 Click PCIECV t edit 2.0 Master Link Speed title style Test Gld System 5GT/s capable, 2.0 spec cmpliant system used fr testing add-in cards Set target link speed t limit maximum link speed and then write retrain link bit. Disable autnmus width r bandwidth changes n bth cmpnents Upstream 2.5 Dwnstream 5.0 Result 2.5 Upstream 5.0 Dwnstream 5.0 Result 5.0 Test criteria Autnmus Bandwidth Status must never be set Cnfig registers must never be reset Actual link speed matches expected link speed PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 36

0 spec requires x4 and x8 t be supprted as

0 Cnfig test spec Testing nly static link width

with standard x16 slt Insert in riser card, and

37 PCIECV Click t edit 2.0 Master Link Width title style Test CEM 2.0 spec requires x4 and x8 t be supprted as intermediate widths Specified in 2.0 Cnfig test spec Testing nly static link width supprt Use lw cst mechanical adaptrs t d all testing with standard x16 slt Insert in riser card, and check that the link cmes up in the crrect link width PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 37

38 Click PCI Express t edit Master 3.0 Cnfig title style Tests PCIECV 3.0 update released 2.1 spec updates E.g. ARI, DPA, Resizable BAR, Multi-cast, LTR, TPH extended capabilities Run tests at 8GT/s 3.0 cnfig space updates Secndary PCI Express extended capability IOV Capabilities E.g. ATS Extended Cap, SR-IOV extended cap PCIECV update released Review the test spec fr details! Full PCIECV 3.0 versin available at wrkshps PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 38

39 Click t edit Master title style Thank yu fr attending the PCI-SIG Develpers Cnference Israel Fr mre infrmatin please g t PCI-SIG Develpers Cnference 2017 Cpyright 2017 PCI-SIG - All Rights Reserved 39