PCI Express : What s Next for Flash Storage

Transcription

1 PCI Express : What s Next fr Flash Strage Justin Wenck Senir Technical Marketing Engineer Flash Memry Summit 2018 Santa Clara, CA 1

2 PCI-SIG Snapsht Organizatin that defines the PCI Express (PCIe ) I/O bus specificatins and related frm factrs member cmpanies lcated wrldwide PCI-SIG cntinues its slid reputatin f delivering lw cst, high-perfrmance, lwpwer specificatins t supprt cmpliance and interperability acrss multiple applicatins and markets. BOARD OF DIRECTORS Australia Austria Belgium Brazil Bulgaria Canada China Czech Republic Denmark Finland France Germany Hng Kng Hungary India Ireland Israel Italy Japan Malaysia Nrway Russia Singapre Slvak Republic Suth Krea Sri Lanka Sweden Switzerland Taiwan The Netherlands Turkey United Kingdm United States Flash Memry Summit 2018 Santa Clara, CA 2

3 PCI-SIG Cntinues t Increase Bandwidth Flash Memry Summit 2018 Santa Clara, CA 3

4 PCIe SSDs fr Strage PCI Express is a great interface fr SSDs Stunning perfrmance 1GB/s per lane (PCIe 3.0 x1) Lane scalability 4GB/s per device (PCIe 3.0 x4) r mre Lwer latency Platfrm + Adapter: 10 µsec dwn t 3 µsec Lwer pwer N external SAS IOC saves 7-10 W Lwer cst N external SAS IOC saves $ CPU-integrated PCIe lanes Up t 128 PCIe 3.0 With Next Gen NVM, the NVM is n lnger the bttleneck Surce: FMS 2013 NVMe Express Overview & Ecsystem Update Flash Memry Summit 2018 Santa Clara, CA 4

5 Grwth f PCIe Technlgy in Strage Data explsin is driving SSD adptin SSD market CAGR f 14.8% during Surce: IDC PCIe SSD market t surpass a CAGR f 33% during Surce: Technavi PCIe technlgy is utpacing ther intercnnect technlgies in bth units and bandwidth/ capacity Units Petabytes 100% 100% 50% 50% 0% % PCIe Other PCIe Other Surce: SSD Insights Q1/18, Frward Insights Flash Memry Summit 2018 Santa Clara, CA 5

6 PCIe: Pwer Efficient Perfrmance Scalable Perfrmance Width scaling: x1, x2, x4, x8, x12, x16, Frequency scaling: Five generatins 2.5 and 5 GT/s with 8b/10b encding 8 and 32 GT/s with 128b/130b encding Lw Pwer (Active/Idle) Rich set f Link and Device States L0s, L1, L1-substates, L2/L3 D0, D1, D2, D3_ht/cld Platfrm-level pwer ptimizatin hks: Dynamic Pwer Allcatin, Optimized Buffer, Flush Fill, Latency Tlerance Reprting Active pwer 5pJ/b, Standby pwer: 10uW/Lane Vibrant ecsystem with IP Prviders Flash Memry Summit 2018 Santa Clara, CA 6

7 It s Nt All Abut $/GB Ttal Cst f Ownership (TCO) Matters TCO Savings Over 5 Years fr Equal Write Perfrmance Capture 60 Uncmpressed UHD-1 4K (10-b) RGB SATA- Intel S3520 PCIe 3.0 Intel P4510 PCIe 4.0 FutureNVM* TCO Savings - $38,461 $45,569 Ttal Drives Sequential Read/Write (MB/s) / / % / +0% / % / +1% Pwer Reductin - -~ 10% ~ 35% Ttal Usable Capacity 144,000 GB 114,000 GB 8,625 GB Surce: *Hypthetical PCIe 4.0 Future NVM SSD: 375GB, $ , 5000MB/s Seq Wr. 6Watts Idle, 25Watts Full Lad, 0.44%AFR Flash Memry Summit 2018 Santa Clara, CA 7

8 Range f Frm Factrs Current PCIE Frm Factrs Pwer (W) EDSFF family Lw Pwer NVMe M.2 80mm and 110mm U.2 2.5in x 7mm Server Perfrmance NVMe Lw prfile HHHL x4 AIC U.2 2.5in x 15mm Lw Server Perfrmance NVMe Lw prfile HHHL x8 AIC High EDSFF 1U Shrt Flash Memry Summit 2018 Santa Clara, CA EDSFF 1U Lng x4, x8 (ruler) EDSFF 1U Lng 18mm heatsink 8

9 PCIe in Strage Perfrmance and user benefits fr current and future strage applicatins Faster data transfer: PCI Express 3.0 Specificatin (8GT/s) published in 2010 Lw pwer with high perfrmance Wide breadth f slutins available frm numerus vendrs Prvides the cst effective perfrmance required fr strage tday PCI Express 4.0 Specificatin (16GT/s) finalized and published in Octber 2017 Numerus vendrs cnfirmed with 16GT/s PHYs in silicn Majr IP vendrs ffering 16GT/s cntrllers PCI Express 5.0 (32GT/s) Specificatin targeted fr release in Q Prtcl already supprts higher speed via extended tags and credits and additinal changes target speed transitin Existing PHYs in the industry already run at 28GT/s / 56GT/s Better user experience: Client and enterprise strage applicatins using PCIe technlgy helps keep data clser t CPU Flash Memry Summit 2018 Santa Clara, CA 9

10 Required BW fr Uncmpressed Vide Surce: T. Cughlin, "Hw Big Are Yur Dreams? Gauging the Size f Future Cntent [The Art f Strage]," in IEEE Cnsumer Electrnics Magazine, vl. 6, n. 2, pp , April Flash Memry Summit 2018 Santa Clara, CA 10

11 PCI-SIG and SDA Liaisn PCI-SIG and the SD Assciatin have frmed a liaisn t advance SD Express as a cmpnent in the PCIe ecsystem Cllabrate n a technical interchange related t SD Express and SD Express Test Guidelines, as well as infrmatin related t PCIe electrical certificatin f SD Express prducts Frm the PCI-SDA Advisry Team and the SD-PCIe Technical Grup whse members are frm cmpanies that belng t bth the SDA and PCI-SIG New SD Express Card leverages PCIe 3.0 interface t deliver up t 985 MB/s transfer rate Maintains backward cmpatibility with existing SD hsts in the market Meets changing perfrmance levels f mbile and client cmputing, imaging, gaming, IT and autmtive applicatins Flash Memry Summit 2018 Santa Clara, CA 11

12 Summary PCIe 3.0 prvides the cst effective perfrmance required fr strage tday Will cntinue t utpace ther SSD strage intercnnect technlgies in bth units and bandwidth/capacity PCIe 4.0 (16GT/s) and 5.0 (32GT/s) will cntinue t deliver perfrmance and key features Enabling emerging NVM Flash Memry Summit 2018 Santa Clara, CA 12

13 Back-up Slides Flash Memry Summit 2018 Santa Clara, CA 13

14 PCI Express 4.0 and 5.0 PCI Express 4.0 Specificatin (16GT/s) finalized and published in Octber 2017 Numerus vendrs cnfirmed with 16GT/s PHYs in silicn Majr IP vendrs ffering 16GT/s cntrllers PCI Express 5.0 Specificatin targeted fr release in Q Changes targeted t primarily speed upgrade Prtcl already supprts higher speed via extended tags and credits Existing PHYs in the industry already run at 28GHz / 56GHz PCI Express 5.0 Specificatin (32GT/s) ideal fr: Applicatins such as artificial intelligence, machine learning, gaming, visual cmputing, strage and netwrking High-end netwrking slutins (i.e. 400Gb Ethernet and dual 200Gb/s InfiniBand slutins) Acceleratr and GPU attachments fr high-bandwidth slutins Cnstricted frm factr applicatins that cannt increase width and need higher frequency t achieve perfrmance Cntinued use f L1 Sub-states t cnstrain pwer cnsumptin during transmissin idle perids RAW BIT RATE LINK BW BW/ LANE/WAY TOTAL BW X16 PCIe 1.x 2.5GT/s 2Gb/s 250MB/s 8GB/s PCIe 2.x 5.0GT/s 4Gb/s 500MB/s 16GB/s PCIe 3.x 8.0GT/s 8Gb/s ~1GB/s ~32GB/s PCIe GT/s 16Gb/s ~2GB/s ~64GB/s PCIe GT/s 32Gb/s ~4GB/s ~128GB/s Flash Memry Summit 2018 Santa Clara, CA 14

15 Ethernet Evlutin Flash Memry Summit 2018 Santa Clara, CA 15

16 Cmpressed Streams Hulu Quality Internet Rate (Mbps) MB/s # SATA Streams # SAS Streams PCIe 3.0 x4 Streams PCIe 4.0 x4 Streams PCIe 5.0 x4 Streams SD p HD p HD k Ultra HD k Estimate Flash Memry Summit 2018 Santa Clara, CA 16