Applications embedding 16MB Phase

Transcription

1 Truly Innovative 28nm FDSOI Technology for Automotive Microcontroller Applications embedding 16MB Phase Change Memory F.ARNAUD 1, P.ZULIANI 2, J.P.REYNARD 1, A. GANDOLFO 2, F.DISEGNI 2, P.MATTAVELLI 2, E.GOMIERO 2, G.SAMANNI 2, C.JAHAN 3, R.BERTHELON 1, O.WEBER 3, E.RICHARD 1, V.BARRAL 3, A.VILLARET 1, S.KOHLER 1, J.C.GRENIER 1, R.RANICA 1, C.GALLON 1, A.SOUHAITE 3, D.RISTOIU 1, L.FAVENNEC 1, V.CAUBET 1, S.DELMEDICO 1, N.CHERAULT 1, R.BENEYTON 1, S.CHOUTEAU 1, P.O.SASSOULAS 1, A.VERNHET 1, Y.LE FRIEC 1, F.DOMENGIE 1, L.SCOTTI 2, D.PACELLI 2, J.L.OGIER 1, F.BOUCARD 1, S.LAGRASTA 1, D.BENOIT 1, L.CLEMENT 1, P.BOIVIN 4, P.FERREIRA 1, R.ANNUNZIATA 2, P.CAPPELLETTI 2 1 STMICROELECTRONICS, 3 CEA-LETI, 850 rue Jean Monnet Crolles, France 2 STMICROELECTRONICS via Camillo Olivetti 2, Agrate Brianza, Italy 4 STMICROELECTRONICS, zone industrielle, 190 avenue Coq, Rousset, France

2 Outline of Presentation Introduction Technology description CMOS devices suite PCM analytical cell 16MB PCM array results Conclusions IEDM conference, Dec , San-Francisco, CA 2

3 Outline of Presentation Introduction Technology description CMOS devices suite PCM analytical cell 16MB PCM array results Conclusions IEDM conference, Dec , San-Francisco, CA 3

4 Automotive Microcontrollers Microcontroller Market +4,8% CAGR 4.1 B$ *Source: Strategy Analytics 5.7 B$ Body 600 M$ Powertrain, Chassis & Safety 2.3 B$ Electrification 650 M$ Gateway 740 M$ ADAS MCU 1.4 B$ Automotive MCU growth contributors: Advanced Powertrain: combining Electric Motors, Thermal Engine and Transmission management Electrification: smart power supporting electrification Gateways: Secure communication interfaces ADAS: safety microcontrollers envm trend: increase memory size due to: - increased software complexity - multiple firmware image storage IEDM conference, Dec , San-Francisco, CA 4

5 Microcontroller Chips for Automotive envm PMU Real MCU layout for automotive IEDM conference, Dec , San-Francisco, CA Analog LOGIC I/Os 5

6 Physical Mechanisms for envm Charges manipulation Atoms manipulation Spin manipulation GeSbTe phase diagram HRS LRS ESF3 structure from SST Y-H Lin et al, Excellent high T retention of In NOxNy ReRAM by interfacial layer engineering VLSI-TSA, 2018 T. Kawahara et al, Spin transfer torque RAM technology Mircoelectron Reliability, 2012 eflash PCRAM Ox.RAM STT MRAM IEDM conference, Dec , San-Francisco, CA 6

7 Phase Change Memory Principle Crystalline phase from SET (1) state to RESET (0) state Amorphous phase from RESET (0) state to SET (1) state Crystalline phase current current time time IEDM conference, Dec , San-Francisco, CA 7

8 Outline of Presentation Introduction Technology description CMOS devices suite PCM analytical cell 16MB PCM array results Conclusions IEDM conference, Dec , San-Francisco, CA 8

9 Technology Architecture Stacked contacts in logic/sram Via in PCM array GST material heater Contact Contact Thin buried oxide Thin Si film Handle substrate PCM array Logic/SRAM area IEDM conference, Dec , San-Francisco, CA 9

10 Process Integration Sequence <100> 45 off-axis FDSOI Substrate GATE STACK (Triple GOx) CONTACT (barre & hole) THIN METAL (Trench First HM) HYBRID BRICK (Bulk & FDSOI) GATE PATTERNING (5V / 1V8 / 1V) PCM ELEMENT (heater & GST) INTERM. METAL (Trench First HM) ISOLATION (STI & well) JUNCTIONS (raised SD & I 2 ) VIA-0 (to PCM & contact) THICK METAL (xxxxx) VT ADJUST (NMOS & PMOS) SALICIDE (SiProtect & NiSi) M1 WIRES (single damascene) ALU PAD (Alu & passivation) IEDM conference, Dec , San-Francisco, CA 10

11 Co-Integrated Memories Morphology GST Shared Contact GND heater Pull-up Pull-down SL BL STI WL Buried oxide HD SRAM Cell (0,120um 2 ) PCM Cell (0,036um 2 ) IEDM conference, Dec , San-Francisco, CA 11

12 Devices Suite - Morphology 5V Transistor 0,6um Logic Transistor 28nm SRAM Transistor 36nm 140A 16A 16A BULK AREA SOI AREA SOI AREA 1,8V Transistor 0,15um PCM Selector 30nm 34A 16A SOI AREA SOI AREA IEDM conference, Dec , San-Francisco, CA 12

13 Cell in X direction Cell in Y direction PCM Element Morphology GST HEATER GST SELECTOR HEATER CONTACT IEDM conference, Dec , San-Francisco, CA 13

14 Outline of Presentation Introduction Technology description CMOS devices suite PCM analytical cell 16MB PCM array results Conclusions IEDM conference, Dec , San-Francisco, CA 14

15 Devices Table Devices Logic devices SRAM devices I/O devices VDDnom (Volt) 1 1 1,5 & 1,8 Lmin (um) 0,028 0,036 0,1 & 0,15 Tinv (nm) 1,6 1,6 3,4 VT options HVT & LVT LL & HS RVT LVT Substrate FDSOI FDSOI FDSOI Devices HV/Analog devices ESD devices VDDnom (Volt) 5 1 1,8 Lmin (um) 0,6 0,048 0,15 Tinv (nm) 14 1,6 3,4 VT options HVT RVT RVT Substrate BULK FDSOI BULK Core oxide IO oxide HV oxide IEDM conference, Dec , San-Francisco, CA 15

16 Core Oxide Transistors Well Scheme GND NMOS PMOS VDD GND NMOS PMOS GND p+ n+ p+ n+ n+ p+ p-bp n-bp p+ n+ n+ n+ p+ n+ n+ p+ p-bp n-bp p+ p+ p-well n-well n-well p-well HIGH VT option (regular well) LOW VT option (flip well) VT adjust GND NMOS PMOS GND GND NMOS PMOS GND n+ n-well n+ p+ n+ n+ p+ p-bp n-bp p-well p+ p+ Mix & match capability n+ n-well n+ p+ n+ n+ p+ p-bp n-bp p-well p+ p+ HIGH VT option (flip well) LOW VT option (flip well) IEDM conference, Dec , San-Francisco, CA 16

17 Digital Performance & Design Flexibility Gate length 100% performance enhancement 28nm Fastest Lg= 28nm 3decades reduction Reference Lg= 32nm Lg= 38nm 38nm High VT 0,9V FBB Low VT VT adjust Low leakage IEDM conference, Dec , San-Francisco, CA 17

18 5V Transistors Digital Characteristics Transfer characteristic Output characteristic V GS =5V V GS =4V V GS =3V V GS =2V 1pA/um V GS =1V PMOS NMOS PMOS NMOS IEDM conference, Dec , San-Francisco, CA 18

19 Triple Gate Oxide Devices Platform for Automotive Micro-Controllers HV Transistor PMOS IOs Transistor Logic Transistor NMOS IEDM conference, Dec , San-Francisco, CA 19

20 5V Transistor Analog Characteristics Flicker Noise NMOS Matching NMOS PMOS Matching PMOS IEDM conference, Dec , San-Francisco, CA 20

21 5V +10% 5V +10% 5V Transistor Gate Oxide Reliability PMOS NMOS 10y life time 10y life time IEDM conference, Dec , San-Francisco, CA 21

22 5V Transistor Hot Carrier Injection 10 years life time PASS VDD= 5V + 10% IEDM conference, Dec , San-Francisco, CA 22

23 Outline of Presentation Introduction Technology description CMOS devices suite PCM analytical cell 16MB PCM array results Conclusions IEDM conference, Dec , San-Francisco, CA 23

24 MOS Selector Requirements Deliver high drive current for cell programming phase (reaching GST melting point) Use optimum W/L ratio reducing the cell area (cost effective solution) Reading operation at low Voltage Mitigate leakage current (IOFF) of un-selected Word-Line and selected Bit-Line during writing and reading steps IEDM conference, Dec , San-Francisco, CA 24

25 MOS Selector Structure Storage Element Source Line Word Line Bit Line Word Line Source Line SL NMOS RBB NMOS NMOS WL BL Buried oxide PWELL = Back Bias (RBB for leakage mitigation) SL NMOS RBB IEDM conference, Dec , San-Francisco, CA 25

26 Enhanced MOS Selector with RBB Technique Area penalty Optimum IEDM conference, Dec , San-Francisco, CA 26

27 1T1R Analytical Cell Description V BL GST HEATER V WL V RBB IEDM conference, Dec , San-Francisco, CA 27

28 1T1R Analytical Cell Electrical Characteristics LRS 1 HRS 0 IEDM conference, Dec , San-Francisco, CA 28

29 Analytical Cell Endurance LRS HRS Cycling algorithm HRS trend 10Mcycles LRS trend IEDM conference, Dec , San-Francisco, CA 29

30 GST RESET Data Retention vs T N.Ciocchini et al Modeling Resistance Instabilities of SET and RESET States in Phase Change Memory with Ge-rich GeSbTe IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 6, JUNE 2014 IEDM conference, Dec , San-Francisco, CA 30

31 Outline of Presentation Introduction Technology description CMOS devices suite PCM analytical cell 16MB PCM array results Conclusions IEDM conference, Dec , San-Francisco, CA 31

32 16MB Test Chip & Array Organization Sense amps 4MB PCM array Row decoders 4MB PCM array OFF-state selectors SL 4MB PCM array 4MB PCM array I/Os PCM MOS selector On-state selector IEDM conference, Dec , San-Francisco, CA 32

33 16MB SET & RESET States Distributions 16MB statistics IEDM conference, Dec , San-Francisco, CA 33

34 16MB Test Chip Reliability Figures ENDURANCE RESET RETENTION IEDM conference, Dec , San-Francisco, CA 34

35 MCU Demo Chip Preliminary Results envm PMU MCU content & specs Core 32b processor SRAM 640KB PCM 6MB T range -40C - 165C Supply V / V Analog LOGIC I/Os Preliminary reliability tests Soldering Pass (30/30) Data retention Pass (30/30) Endurance (10K) Pass (30/30) IEDM conference, Dec , San-Francisco, CA 35

36 Outline of Presentation Introduction Technology description CMOS devices suite PCM analytical cell 16MB PCM array results Conclusions IEDM conference, Dec , San-Francisco, CA 36

37 Conclusions For the first time, Non volatile Phase Change Memory has been co-integrated with 28nm FDSOI technology for microcontroller applications in the Automotive market Triple gate oxide scheme enabling 5V transistor with FDSOI substrate for analog requirements in Automotive system Attractive leakage/drivability of FDSOI NMOS selector leveraging Reverse Body Biasing technique Fully validated 0,036um 2 PCM cell using optimized GST alloy showing robust endurance and good activation energy compatible with Automotive criteria (150 C achieved) Excellent PCM current distributions demonstrated on 16MB array before and after 150 C bake without degradation after 10k cycles IEDM conference, Dec , San-Francisco, CA 37

38 Acknowledgements Innovation proposed and developed by design, process, electrical characterization and product test teams from European ST sites (Rousset, Agrate and Crolles) using patents in PCM cell design and GST alloy optimization for automotive The authors would like to warmly thank our colleagues from CEA-LETI located in Grenoble for their strong technical expertise, PDF Solution and their constant support in deep electrical characterizations on this technology platform IEDM conference, Dec , San-Francisco, CA 38

39 Thank You for your attention! Visit us at IEDM conference, Dec , San-Francisco, CA 39