High Volume Photonics Manufacturing

Transcription

1 Common Pla)orms Common Interfaces Cost Integra3on Cost INEMI Webcast High Volume Photonics Manufacturing Bob Pfahl, Principle Investigator Lionel Kimerling, Principle Investigator Jim McElroy, Executive Director

2 Connectivity and Society Compute system performance has increased at a steady rate of 1000x/10 yr with ~constant cost for 20 yrs. The same scaling rate is needed for the next 20 years. Security, Efficiency, Convenience, Presence, Education, Culture 2

3 Migration of optics from board edge eliminates interfaces: devices, drivers and transmission lines Optical Connection Pluggable Electrical Connection Transmission Line Cage CPU Linecard/PCB OE Optronics MSA AOC Cage CPU Agilent Embedded CPU Reflex CPU Integrated Altera CPU Board Level CPU Fujitsu CTR III TWG Report, Semicon West (2013), Roe Hemenway, Photonic Controls 3

4 Pervasive Photonic Integration The number of photonic components deployed in IT systems is increasing. The contribution of photonics to system cost is becoming significant. Manufacturing cost reduction is directly related to the number of units produced. If a common manufacturing platform is shared across the industry, one can expect that cost reduction will scale with manufacturing volume. Integrated Silicon Microphotonics is today the only platform capable of high volume production (>10 million units) and high levels of integration. 4

5 Deployment of Optical Interconnection Design Rule: photonics at BxD=1Tb/s x cm Monolithic, chip-level photonic integration: solution to cost, energy bandwidth density. 5

6 MATERIALS & COMPONENTS COMPONENTS SYSTEMS NETWORKS SERVICES CONTENT PROCESS EQUIPMENT cost revenues END USERS inemi MIT 7

7 PSMC Technical Working Groups Monolithic Integration TWG Lionel Kimerling, MIT Hybrid Integration TWG Dick Otte, Promex Industries Packaging of Electronic Photonic Systems TWG Bill Bottoms, 3MTS Circuit boards, Backplanes and Connectors TWG John MacWilliams, Bishop Functions and Markets TWG Richard Grzybowski, MACOM You are invited to par.cipate: 7

8 Electronic-Photonic Systems Functionality and Architecture Functionality is the ability of a technology to perform a complete task: r IT: communication, computation, imaging r and to scale to future needs r with reducing cost, energy and footprint, latency. Architecture is evolving to distributed, self-aware topologies and convergence: r electronic-photonic r hardware-software-architecture 8

9 Function and Architecture Performance Objectives Bandwidth: as close to as possible Physical Density: as close to as possible Latency: as close to 0 as possible Power Required: as close to 0 as possible Cost: as close to 0 as possible I/O Port Count: as close to as possible 9

10 Scaling Functionality Roadblock: Assembly and Packaging Design: increased component density, constant power density, chip-to-package-to-board electronic-photonic partitioning waveguide/fiber attach fiber-to-the-user interface/architecture Manufacturing: throughput, yield, utilization known good die photonic test chip repair reliability and redundancy 10

11 Large Scale Integration History VLSI Consortium (Japan) r r Silicon wafer specification Defects: crystal growth and processing SEMATECH (US) r r ITRS r r Tool and fab standardization Software (materials, tools, scheduling, design), Yield, Throughput Function transition from DRAM to Microprocessor Consolidation to foundry structure PETRA (Japan) r r Silicon Photonics Electronic-Photonic Synergy 11

12 Commercial Entry of Silicon Photonics Board-level photonic interconnection: 2015 Interconnect Initial penetration is in HPC and Core Routers, then to Datacenters Factors of speed, energy, density come together for optical solution at board level. Time Frame Reach BW BW Density (G/cm 2 ) Energy (pj/bit) Rack ~ m G ~ à 200 Chassis ~ m G ~ à 50 Backplane ~ m G ~ à 25 Board ~ m 0.3 1T ~ à 5 Module ~ cm 1 4 T > à.1 Chip ~ cm 2-20T > à.01 PETRA: CTR III TWG Report, Semicon West (2013), Roe Hemenway, Photonic Controls 12

13 Integrated Microphotonics manufacturing and performance Scaling with a standard, modular platform: increases: yield, reliability, density reduces: cost, time to market, power, latency 13

14 Photonic System Disaggregation Computation systems have become communication-centric. Communication systems have become heterogeneous. Application efficiency optimization requires disaggregated, special purpose hardware. r modularity r retrofit updated hardware resources r PC model : commoditize components r silicon photonics focus: transceiver and switch single mode silicon photonics is future-proof 14

15 Silicon Photonics for Disaggregation In Jan. 2013, Intel announced a collaboration with Facebook on a new disaggregated, rack-scale server architecture that enables independent upgrading of compute, network and storage subsystems Mezzanine Options Optical PCIe via Intel Silicon Photonics Intel Ethernet chip and Intel Silicon Photonics Intel Atom TM Micro-server tray Mezzanine fiber Intel Xeon processor based tray The disaggregated rack architecture includes Intel s new photonic architecture, based on high-bandwidth, 100Gbps Intel Silicon Photonics Technology, that enables fewer cables, increased bandwidth, farther reach and extreme power efficiency compared to today s copper based interconnects. Source: Justin Rattner, Intel 15

16 Switching Platform Analysis Problem: communication and computation scaling r data center revolution: everything is computation r cost, capacity, energy, latency: 2x/yr = 1000x/10yrs r efficient hardware, software and architecture Constraints: supply chain coordination r change guided by an inclusive Roadmap r hardware/architecture/software convergence Switches in parallel architectures r minimize: energy, latency r maximize: utilization, capacity, interoperability, control r Dis-aggregation; Internet of Things; Virtualization 16

17 The VCSEL Array E-O-E Matrix Switch High-yield arrays of parallel VCSELs, PINs, IC s and fiber Array level IC s with integrated and shared functions Electrical connector with short electrical traces Low cost MMF Parallel fiber alignment image compliments of Finisar 17

18 Optical Path Switching IP to circuit switching for large files 10 3 reduction in cost 10 3 increase in data rate no need to match data rates congestion reduction multiple access by broadcast 18 VICTORIES Project, AIST Japan

19 Silicon Photonics for Functionality LSI Silicon Photonics Silicon Phased Arrays for LIDAR Michael Watts, MIT 26x26 Quantum Photonic Processor Dirk Englund, MIT 19 and routing, sensing, imaging,...

20 Design-Tools-Processes and COST Process-based Cost Modeling (PBCM) Objective: Map from description of technology to process cost. Purpose: Inform technical decisions BEFORE investment. Product Description Processing Requirements Resource Requirements Process Operations Financial Current Model Captures ~60 Processes Model Model Model Production Cost Operating Conditions Factor Prices Kirchain, MIT (2005)

21 Cost is Highly Volume Dependent Integration provides cost savings at high volume. Cost at Low Volume r hybrid InP/Si chip < monolithic Si photonic chip, but r hybrid backend > integrated backend due to assembly of discrete components. Summary of findings: r Low (<1.3 M units): DML VCSEL array r Medium (1.3 M~2.5 M units): Hybrid InP/Si r High (>2.5 M units): Monolithic Si r Backend (packaging and assembly) is the major factor. Kirchain, MIT

22 Cost is Lower for Larger Wafer Size 22 Kirchain, MIT

23 Manufacturing History 1980s TODAY Vertically-integrated firms. Research, development, design, production and marketing promote innovation, quality and efficiency. Core firm activities located close to lead customers and best suppliers to promote JIT & mutual learning. Core-competence firms. Massive fragmentation of production systems. Functions distributed between home societies and host societies. Networks of production chains link brands, product definition and design, contract manufacturers, assemblers, distributors, retailers. Elisabeth Reynolds, MIT Industrial Performance Center

24 Challenge: the Industrial Ecosystem When innovation grew out of large firms, resources ($ $, skills, plants) were available for scale up. Where do those resources come from today? Large employers provided skills and training. How do we educate the workforce we need? Integrated Silicon Photonics is a transformative manufacturing technology. How will it be adopted by and diffused into the firms who might use it? Elisabeth Reynolds, MIT Industrial Performance Center 17

25 Integrated Photonics Manufacturing Institute Innovation and Manufacturing Institute IP-IMI $110M US + $110M industry for 5 years r Each manufacturing innovation institute serves as a regional hub, bridging the gap between applied research and product development by bringing together companies, universities, and Federal agencies to co-invest in key technology areas that encourage investment and production in the U.S.: r education and training of students and workers at all levels, r provide the shared assets to help companies, most importantly small manufacturers, access the cuttingedge capabilities and equipment to design, test, and pilot new products and manufacturing processes. 25

26 Monolithic Silicon Microphotonics Roadmap FuncGon TxRx Matrix Switch Processor Comm/Comp/Imaging Embedded E- P hybrid 8x8 hybrid coherent Signal CondiGoning WDM 32x32 FFT Monolithic- embedded Monolithic- embedded Monolithic- embedded Cost $1/Gbps $0.1/Gbps $0.01/Gbps BW density 30 Tb/s/cm 2 Energy 10pJ/b 1pJ/b 100fJ/b Reach 1000km 100m 1cm I/O Capacity Small Commercial Demand for Technically Viable OpGcal SoluGons 40 Gbps 400Gbps 128Tbps NOW NEXT LIMITS Commercially Viable OpGcal SoluGons Deployed No Technically Viable OpGcal SoluGons Exist 26

27 A Revolution in Packaging Is Needed At the leading edge everything will change to allow high reliability SiP products meeting market needs at low cost. This requires: ü New design and simulation tools ü New materials ü New device designs and architectures ü New package architectures ü New network architectures ü New manufacturing processes

28 Photonic System Packaging Roadmap Components Package substrates Materials properges Electrical ProperGes Photonic ProperGes Into/out of package Energy/thermal Heterogeneous Integra6on by material and component Electronic- Photonic Substrates required Increase system performance Packaging is oven the limigng factor Supply chain Volume manufacturing Small Commercial Demand for Technically Viable OpGcal SoluGons Supply Chain is Key to product cost NOW NEXT LIMITS Commercially Viable OpGcal SoluGons Deployed No Technically Viable OpGcal SoluGons Exist 28

29 Summary: Scaling IT to 2050 Technology drivers r Component performance will scale with integration. r Parallelism is architectural scaling paradigm. r Virtualization is functional scaling paradigm. r All drivers will not scale at the same pace. r Programming has to keep up. Architecture/Hardware/Software must be co-designed. Vision for World Wide Data Center 2035 Internet = one interconnected data center Resources virtualized and provisioned as services 29

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31 Video Targets for Photonic Integration Data Centers, High Performance Computing IoT: sensors, imagers,... Poorest Roadmap Vision scaling: switch/router port count scaling architecture: hybrid packet/circuit networks management: high connectivity complexity control: self aware functionality The Biggest Problems to Solve Manufacturing: cost, energy, density, reliability, T-to-M Locality: control and programming 31