Lecture 13: Multi-Cycle Control Unit. Spring 2018 Jason Tang

Transcription

1 Lecture 13: Multi-Cycle Control Unit Spring 2018 Jason Tang 1

2 Topics Multi-cycle path Multi-cycle implementation Multi-cycle control 2

3 Single-Cycle path A single-cycle path has, by necessity multiple s, and also separate and instruction memories adder 4 PC addr read Instruction Memory Write ister File WEn A Sel B Sel W Sel Zero Extend ExtSel B Bus Shift Left 2 A Bus Src adder Op Clock PCSel Branch BranchType Control Unit Condition Codes MemRead addr write C Bus read Memory MemWrite MemTo 3

4 Motivation for Multi-Cycle path Whereas a single-cycle path takes 1 clock cycle to execute any instruction, design a system that requires multiple shorter cycles to execute Allow the same function unit to be used for different purposes during the path Different uses on different clock cycles Allows sharing of resources, and thus reduces hardware A single memory unit, for both instructions and A single for all arithmetic, instead of an and two adders 4

5 Designing Multi-Cycle path At end of a clock cycle, all used in subsequent clock cycle must be stored One or more registers added after every functional unit Operations are speculatively performed, and results are ignored if that operation is not needed Example: Some register number is written to BSel (and thus a value comes out of register file s B Bus), even if the fetched instruction is D-Type (and thus has no second operand) 5

6 Multi-cycle path Five classic parts to path: Fetch: Read from memory the instruction at PC Decode: Determine instruction type and read from registers Execute: Perform operation as given by instruction Memory: Load or store a value from memory Write Back: Store result in register 6

7 Partitioning path isters added between each stage Next PC ister Instruction ister PC Fetch Decode Execute Memory Operands isters Output ister Memory ister Write Back Not every stage is used for every instruction Example: An unconditional branch to a PC-relative address skips Memory and Write Back stages 7

8 Incomplete Multi-cycle path Design Instruction and memory merged into single unit Single also used to update PC PC write addr MemRead Memory read Write 32 MemWrite ister File WEn A Sel B Sel W Sel Zero Extend A Bus B Bus 4 ExtSel Shift Left 2 C Bus SrcA SrcB BranchType Op Branch Control Unit Condition Codes 8

9 Multi-cycle RTN for ldur ldur had one of the longest paths on ARMv8-A Many temporary registers added between each operation Stage ister Transfers Controls Set Fetch IR = Mem[PC]; Out = PC + 4 Decode Execute Memory Write Back PC = Out; A = X[n]; Imm9 = SignExtend(imm9) Out = A + Imm9 Memister = Mem[Out] X[t] = Memister MemRead = 1, SrcA = PC, SrcB = 4, Op = add ASel = n, PCWrite = 1 SrcA = A, SrcB = imm9, Op = add MemAddrSrc = Out, MemRead = 1 WSel = t, MemTo = MDR, Write = 1 9

10 Multi-cycle ldur Fetch Controls set: MemAddrSrc = PC (not shown), MemRead = 1, SrcA = PC, SrcB = 4, Op = add BranchType PC write addr MemRead Memory read 32 MemWrite Mem Inst Write ister File WEn A Sel B Sel W Sel Zero Extend A Bus B Bus 4 ExtSel Shift Left 2 SrcA Op SrcB Out Branch Control Unit Condition Codes 10

11 Multi-cycle ldur Decode Controls set: ASel = n BranchType PC PCWrite write addr MemRead Memory read 32 MemWrite Mem Inst Write ister File WEn A Sel B Sel W Sel Zero Extend Imm12 Imm9 Imm19 Imm26 A B 4 Shift Left 2 ExtSel SrcA SrcB Op Out Branch Control Unit Condition Codes 11

12 Multi-cycle ldur Execute Controls set: SrcA = A, SrcB = imm9, Op = add BranchType PC PCWrite write addr MemRead Memory read 32 MemWrite Mem Inst Write ister File WEn A Sel B Sel W Sel Zero Extend Imm12 Imm9 Imm19 Imm26 A B 4 Shift Left 2 ExtSel SrcA SrcB Op Out Branch Control Unit Condition Codes 12

13 Multi-cycle ldur Memory Controls set: MemAddrSrc = Out, MemRead = 1 BranchType PC PCWrite MemAddrSrc MemRead write addr read Memory 32 MemWrite Mem Inst Write ister File WEn A Sel B Sel W Sel Zero Extend Imm12 Imm9 Imm19 Imm26 A B 4 Shift Left 2 ExtSel SrcA SrcB Op Out Branch Control Unit Condition Codes 13

14 Multi-cycle ldur Write Back Controls set: WSel = t, MemTo = MDR, Write = 1 MemTo BranchType PC PCWrite MemAddrSrc MemRead write addr read Memory 32 MemWrite Mem Inst Write ister File WEn A Sel B Sel W Sel Zero Extend Imm12 Imm9 Imm19 Imm26 A B 4 Shift Left 2 ExtSel SrcA SrcB Op Out Branch Control Unit Condition Codes 14

15 Control Model States specifies control points for register transfers Transfer occurs upon exiting state (same falling edge) inputs (conditions) Next State Logic Control State Output Logic outputs (control points) 15

16 Control Specification for Multi-Cycle path IR Mem[PC] Out PC + 4 Fetch A R[n] B R[m] Imm* Extend(*) PC Out Decode Out A op B R-Type R Exec ldur ldur, stur Out A + Imm9 stur Load/Store Exec cbz Out A + 0 cbz Exec (cond is false) (cond is true) MDR Mem[Out] ldur Mem Mem[Out] B stur Mem Out PrevPC + Imm19 cbz Exec2 R[d] Out R Write R[d] MDR ldur Write PC Out cbz Write 16

17 Detailed Control Specification State Instruction Next State SrcB Control Fetch???? Decode Constant 4 R-Type R Exec X Decode ldur Load/Store Exec X stur Load/Store Exec X cbz cbz Exec X R Exec R-Type R Write B Load/Store Exec ldur stur ldur Mem stur Mem Imm9 cbz Exec cbz cbz Exec2 & Z Fetch & Z Constant 0 ldur Mem ldur ldur Write X stur Mem stur Fetch X cbz Exec2 cbz cbz Write Imm19 R Write R-Type Fetch X ldur Write ldur Fetch X cbz Write cbz Fetch X 17

18 Performance Evaluation State diagram gives CPI for each instruction Workload gives frequency of each type Instruction CPI Frequency CPI Frequency R-Type 4 40% 1.6 ldur 5 30% 1.5 stur 4 10% 0.4 cbz (taken) 5 20% 1.0 Average CPI: