Review of Rad Hard electronics activities at European Space Agency. G. Furano ESA/ESTEC - Data Systems Division, the Netherlands

Transcription

1 Review of Rad Hard electronics activities at European Space Agency G. Furano ESA/ESTEC - Data Systems Division, the Netherlands TWEPP 2012 Topical Workshop on Electronics for Particle Physics 19 September 2012 Oxford, UK

2 Outline RH Electronics at ESA Current requirements on environmental constraints and radiation (TID and SEE) for different classes of missions, some examples. ASIC vs. FPGA issue European Digital and Mixed ASIC rad hard sources DARE and DARE+ rad-hard by design libraries Development (and availability) of standard IP cores Some words about LEON-2(and 3/4) fault tolerant processor IP core and its availability outside ESA. The particular case of memories, and challenges of the sub 45nm components (and COTS components in general). Future ESA.

3 Preface How Hard is Rad Hard? Space electronics systems may have very variable requirements in terms of reliability, availability and radiation harness Example 1: Earth Observation missions are LEO, are well inside magnetosphere, possibly polar, and last 2-5 years. Accumulated dose ~ 1-5 krad/yr Dose due mostly to protons in inner belts Fail-safe operational requirements (~) Payload softer - Platform harder

4 Preface How Hard is Rad Hard? Space electronics systems may have very variable requirements in terms of reliability, availability and radiation harness Example 2: Telecom missions are geostationary, and last >15 years. Accumulated dose ~ 5-10 krad/yr Dose due to electrons (and their Bremsstrahlung) in outer belts Fail-operational requirements Some systems double-failure op Payload and Platform very hard Lifetime of a platform can be decades

5 Preface How Hard is Rad Hard? Example 3: Planetary probe on Jupiter (next ESA flagship). 10 years in interplanetary space just to get there (GCRs!) Accumulated dose ~ 100 krad/month (???) Dose due to protons and electrons in Jovian orbit Once-in-a-lifetime scientific opportunity (failure is not an option) European taxpayers politicians want it cheap

6 In context: Integrated Circuits in ESA Missions Technology: Proba V Launchers: Ariane 5, Vega Earth Observation: GOCE, Sentinel 2 Science: Venus Express, Rosetta, Bepicolombo Navigation: Galileo IOV Telecom: Immarsat 4, Hylas All ICs with number of pins larger than 40 have been recorded

7 Trends for Integrated Circuits in Space Number of ICs is increasing Number of programmable components is increasing Number of FPGAs is increasing Telecommunication and Navigation use the largest number of ICs Data were inconclusive we had to use statistics

8 Spacecraft Development Flow (simplified) Existing EEE Qualified Component Mission Requirement Spacecraft Design CUSTOMER Component Specification PRIME Spacecraft Design SUBCO Qualified Component Manufacturer Technology In Flight Monitoring Mission Spacecraft AIT Component Inspection

9 Qualified EEE Component Development (simplified manager's view) Mission Requirement Spacecraft Design Component Specification Spacecraft Design Manufacture Prototype Testing Technology In Flight Monitoring Mission Design Screening Spacecraft AIT Component Inspection Qualification

10 Qualified EEE Component Development (closer to reality) Mission Requirement Spacecraft Design Component Specification Spacecraft Design Manufacture Prototype Testing Technology In Flight Monitoring Mission Design Screening Spacecraft AIT Component Inspection Qualification

11 Reality check: why ASICs, and not FPGAs As you saw we use a LOT of FPGAs, and we're happy fine with them, but FPGAs should be forbidden in space applications until the designers learn how to design with them (Sandi, one of the best critical app FPGA designers in Europe) With a TID requirement of 100 Krad (equivalent to 15-year telecom) there s only one possible choice for FPGA: Microsemi (ACTEL) antifuse Antifuse FPGAs are live-at-power-on, they don t need additional NVRAM to store code Antifuse FPGAs are one time programmable and VERY expensive Antifuse FPGAs are power hungry (and dual power ) Antifuse FPGAs are subject to US DOD Export Regulations (ITAR) Latest generation antifuse FPGAs come in HUGE packages (TQFP 256/352 unless you are able to qualify mounting of CCGA624) Latest generation Antifuse come with a relatively soft embedded RAM. EDAC is thus mandatory. ESA UNCLASSIFIED For Official Use

12 Is (quick, cheap, reliable) Space Electronics Development with Digital and A/MS ASIC Technology Feasible? In Europe there are at least three non proprietary RH Digital ASIC technologies with large space heritage In Europe there is currently only one A/MS ASIC technology flow that will reach T.R.L. 9 in 2013 The development EEE components and in particular of A/MS ASICs complicates the spacecraft supply chain and development chain How can functionality, reliability and radiation tolerance be ensured?

13 European Digital ASIC options vendor Lib name MG2RT MH1RT ATC18RHA RH-CMOS65LP ATC µm 65nm DARE (design against rad effects) Techno node 0.5µm 0.35µm 0.15µm SOI 180nm, 90nm Library developer ATMEL (F), co-funded by ESA and CNES STM(F,I) co-funded by ESA and CNES IMEC(B) funded by ESA ASIC Manufacturer MG2RT => MHS(F) Nantes, STMicroelectronics (F) Crolles UMC (Taiwan) rad tests on test vehicles for terrestrial radiation ( ). Deep Sub-micron 1st phase launched end Feasibility and definition of rad hard lib done. Several test vehicles manufactured and tested, including High Speed Serial Link. Alpha Design Kit released! New ESA contracts, to complete libraries, CAD flow, HSSL IP: nm Design Kit available since Activities in progress to add lib elements, fix memory compilers, mixed-signal DK and consolidate end-to-end space ASIC flow. MH1RT & ATC18RHA & ATC77 => LFOUNDRY (F) Rousset Status MG2RT => Discontinued, 2010 last time buy MH1RT => Discontinued, 2011 last time buy ATC18RHA => stable, ESCC certified ATC77=> in development, SOI 0.15, Mixed SIgnal Design Kit available in 3Q2013 (TBC) 1st porting efforts to 90nm concluded successfully in Work ongoing.

14 Digital and A/MS ASIC Design Flow DARE is the only Digital + A/MS technology flow that reaches T.R.L. 9 in What does DARE provide? Digital Design kit (synthesis library, back-end services) Analogue Design kit (Analogue library with radiation simulation models) A/MS building blocks DARE Currently targets UMC 0.18 Fab DARE A/MS technology porting to XFAB is under development DARE/XFAB ESCC capability approval is under discussion DARE A/MS building block porting to other foundries is under discussion

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16 A/MS ASIC Design Flow Building blocks

17 A/MS ASIC Design Flow Building blocks

18 Technology Trend in space electronic systems: System on a Chip Reduction of power consumption, mass and dimensions achievable with silicon evolution and introduction of the SoC technology are significant: GOCE (2009) CDMU TAS-I ERC32 GAIA (2013) CDMU RUAG-S AT697F SEOSAT (2014) OBC ASTRIUM-E SCOC3 Power consumption = < 90 W average (excluding external loads) Power consumption = < 40W average (excluding external loads) Power consumption = 15W peak (excluding external loads) Mass = 21kg Mass = 16kg Mass = 5.2kg Dimensions = 470(L)x272(H)x332(D) mm Dimensions = 420(L)x270(H)x(276(D) mm Dimensions = 250(L)x150(H)x216(D) mm

19 Next Generation Multi-Purpose Processor (NGMP) Quad Core LEON4 SoC 32bit Microprocessor The first phase of the activity has been kicked off in 3Q2009 with Aeroflex Gaisler as contractor. The NGMP is based on a SPARCV8-compliant multi-core architecture. The objective is to have a standard product implemented in DSM CMOS (65 nm is today s baseline). ASIC in commercial Silicon technology available! NGMP will include by a large on-chip memory (128-bit wide Level-1 cache, Level-2 cache of 256kB-2M depending on the available technology), SpW, Ethernet and UARTs, PCI 2.3, GPI/Os and debug I/Fs.

20 Heterogeneous/Multicore processor based DHS: Concept AOCS Processor TC/HK Processor Local Memory Local Memory Payload Processors Local Memory DRAM DRAM DRAM Local Memory Local Memory MEM I/F Processor Processor Processor Processor Processor DRAM DRAM FLASH TM I/F TM Radio PROM I/F Boot PROM TC I/F TC Radio Power Control IO Bus TC/HK Bus AOCS IO AOCS Interfaces/Bus SpaceWire IO Payload IO TC/HK IO SpaceWire Interfaces GPIO / UART / I2C / CAN TC/HK Bus

21 Technology Trend in space electronic systems: Mass Memories Trends: Hubble Rosetta GAIA Sentinel Gbit 4 Gbit 800 Gbit 2.4 Tbit (FLASH) 20 Mbps 100 Mbps (7*40Mbps SpW ch) 2.5 Gbps Input data rates will increase up to 10Gbps, while downlink will reach 3 Gbps. TerraSAR-X MMU (Astrium) ISSR (Astrium) GAIA PDHU (Syderal)

22 Technology Trend in space electronic systems: FLASH-based Mass Memories There s not such thing as a space grade NVRAM Commercial markets are dominated by NAND (and some NOR) FLASH Due to its simple structure and high demand for higher capacity, NAND FLASH memory is the most aggressively scaled technology among electronic devices. The technology has reached 20 nm in production (SAMSUNG, INTEL, MICRON). While the expected shrink timeline was a factor of two every three years per original version of Moore's law, this has recently been accelerated in the case of NAND flash to a factor of two every two years. As the feature size of flash memory cells reach the minimum limit further flash density increases will be driven by greater levels of MLC, possibly 3-D stacking of transistors, and improvements to the manufacturing process. The decrease in endurance and increase in uncorrectable bit error rates that accompany feature size shrinking shall then be compensated by improved error correction mechanisms. Inconvenient truth: FLASH are not NVRAM management, failure modes, and error correction schemes are very complex and application dependent!

23 Radiation Monitors: the way to keep an eye on our Radiation design Margins (and models) France: ICARE, CARMEN UK: MERLIN, CEDEX, Gal-EMU*, SPEAR*, HMRM* Switzerland: REM*, SREM*, LEED, Gal-EMU* Belgium: EPT* Italy: Alteino, ISS experiments, PAMELA Germany; DOSTEL, RAD, EuCPAD* Spain: Las Dos Torres, LPF-RM Portugal: MFS/AEEF* Czech Republic: SATRAM (Medipix)* Hungary: TriTel etc *ESA programme Developments are Harmonised through IPC/THAG and tracked by the Space Environments and Effects Network of Technical Competencies (SEENoTC) and classified by the ESCC/CTB Radiation Working Group as follows: Devices designed for providing in-situ data to host spacecraft: 1. Coarse radiation housekeeping 2. Alert and saving function 3. Support to platform and payload systems Devices designed for providing space-weather data: 4. Future mission preparation, provision of science data

24 ESA radiation monitors Present radiation monitors (e.g. SREM, EMU, ) ~ 2-3 kg ~ 2-3 W ~ 1 min time resolution Energy resolution channels Several units flown A wide range of orbits Engineering instrument RWG Categories 1-4 Next Generation Radiation Monitor (NGRM) < 1 kg <1W < 1 min time resolution Energy resolution channels Several units to be flown A wide range of orbits Engineering instrument RWG Categories 1-4 Future radiation monitors ( Highly Miniaturised Radiation Monitor, HMRM) ~ 100 grams ~ 100 mw < 1 min time resolution Energy resolution channels 10s-100s units to be flown A wide range of orbits Engineering instrument RWG Categories 1-3(+)

25 ESA radiation monitors

26 Future Technologies for Space ESA Development of A/MS supply chain with Process Capability Approval standard Support user groups of 350nm CMOS technologies AMS/ON-SEMI/XFAB A/MS technology with radiation characterisation and modelling generic SET simulation tool development High Radiation Tolerance (MRad) D+A/MS technology development with DARE/UMC Extend voltage range of DARE/UMC (CAN/LVDS) and extend A/MS building blocks for DARE/UMC Migration & Deployment of DARE technology to European Foundries: XFAB/IHP/LFoundry Identify missing elements in the A/MS technology Full qualification of 150 nm SOI and 65 nm CMOS RH Technologies Space grade 32bit microcontroller(s) the real FPGA replacemement! European reprogrammable, rad tolerant (SRAM) FPGA

27 Future Technologies for Space ESA IP Cores (and VHDL modeling guidelines ) Communication Processing Image compression Standard IP library for FLASH EDAC+Management Present processors Future processors (multi core, etherogeneous and homogeneous) Physical layer serial digital Specs Chips (CAN, 1553 ) Known good parts and design methods POL converters Standard FDIR schemes RASTA test and breadboarding system Software

28 Would you like to know more? space-env.esa.int