Design, Test & Repair Methodology for FinFET-Based Memories

Transcription

1 White Paper Design, Test & Repair Methodology for FinFET-Based Memories October 2015 Author Dr. Yervant Zorian Chief Architect and Fellow, Synopsys Like any IP block, memories need to be tested. But unlike many other IP blocks, memory test is not as simple as pass/fail. Memories are typically designed with redundant rows and columns that can be used to address process related defects, thereby increasing system-on-chip (SoC) yield to 90% or higher. In turn, redundancy allows memory designers push the process node to the limit, knowing that defects can be fi xed. The test process becomes increasingly important to supplement the design-manufacturing process. Testing memories has always presented a unique set of issues. Now, with the advent of FinFET-based memories, additional challenges need to be addressed. This white paper covers: The new design complexities, defect coverage and yield challenges presented by FinFET-based memories How to synthesize test algorithms for detection and diagnosis of FinFET specifi c memory defects How incorporating built-in self-test (BIST) infrastructures with high-effi ciency test and repair capabilities can help to ensure high yield for FinFET-based memories While this white paper has a particular focus on FinFET processes, many of these challenges are not processspecifi c. The new memory test issues presented here are relevant for any memory, whether supplied by Synopsys, a third party IP vendor or designed in-house. Comparing FinFET and Planar Technologies Intel fi rst used FinFET technology at 22nm and other major foundries joined in at 14/16nm and below. FinFET technologies have only grown in prevalence and importance since, as shown in Figure 1. Figure 1: Growth of active designs and tapeouts for process technologies from 90nm to 7/5nm FinFET

2 To understand the FinFET architecture, designers should fi rst compare the channels to a planar architecture, as shown in Figure 2. The left image shows a planar transistor. The major process motivation for switching to FinFET is what process engineers call short-channel effects and what design engineers call leakage. When the channel under the gate is too short and too deep for the gate to control it properly, even with it is off it is still partially on and leakage current fl ows, leading to very high static power dissipation. The middle image shows a FinFET. The fi n (grey) is thin and the gate wraps completely around it. All parts of the channel, where the fi n passes through the gate, are well-controlled and leakage is much lower. In process-speak, the channel is fully depleted of carriers. Typically, the architecture uses multiple fi ns (two or three), but future processes may use more. Using multiple fi ns offers better control than just a single fi n. The use of multiple fi ns highlights a substantial difference between FinFET and planar architectures. Planar processes use a two-dimensional interface with dimensions of the transistor width and length. In FinFETs, the size of the fi n is fi xed and the thickness of the gate (that defi nes the channel length) is also fi xed. The only parameter for varying a FinFET is the number of fi ns, and that has to be an integral number. For example: it is not possible to have 2½ fi ns. Field Effect Transistors (FET): The Field from Gate Controls the Channel Gate Planar FET Gate FinFET Gate Drain Source Source Oxide Oxide Oxide Silicon substrate Silicon substrate Silicon substrate Single gate channel control is limited at 20nm and below Multiple gate surrounds a thin channel and can fully deplete it of carriers. This results in much better electrical characteristics Figure 2: Planar vs FinFET architectures FinFETs offer more effi cient transistors that enable lower operating voltages, which has positive effects on both static power (linear) and dynamic power (quadratic). The power savings can be as high as 50%. The performance is higher as well at 0.7V, performance (throughput) is 37% better than planar technology. FinFET Complexity Leads to Manufacturing Challenges The complexity of a FinFET compared to planar typically leads to a more expensive manufacturing process, at least initially. As foundries gain more experience and better control of the process, these costs will probably decline but for the time being there is an increase in moving from planar processes. FinFETs also have thermal challenges. As the fi ns stick up, the body (substrate) of the die does not act as a heatsink and this can result in degradation and aging. The thermal challenges also have implications for repair because in some circumstances, memories need to be repaired not just at manufacturing test, but also later in the fi eld. Foundries need to take these challenges into account when making the process yield, ramping it to volume and so on. Typically, the foundries are also responsible for the memory bit cells which require thorough analysis (through simulation) and qualifi cation (through running wafers). The IP providers, whether for memories, standard cells, or interfaces, also need to build their layout while taking these issues into account. The impact on the SoC designers is less, at least for digital fl ows. Designers typically will never see a fi n any more than they ever saw a transistor before, unless they look inside the standard cells that their place-and-route tool was using to connect with the metal fabric. Design, Test & Repair Methodology for FinFET-based Memories 2

3 STAR Memory System The Synopsys ecosystem (Figure 3) includes all the tools required to create the layout, perform extraction, simulation and so forth. The internal Synopsys IP groups are able to leverage the complete Synopsys tool suite to design, validate, and test Synopsys IP, including memories. StarRC HSPICE CustomSim Custom Designer IP Sentaurus Proteus IC Validator Figure 3: Synopsys tool suite Synopsys has built expertise starting from the lowest levels. They have built multiple test chips with all the different FinFET manufacturers: Samsung, TSMC, Intel, GLOBALFOUNDRIES and UMC. As of August 2015, Synopsys has run more than 50 FinFET test chips. These chips have used the Synopsys test and repair solution known as the DesignWare STAR Memory System, where STAR in turn stands for Self-Test and Repair. Self-test and repair has been used for many process generations, not just with FinFET. With constant investments, Synopsys has improved STAR Memory System. In Figure 4, the STAR Memory System is represented by the purple boxes. These contain RTL blocks that are generated from the STAR Memory System IP compilers to deal with individual memories:, dual port, single port, register files and so on. The wrappers are all tied together through the STAR Memory System processors, which report back to the overall manager of the whole system, the STAR Memory System server which in turn provides all the required schedules and handshakes. The external interface is through the JTAG test access port (TAP) controller. Design, Test & Repair Methodology for FinFET-based Memories 3

4 Automated RTL solution for Synopsys and non-synopsys memories Performs test, diagnosis and redundancy analysis Cache group 1 CPU Cache group 2 Test bus Test bus processor MMB processor MMB processor Efuse server processor SoC TAP Standard JTAG and IEEE1500 interface Tester-ready pattern generation Failure diagnosis and fault classification Seamless interfaced to shared multi-memory bus (MMB) 2P RF 1P RF Multi-bit correcting ECC Compiler DP e-flash External memory test Post-silicon bring-up, debug, diagnosis and characterization Industry s 1 st commercial solution for e-flash Figure 4: DesignWare STAR Memory System: Process-optimized memory test, repair & diagnosis Each of the STAR Memory System processors are intelligent enough to handle detecting, diagnosing and repairing defects on the chip. Connecting and configuring all those purple boxes could be time-consuming and error prone, so the STAR Memory System also provides the automation needed to: Generate, insert and verify the configuration Complete the test pattern generation Perform classification of faults Locate the failure Correct when possible Synopsys mapped all of these automated steps onto FinFET technologies to handle the new classification and failure issues associated with FinFET specific memories. Starting in 2012, Synopsys has worked with an ecosystem of memory designers who have early access to process parameters. Working with multiple FinFET manufacturers, Synopsys analyzed their bit cells and also examined their models, validated them, created test chips, and analyzed the silicon directly in Synopsys internal labs. This process gave Synopsys a deep understanding of defect issues with FinFETs and enabled Synopsys to optimize the STAR Memory System to address them. As a result, today the STAR Memory System is used in multiple capacities: For process development: Using STAR Memory System to characterize and understand the foundry process for manufacturing For IP qualification: Characterizing and qualifying the memory IP itself For SoC design: Incorporating the STAR Memory System into the design for SoC analysis, including manufacturing test and repair For managing field reliability and aging: Handling the thermal issues inherent in FinFET processes due to the fin protruding, thermally isolated from the underlying base. Issues that can arise through the life of the SoC can be as minor as soft errors, which are automatically corrected through error correcting code (ECC). But aging in high-reliability systems may require the STAR Memory System to be used periodically, or at power-on to fix faults that develop in the field long after manufacturing test is completed. Design, Test & Repair Methodology for FinFET-based Memories 4

5 Of course the memory is not the only part of the chip that needs to be tested. There will also be logic blocks, interface IP blocks, analog mixed-signal (AMS) blocks and so on. Synopsys provides a comprehensive set of test and IP solutions that integrate smoothly with the STAR Memory System (Figure 5). For logic blocks, Synopsys offers DFTMAX and TetraMax. Interface IP (such as DDR, USB, and PCIe) have their own self-test engines but they all work seamlessly with the STAR Hierarchical System, Synopsys system-level test solution. It is not enough to have a solution for an individual block, but the SoC must work smoothly at the top level. Design Silicon Logic Memory Interface IP AMS (custom) DFTMAX TetraMAX (ATPG) STAR Memory System DesignWare IP with self-test User patterns/ self-test STAR Hierarchical System TetraMAX (Diagnosis) STAR Memory System (Diagnosis & Repair) STAR Hierarchical System STAR Hierarchical System Yield Explorer and Camelot TM Figure 5: Synopsys test and yield solution: Improving quality, reliability and yield Understanding FinFET Memory Failures and Defects Before understanding how to test and repair memories, designers must understand the ways in which they can fail. For example, resistive faults have been revealed as a performance problem in logic, where the logic passes the test but does not work at full speed. In memories, resistive faults can manifest in a more subtle way. The faults might cause a detectable error only after multiple operations (a write followed by several reads) instead of the more standard single operation (a read). Designers must also ascertain which errors can realistically occur by looking at the layout. In digital logic testing, big increases in coverage can be obtained by analyzing which metals are adjacent and might short together. The same can be done in a memory by analyzing potential resistive shorts, where signal lines may fail and so on. This requires a mixture of looking at the layout and spinning and analyzing test chips to identify possible faults. The requirement for deep analysis is one of the reasons that Synopsys has run more than 50 FinFET test chips at multiple foundries. Information from these tests is used to improve the STAR Memory System. Figure 6 illustrates several different defect types possible with FinFET processes. It illustrates just one fi n per transistor, but there is typically more than one fi n per transistor. Of course opens and shorts can occur but in FinFETs they can cause different behavior: fi n opens, gate opens, fi n stuck-ons, in-gate fi n shorts and so on. Each of these can be a hard open or short or can be resistive, with a resistance value varying from low to high producing different behavior. Design, Test & Repair Methodology for FinFET-based Memories 5

6 Fin Open Gate Open Process Variation Fin Stuck-On Gate-Fin Short Figure 6: Potential FinFET defect types After analyzing the layout, designers must look at the topology to see if faults can realistically occur, based on the physical structure of the transistor. The next step for designers is to go up a level from the pure transistor. An cell contains six transistors so the cell needs to be analyzed for opens in internal nodes, and how that might occur, and what would be the result. At the next level, the cell layout is the target. For example, Figure 7 shows all the possible open defects that can occur in the six transistor cell. Third, designers analyze the entire memory array for faults such as opens in bit-lines, shorts between word lines and so on. Finally, at the block level, the entire memory including surrounding blocks such as the address decoder need to be examined, as do the sense-amps. The actual analysis proceeds through defect injection. This is based on the GDS (layout) itself. Defect injection is done on the layout and on the SPICE models, using a defect library for each of the libraries and then seeing how they behave. Defect injection is done on transistors for all providers of 14/16nm FinFET whether they are IDMs or foundries. Defect injection is also done for planar technologies at higher nodes such as 45nm and 28nm. Considered locations of open defects in 6T FinFET -cell All transistor fins and nodes in cells Figure 7: Example of open defects injected in FinFET memory cell layout Defect injection demonstrates how each defect is behaving. The next action is to fi nd a test sequence that detects the defect, through Test Sequence Identifi cation (TSI). For each one of the potential defects, one or more test sequences are identifi ed, as well as the conditions under which it would be detected and the fault model that it corresponds to. Lots of test sequences, stress corners and simulation setups are used until a sequence is found that exhibits an observable difference from the defect-free version of the cell. In some cases, these defects will be fault models that have previously been seen in planar technology but FinFET memories have some additional failure modes. For example, Figure 8 shows a subtle failure mode. A resistive fi n open in a pull-down transistor results in a dynamic deceptive read destructive fault (ddrdf). Here, a write, followed by 7 reads, results in the bit value of the memory cell fl ipping. This can then be examined in more detail since it turns out to be frequency dependent. At 1.2MHz it just takes 4 reads but at 4MHz it takes 18. The temperature and voltage also impact these values. Design, Test & Repair Methodology for FinFET-based Memories 6

7 Figure 8: Defect injection investigation results: ddrdf-7 Some broad conclusions from Synopsys fault modeling on FinFET technologies are: FinFET-based memories are more prone to dynamic faults than planar memories FinFET-based memories are more stable against process variation faults Static single-cell and coupling faults are common in both types of memories Stress corners (voltage, temperature, frequency) are important for detecting FinFET-specifi c faults using only nominal corners misses some issues. Generating Test Sequences Once the fault modeling background is complete, designers understand the voltage, temperature and frequencies requirements for tests. The sequences for a given corner are combined with an engine known as the Test Algorithm Generator (TAG). The TAG will combine together small test sequences for individual fault types and create a minimum test algorithm to minimize the test time and so the test cost. Figure 9 shows the TAG for FinFETs. The processes in the fi gure are all automated, from injection of the fault to test sequence identifi cation to the TAG itself. Different pieces of algorithms can be partitioned for different corners and different levels of fault detections. Partitioning creates a pool of test sequences for different conditions, as different users and applications will have different requirements. For example, during manufacturing test, designers must identify failures so that they can be corrected, but a complete analysis on every failure to identify the root cause can be too time-consuming. However, if an error occurs often, designers will run more complex and expensive tests to narrow down exactly what is happening so they can take corrective action. Basic flow 4 levels of defect injection Advanced flow 4 levels of defect injection Probability of defects (provided by manufacturer) Test sequences for FinFET New test algorithm Test sequences for FinFET New test algorithm Partition 1 New test algorithm Partition 2 New test algorithm Partition N Most probable faults Less probable faults Figure 9: Test algorithm synthesis for FinFETs Design, Test & Repair Methodology for FinFET-based Memories 7

8 These processes and tests are all implemented in the STAR Memory System, taking into account failures from most FinFET providers, who share a wide commonality between them even though the bit cells are very different from each other. The STAR Memory System includes programmability in it. Through the JTAG port and the TAP controller, the algorithm can be updated to modify the test sequence itself or upgrade the algorithm for debug and diagnosis purposes or simply to upgrade it, even in the field. Detecting & Repairing Faults Using the STAR Memory System Synopsys deep and thorough analysis of failures and defect potentials in FinFETs is built into enabling the STAR Memory System to work at many levels, as shown in Figure 10. The highest level is just knowing which memory instance is failing, which for manufacturing test and correct may be enough. Next is the logical address of the failure and the physical address of the failure. The STAR Memory System can then identify the physical X,Y coordinates of the failing bit. The defect can be classified (single bit, paired bit, whole column, etc.), the fault classified and finally localized to the precise site of the failure. Note that all this has been identified by the STAR Memory System sitting outside the chip, not by using electron microscopy or other more intensive/ expensive approaches. 1. Memory instance failure 2. Logical address of failure 3. Physical address of failure (row, col) 4. Physical X, Y coordinates of failing bit 5. Defect classification (sing bit, paired bit, col, row etc.) 6. Fault classification (stuck-at, transition, coupling, etc.) 7. Fault localization (aggressor/victim cell coordinates etc.) Figure 10: DesignWare STAR Memory System: Multi-level precision diagnostics The development of tools and IP that yields high quality of results to the SoC users (or memory IP designers) is a long and ongoing process. Starting with in-depth memory design knowledge, early access to process parameters from multiple foundries, extensive fault injection simulations, silicon characterization and accurate behavioral and structural models, the process can take more than three years. Deep understanding of unique FinFET defects has resulted in optimized test algorithms for lower area impact and lower test time, plus understanding the stress conditions to exercise the defects. Finally, all that knowledge was incorporated into the STAR Memory System to create automatic insertion, fast test bring up, and maximum yield. FinFETs offer more possibilities to optimize timing with a pre-inserted group of memories with scheduling. The BIST multiplexers can be already in place with a shared test bus. These test buses can be reused by custom datapath creators and by processor cores. Synopsys created the Multi-Memory Bus (MMB) processor to take advantage of the possibilities offered by FinFETs. The MMB shares the BIST/BISR logic with all caches mapped to the bus, eliminating the need for memory wrappers, leading to smaller area and power consumption (Figure 11). Design, Test & Repair Methodology for FinFET-based Memories 8

9 Flexible placement or re-use of BIST Mux es and pipeline registers Processor... Memory Cache Group 1 Cache Group 2 CPU Test Bus Test Bus MMB MMB Processor Processor Conventional STAR Memory System Processor Supports generic test bus as well as processor-specific architecture Adds repair infrastructure to memories accessible through shared test bus MMB Processor Low area and power: BIST/BISR logic shared for all memories mapped to bus Eliminates the need for memory wrappers Figure 11: MMB processor builds on conventional STAR Memory System processors for higher FinFET performance and smaller area Figure 12 shows an SoC example where some memories use the STAR Memory System conventionally while the memories in the CPU core are accessed by the MMB processors. The MMB processor does not deal with the wrappers directly, but instead accesses the bus ports which are represented by the red boxes in Figure 12. The MMB processor reads the information from the CPU RTL to understand the memory specifi cs and the confi guration of the write bus, resulting in an immediate handshake. SOC Design Block MMB Processor MMB JTAG Efuse Server MMB Processor MMB CPU Core SHS wrapper Analog mixed/ signal IP SHS wrapper Digital IP Processor wrapper ROM Processor wrapper wrapper SP, 2P, MP s SP, 2P, MP s Figure 12: STAR Memory System MMB use model Repairing Faults Modern memories have both row and column redundancy (Figure 13). When failures are detected, the redundant columns can be confi gured by recording the problems and the repair solutions in non-volatile memory. The STAR Memory System automatically handles the repair by narrowing down the location of the fault and determining how to swap it out. The process can be optimized for all stress corners so that faults are detected at one corner and augmented to the next corner and so on. Design, Test & Repair Methodology for FinFET-based Memories 9

10 Figure 13: Using row and column repair to maintain high FinFET yields Since the STAR Memory System is so automated, diagnosis and repair can be repeated in the fi eld at predetermined intervals, such as whenever the system is powered on or some pre-specifi ed duration. The repetition allows faults that result from aging to be eliminated using built-in redundancy. FinFETs suffer from one particular aging problem that planar does not: negative bias temperature instability (NBTI). NBTI is mostly temperature based but results in gradual deterioration depending on the temperature range under which the FinFET is operating. Single Event Effects and Error Correction Not only do predictable errors occur, but intermittent soft errors can also occur. Intermittent soft errors do not need to be fi xed with built-in redundancy. They are usually caused by high energy particles. As the bit cells become closer and closer together in smaller process nodes, single-event-effects (SEE) can affect more than a single bit, and the multi-bit defects need to be detected and corrected. To combat these types of errors, the STAR Memory System contains an ECC compiler. The compiler provides more than the classic memory ECC, which typically permits multi-bit error detection but can only handle singlebit correction. The ECC compiler, on the other hand, can handle multi-bit correction. The STAR Memory System ECC Compiler defi nes the appropriate memory confi guration, replaces the memory with a memory with ECC (which will be wider than the required data, of course: a 32 bit memory will be ~40 bits wide). The memory is then wrapped with all the system test and repair logic. Design, Test & Repair Methodology for FinFET-based Memories 10

11 3D SoCs/ICs Use STAR Memory System to test external memory and interconnects Test individual die before packaging External Memory External Memory External Memory External Memory Digital core - DFTMAX Compression, STAR Memory System TAP MSIP - BIST, IEEE access Use TAP to run tests after packaging Figure 14: External memory test in 3D-ICs External DRAM, or memory-on-logic, presents a new set of challenges. Using through-silicon vias (TSVs) or other techniques, the DRAM physically sits on top of the chip, as shown in Figure 14. However, the memories are not directly accessible to the outside world, or at least not with the performance required to test them. Testing vehicles can t easily intercept signals between the memories and the logic if they are using a high-speed interface such as DDR4, JEDEC Wide I/O or Micron s Hybrid Memory Cube. Instead, an engine that sits on the SoC but can interact with the DRAM that is external to the chip can drive the interfaces at the necessary high speed. Just as with onchip memory, SoCs using external DRAM must fi nd out which memory, bit, or interconnect in the stack is failing and why. The STAR Memory System can handle this requirement and often repair it. STAR Hierarchical System All FinFET SoCs include more than just memories. They will have other mixed signal IP such as PCIe, USB, DDR, PLLs and more. Each of these interfaces requires self-testing and, in many cases, faults need to be detected and repaired. For fast I/O interfaces, repair means tuning, calibration and framing. To further complicate test and repair, some interface IP will itself contain memories. This complex system requires a thorough test and repair infrastructure like the STAR Hierarchical System shown in Figure 15. Design, Test & Repair Methodology for FinFET-based Memories 11

12 Cache group CPU Test bus processor processor Efuse Server SoC TAP Sub-server Interface IP Analog/ mixed-signal IP PLL Digital core Figure 15: DesignWare STAR Hierarchical System The STAR Hierarchical System compliments the STAR Memory System to enable test, debug and correction of mixed-signal non-memory IP. As a hierarchical solution, the STAR Hierarchical System can take an IP with its patterns from the sub-chip level up to the entire SoC, creating the access and interface, building up the patterns at the next level. Summary Today Synopsys has full support for a wide range of process nodes, including 14nm and 16nm FinFET, and work is progressing on 10nm and 7nm technologies. Using the knowledge gained from the test chips in these process nodes, the innovations in STAR Memory System will continue to improve test and diagnostics capabilities for embedded memories while adding functionality to optimize SoC yield. Synopsys also offers the STAR Hierarchical System to comprehensively test range of other mixed-signal and interface IP by leveraging any existing standard based interconnect like as well as TAP controller. Synopsys, Inc. 690 East Middlefield Road Mountain View, CA Synopsys, Inc. All rights reserved. Synopsys is a trademark of Synopsys, Inc. in the United States and other countries. A list of Synopsys trademarks is available at All other names mentioned herein are trademarks or registered trademarks of their respective owners. 10/15.rd.CS6548.