SYSTEM IN PACKAGE AND FUNCTIONAL MODULE FOR MOBILE AND IoT DEVICE ASSEMBLY

Transcription

1 SYSTEM IN PACKAGE AND FUNCTIONAL MODULE FOR MOBILE AND IoT DEVICE ASSEMBLY W. Koh, PhD Huawei Technologies JEDEC Mobile & IOT Forum Copyright 2017 Huawei Technologies, Ltd.

2 OUTLINE Mobile and IoT Device Trends Drivers/Advantages of SiP and Modules System in-package Advancement Functional Module Progress Device Assembly Concerns/Needs Industry Standards Metrology Assembly Yield Reliability Concluding Remarks

3 INTRODUCTION System level miniaturization using Morethan-Moore process and technology for SiP to bypass IC scaling (More Moore) Advantages Smaller footprint Less power Good performance Simpler board design Ease in PB assembly Number of components shrinking with use of mobile SOC, SiP, and modules Smart devices and IoT everywhere GE Smart lamp

4 Visual devices: AR/VR Audio devices: Wireless earbuds/headsets Body devices: LTEconnected Phonewatch DEVICE TRENDS

5 CONTROL OF SMART DEVICES (UI) Touch panel display/keypads Remote controller Smartphone Voice enabled controls Other web-enabled devices Integrated sensors and MEMs Vesper piezoelectric MEMS microphone

6 SiP TRENDS SiP in JEDEC package format PoP (SOC+memory) 2.5D/3D WLP Advanced processes for SiP TSV, WLP, CuP Bumping, termination (leads/balls), interconnection

7 RF FRONT END MODULE SiP Huawei P9/P10 Front End Modules: Skyworks SkyOne Ultra: SiP with integrated LTE and Taiyo Yuden SAW/BAW duplexer

8 FOWLP SIP TSMC INFO: wafer level integration

9 FM PRODUCTS RF modules Digital Camera Modules (DCM) Security sensor modules (Fingerprint/facial recognition) DRAM DIMM modules Power Management modules Interconnection is critical Source: Samsung

10 INTEGRATED DCM Sony 3-layer stacked DCM with DRAM memory High speed data readout 4X faster signal read (ISSSCC, Feb. 5, 2017)

11 BLE MODULES FOR IOT Bluetooth Low Energy SOC: integrated RF/μcontroller ($1) BLE Modules: transceiver, controller and built-in antenna ($3)

12 RF MODULE INTEGRATION Pillsy

13 MEMROY MODULES Intel Optane module as cache memory for laptop

14 Apple Watch S1 and S2 SMART WATCH MODULES

15 SiP FABRICATION CONCERNS Cost of enabling technology wafer thinning, thin package materials, thermal interfacing materials, TSV, micro bumping Molding of thin molding compounds and long term reliability Fine pitch solder joints Cost of integration processes Assembly process control and yield High temperature warpage induced defects: bridging, head in pillow, non-wet open

16 ASSEMBLY NEEDS Component dimension measurement and stability Board level interconnection materials and processes Fine-pitch paste printing High throughput, feedback loop SMT lines with inline AOI inspection Quick functional test and reliability studies

17 METROLOGY MEASUREMENT R.T. coplanarity High temperature dynamic measurements: warp/deformation for SiP, modules, connectors, and PB JC-11 TG: JEDEC Announces Task Group to Define High Temperature Flatness Requirements and Metrology for Connectors and PCB Footprints (Apr 13, 2017) SPP-024: High Temperature Flatness requirements for BGA: FSL (Flatness Sensitivity Levels)

18 ASSEMBLY TRENDS Moving toward application of low melt solder (SnBiAg, mp<200⁰c), reflow peak <230⁰C Step soldering for temperature-sensitive components Use flex circuits and flex hybrid electronics (FHE) Adoption of MCP, SiP and modules to reduce number of components

19 HI-TEMP Pb-FREE SMT REFLOW SAC solder alloys require up to 260⁰C reflow peak temperature That s 500⁰F hot, like grilling a steak on hot grill (When baking a steak, the recommended oven temperature is typically 400⁰F (200⁰C)

20 PoP POTATO CHIPS Under HT reflow, PoP packages may bend like Pringles potato chips Solutions: stiffening the packages Use lower melting solder paste and lower peak reflow Fujitsu

21 WARPAGE-RELATED STANDARDS JEDEC Publication 95, SPP-024 (Mar 2009) High Temperature Flatness Requirement for BGA Packages JEDEC JESD22-B112 Package Warpage Measurement of Surface-Mount Integrated Circuits at elevated Temperature JEITA ED-7306, Measurement methods of package warpage at elevated temperature and the maximum permissible warpage JESD22-B108, Coplanarity Test for Surface-Mount Semiconductor Devices. JESD22-B111 DROP SHOCK TEST SEMI 3DS-IC Standards Developments: TSV, metrology, interposer, carriers

22 EPOXY FLUX POLYMER REINFORMCEMENT Epoxy flux may be the easiest way to apply polymer reinforcement to LT solder joints No additional cure like underfill Good solder wetting PoP assembly Increase drop and shock resistance Reduce pad cratering Indium Corp Epoxy Flux EF-A and EF-E Pacrim Tech Page 22

23 CHALLENGES SiP and module Design for Manufacturing (DFM) Device User-interface Interconnection Test and metrology Materials and Processes for warpage control Standards Low cost, HVM assembly of IoT devices Supply chain/ecosystem for SiP and Module: distributors Avnet and Arrow started IoT supply groups Kyocera 6411 Series M.2 card edge connectors

24 CONCLUDING REMARKS SiP package format largely regulated by JEDEC standards, thin and large-sized packages still challenging in SMT assembly Functional modules follow more custom-design, little standards available Assembly concerns over SiP and FM: Large body size Thin thickness interconnect pitch SMT reflow deformation caused solder joint defects and yield loss (HiP, NWO, bridging) Better warpage control Trend to use low-melt solders and lower reflow peak

25 THANK YOU! Reference: More-than-Moore 2.5D and 3D SiP Integration Authors: Radojcic, Riko (2017 Springer International Publishing)