HIGH SPEED 128K (8K X 16 BIT) IDT70825S/L SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAM )

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1 HIGH SPEED 18K (8K X 16 BIT) SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAM ) Features High-speed access Commercial: ///4 (max.) Low-power operation IDT78S Active: 77mW (typ.) Standby: mw (typ.) IDT78L Active: 77mW (typ.) Standby: 1mW (typ.) 8K x 16 Sequential Access Random Access Memory (SARAM ) Sequential Access from one port and standard Random Access from the other port Separate upper-byte and lower-byte control of the Random Access Port High speed operation taa for random access port tcd for sequential port clock cycle time Architecture based on Dual-Port RAM cells Compatible with Intel BMIC and 84 PCI Set Width and Depth Expandable Sequential side Address based flags for buffer control Pointer logic supports up to two internal buffers Battery backup operation - V data retention TTL-compatible, single V (+%) power supply Available in 8-pin TQFP and 84-pin PGA Industrial temperature range (-4 C to +8 C) is available for selected speeds Description The IDT78 is a high-speed 8K x 16-Bit Sequential Access Random Access Memory (SARAM). The SARAM offers a single-chip solution to buffer data sequentially on one port, and be accessed randomly (asynchronously) through the other port. The device has a Dual-Port RAM based architecture with a standard SRAM interface for the random (asynchronous) access port, and a clocked interface with counter Functional Block Diagram A-1 1 CE OE R/W LSB LB MSB UB CMD I/O-1 Random Access Port Controls 16 1 DataL AddrL 8KX16 Memory Array DataR AddrR 16 Sequential Access Port Controls Reg RST CNTEN SOE SSTRT1 SSTRT SCE SR/W SLD SI/O-1, RST Pointer/ Counter Start Address for Buffer #1 End Address for Buffer #1 Start Address for Buffer # End Address for Buffer # Flow Control Buffer Flag Status 1 COMPARATOR EOB1 EOB 16 drw 1 9 Integrated Device Technology, Inc JANUARY 9 DSC-16/

2 sequencing for the sequential (synchronous) access port. Fabricated using CMOS high-performance technology, this memory device typically operates on less than 77mW of power at maximum high-speed clock-to-data and Random Access. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode. The IDT78 is packaged in a 8-pin Thin Quad Flatpack (TQFP) or 84-pin Pin Grid Array (PGA). Pin Configuratio (1,,) INDEX SI/O SI/O VCC SI/O4 SI/O SI/O6 SI/O7 GND SI/O8 SI/O9 SI/O SI/O11 VCC SI/O1 SI/O1 SI/O14 SI/O1 GND N/C A1 SI/O1 SI/O GND N/C SCE SR/W RST SLD SSTRT SSTRT1 GND GND CNTEN SOE GND EOB EOB1 VCC I/O GND VCC IDT78PF PN8-1 (4) 8-PinTQFP Top View () GND VCC GND A11 A A9 A8 A7 A6 A A4 A A VCC VCC A 1 CMD 16 CE 17 LB 18 4 UB 19 4 R/W OE 16 drw I/O1 I/O I/O I/O4 I/O I/O6 I/O7 I/O8 I/O9 I/O I/O11 I/O1 I/O1 I/O14 I/O1 A1, I/O1 VCC EOB1 GND CNTEN GND SSTRT SR/W NC GND NC I/O NC I/O EOB SOE RST SLD SCE SI/O SI/O1 SI/O I/O GND GNDSSTRT1 SI/O VCC I/O7 I/O6 GND IDT78G SI/O8 SI/O7 GND G84- (4) 1 6 I/O9 I/O I/O8 SI/O9 84-Pin PGA SI/O SI/O Top View () I/O4 VCC SI/O4 SI/O I/O I/O11 VCC SI/O1 VCC SI/O11 8 I/O1 I/O1 SI/O14 SI/O I/O14 NC CMD VCC A NC SI/O I/O1 GND OE LB A VCC A4 A7 A A1 GND NC R/W UB CE A1 A A A6 A8 A9 A A B C D E F G H J K L INDEX 1. All VCC pi must be connected to power supply.. All GND pi must be connected to ground supply.. PN-8-1 package body is approximately 14mm x 14mm x 1.4mm. G84- package body is approximately 1.1 in x 1.1 in x.16 in. 4. This package code is used to reference the package diagram.. This text does not indicate orientation of the actual part-marking. 16 drw

3 Pin Descriptio: Random Access Port (1) SYMBOL NAME I/O DESCRIPTIONS A-A1 Address Lines I Address inputs to access the 819-word (16-Bit) memory array. I/O-I/O1 Inputs/Outputs I Random access data inputs/outputs for 16-Bit wide data. CE Chip Enable I When CE is LOW, the random access port is enabled. When CE is HIGH, the random access port is disabled into power-down mode and the I/O outputs are in the High-impedance state. All data is retained during CE = VIH, unless it is altered by the sequential port. CE and CMD may not be LOW at the same time. CMD Control Register Enable I When CMD is LOW, address lines A-A, R/W, and inputs/outputs I/O-I/O1, are used to access the control register, the flag register, and the start and end of buffer registers. CMD and CE may not b e LOW at the same time. R/W Read/Write Enable I If CE is LOW and CMD is HIGH, data is written into the array when R/W is LOW and read out of the array when R/W is HIGH. If CE is HIGH and CMD is LOW, R/W is used to access the buffer command registers. CE and CMD may not be LOW at the same time. OE Output Enable I When OE is LOW and R/W is HIGH, I/O-I/O1 outputs are enabled. When OE is HIGH, the I/O outputs are in the High-impedance state. LB, UB Lower Byte, Upper Byte Enables I When LB is LOW, I/O-I/O7 are accessible for read and write operatio. When LB is HIGH I/O-I/O7 are tristated and blocked during read and write operatio. UB controls access for I/O8-I/O1 in the same manner and is asynchronous from LB. VCC Power Supply I Seven +V power supply pi. All VCC pi must be connected to the same +V VCC supply. GND Ground I Ten ground pi. All ground pi must be connected to the same ground supply. Pin Descriptio: Sequential Access Port (1) SYMBOL NAME I/O DESCRIPTIONS 16 tbl 1 SI/O-1 Inputs/Outputs I Sequential data inputs/outputs for 16-bit wide data. Clock I SI/O-SI/O1, SCE, SR/W, and SLD are registered on the LOW-to-HIGH traition of. Also, the sequential access port address pointer increments by 1 on each LOW-to-HIGH traition of when CNTEN is LOW. SCE Chip Enable I When SCE is LOW, the sequential access port is enabled on the LOW-to-HIGH traition of. When SCE is HIGH, the sequential access port is disabled into powered-down mode on the LOW-to-HIGH traition of, and the SI/O outputs are in the High-impedance state. All data is retained, unless altered by the random access port. CNTEN Control Enable I When CNTEN is LOW, the address pointer increments on the LOW-to-HIGH traition of. This function is independent of CE. SR/W Read/Write Enable I When SR/W and SCE are LOW, a write cycle is initiated on the LOW-to-HIGH traition of. When SR/W is HIGH, and SCE and SOE are LOW, a read cycle is initiated on the LOW-to-HIGH traition of. Termination of a write cycle is done on the LOW-to-HIGH traition of if SR/W or SCE is HIGH. SLD Address Pointer Load Control I When SLD is sampled LOW, there is an internal delay of one cycle before the address pointer changes. When SLD is LOW, data on the inputs SI/O-SI/O1 is loaded into a data-in registe r on the LOW-to-HIGH traition of. On the cycle following SLD, the address pointer changes to the address location contained in the datain register. SSTRT1 and SSTRT may not be LOW while SLD is LOW or during the cycle following SLD. SSTRT1, SSTRT Load Start of Address Register I When SSTRT1 or SSTRT is LOW, the start of address register #1 or # is loaded into the address pointer on the LOW-to-HIGH traition of. The start address are stored in internal registers. SSTRT1 and SSTRT may not be LOW while SLD is LOW or during the cycle following SLD. EOB1, EOB End of Buffer Flag I EOB1 or EOB is output LOW when the address pointer is incremented to match the address stored in the end of the buffer registers. The flags can be cleared by either asserting RST LOW or by writing zero into Bit and/or Bit 1 of the control register at address 1. EOB1 and EOB are dependent on separate internal registers, and therefore separate match addresses. SOE Output Enable I SOE controls the data outputs and is independent of. When SOE is LOW, output buffers and the sequentially addressed data is output. When SOE is HIGH, the SI/O output bus is in the High-impedance state. SOE is asynchronous to. RST Reset I When RST is LOW, all internal registers are set to their default state, the address pointer is set to zero and the EOB1 and EOB flags are set HIGH. Rst is asynchronous to. NOTE: 1. "I/O" is bidirectional input and output. "I" is input and "O" is output. 16 tbl 6.4

4 Absolute Maximum Ratings (1) Symbol Rating Commercial & Industrial VTERM () TBIAS TSTG IOUT Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature DC Output Current Unit -. to +7. V - to +1 o C -6 to + o C ma Recommended Operating Temperature and Supply Voltage (1,) Grade Ambient Temperature GND Vcc Commercial O C to +7 O C V.V + % Industrial -4 O C to +8 O C V.V + % 16 tbl 4a 1. This is the parameter TA. This is the "itant on" case temperature.. Industrial temperature: for specific speeds, packages and powers contact your sales office. 16 tbl a 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio above those indicated in the operational sectio of this specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect reliability.. VTERM must not exceed Vcc + % for more than % of the cycle time or maximum, and is limited to < ma for the period of VTERM > Vcc + %. Capacitance (TA = + C, f = 1.mhz, TQFP only) Symbol Parameter Conditio () Max. Unit CIN Input Capacitance VIN = dv 9 pf COUT Output Capacitance VOUT = dv pf Recommended DC Operating Conditio Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4... V GND Ground V VIH Input High Voltage. 6. () V VIL Input Low Voltage -. (1).8 V 1. VIL > 1.V for pulse width less than.. VTERM must not exceed Vcc + %. 16 tbl 16 tbl 6 1. This parameter is determined by device characterization, but is not production tested.. dv references the interpolated capacitance when the input and output signals switch from V to V or from V to V. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC =.V ± %) 78S 78L Symbol Parameter Test Conditio Min. Max. Min. Max. Unit ILI Input Leakage Current VCC =.V, VIN = V to VCC ILO Output Leakage Current VOUT = V to VCC 1 µa 1 µa VOL Output Low Voltage IOL = +4mA.4.4 V VOH Output High Voltage IOH = -4mA.4.4 V 16 tbl 7 4

5 DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (1,,8) (VCC =.V ± %) 78X 78X 78X 78X4 Symbol Parameter Test Condition Version Typ. Max. Typ. Max. Typ. Max. Typ. Max. Unit ICC Dynamic Operating Current (Both Ports Active) CE = VIL, Outputs Disabled SCE = VIL () f = fmax () COM'L S L ma ISB1 Standby Current (Both Ports - TTL Level Inputs) SCE and CE > VIH (7) COM'L S CMD = VIH f = fmax () L ma ISB Standby Current (One Port - TTL Level Inputs) CE or SCE = VIH COM'L S Active Port Outputs Disabled, f=fmax () L ma ISB Full Standby Current (Both Ports - CMOS Level Inputs) Both Ports CE and SCE > VCC -.V (6,7) VIN > VCC -.V or VIN <.V, f = (4) COM'L S L ma ISB4 Full Standby Current (One Port - CMOS Level Inputs) One Port CE or SCE > VCC -.V (6) Outputs Disabled (Active Port) VIN > VCC -.V or VIN <.V f = fmax () COM'L S L ma 16 tbl 8a 1. 'X' in part number indicates power rating (S or L).. VCC = V, TA = + C; guaranteed by device characterization but not production tested.. At f = fmax, address, control lines (except Output Enable), and are cycling at the maximum frequency read cycle of 1/tRC. 4. f = mea no address or control lines change.. SCE may traition, but is LOW (SCE=VIL) when clocked in by. 6. SCE may be -.V, after it is clocked in, since =VIH must be clocked in prior to powerdown. 7. If one port is enabled (either CE or SCE = LOW) then the other port is disabled (SCE or CE = HIGH, respectively). CMOS HIGH > Vcc -.V and LOW <.V, and TTL HIGH = VIH and LOW = VIL. 8. Industrial temperature: for other speeds, packages and powers contact your sales office. Data Retention Characteristics Over All Temperature Ranges (L Version Only) (VLC <.V, VHC > VCC -.V) Symbol Parameter Test Condition Min. Typ. (1) Max. Unit VDR VCC for Data Retention VCC = V. V ICCDR Data Retention Current CE > VHC VIN = VHC or = VLC IND. 4 µa COM'L. tcdr () Chip Deselect to Data Retention Time SCE = VHC (4) when = V tr () Operation Recovery Time CMD = VHC trc () V NOTES : 1. TA = + C, VCC = V; guaranteed by device characterization but not production tested.. trc = Read Cycle Time. This parameter is guaranteed by device characterization, but is not production tested. 4. To initiate data retention, SCE = VIH must be clocked in. 16 tbl 9a 6.4

6 Data Retention and Power Down/Up Waveform (Random and Sequential Port) (1,) VCC 4.V DATA RETENTION MODE VDR V 4.V tcdr tr CE VIH VDR VIH SCE tpd tpu ICC ISB 1. SCE is synchronized to the sequential clock input.. CMD > VCC -.V. ISB 16 drw 4 V V 89Ω 89Ω DATAOUT DATAOUT 47Ω pf 47Ω pf* 16 drw 16 drw 6, Figure 1. AC Output Test Load Figure. Output Test Load (for tclz, tblz, tolz, tchz, tbhz, tohz, Z, tckhz, and tcklz) *Including scope and jig. AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to.v Max. 1.V 1.V Figures 1, and 16 tbl taa/tcd/teb (Typical, ) pf is the I/O capacitance of this device, and pf is the AC Test Load capacitance CAPACITANCE (pf), 16 drw 7 Figure. Lumped Capacitance Load Typical Derating Curve 6

7 Truth Table I: Random Access Read and Write (1,) Inputs/Outputs CE CMD R/W OE LB UB I/O-I/O7 I/O8-I/O1 Mode L H H L L L DATAOUT DATAOUT Read both Bytes. L H H L L H DATAOUT High-Z Read lower Byte only. L H H L H L High-Z DATAOUT Read upper Byte only. L H L H () L L DATAIN DATAIN Write to both Bytes. L H L H () L H DATAIN High-Z Write to lower Byte only. L H L H () H L High-Z DATAIN Write to upper Byte only. H H X X X X High-Z High-Z Both Bytes deselected and powered down. L H H H X X High-Z High-Z Outputs disabled but not powered down. L H X X H H High-Z High-Z Both Bytes deselected but not powered down. H L L H () L (4) L (4) DATAIN DATAIN Write I/O-I/O11 to the Buffer Command Register. H L H L L (4) L (4) DATAOUT DATAOUT Read contents of the Buffer Command Register via I/O-I/O1. 1. H = VIH, L = VIL, X = Don't Care, and High-Z = High-impedance.. RST, SCE, CNTEN, SR/W, SLD, SSTRT1, SSTRT,, SI/O-SI/O1, EOB1, EOB, and SOE are unrelated to the random access port control and operation.. If OE = VIL during write, Z must be added to the twp or tcw write pulse width to allow the bus to float prior to being driven. 4. Byte operatio to control register using UB and LB separately are also allowed. Truth Table II: Sequential Read (1,,,6,8) Inputs/Outputs 16 tbl 11 SCE CNTEN SR/W EOB1 EOB SOE SI/O MODE L L H LOW LAST L [EOB1] Counter Advanced Sequential Read with EOB1 reached. L H H LAST LAST L [EOB1-1] Non-Counter Advanced Sequential Read, without EOB1 reached L L H LAST LOW L [EOB] Counter Advanced Sequential Read with EOB reched. L H H LAST LAST L [EOB - 1] Non-Counter Advanced Sequential Read without EOB reached. L L H LOW LOW H High-Z Counter Advanced Sequential Non-Read with EOB1 and EOB reached. Truth Table III: Sequential Write (1,,,4,,6,7,8) Inputs/Outputs 16 tbl 1 SCE CNTEN SR/W EOB1 EOB SOE SI/O MODE L H L LAST LAST H SI/OIN Non-Counter Advanced Sequential Write, without EOB1 or EOB reached. L L L LOW LOW H SI/OIN Coounter Advanced Sequential Write with EOB1 and EOB reached. H H X LAST LAST X High-Z No Write or Read due to Sequential port Deselect. No counter advance. H L X NEXT NEXT X High-Z No Write or Read due to Sequential port Deselect. Counter does advance. 16 tbl 1 1. H = VIH, L = VIL, X = Don't Care, and HIGH-Z = High-impedance. LOW = VOL.. RST, SLD, SSTRT1, SSTRT are continuously HIGH during a sequential write access, other than pointer access operatio.. CE, OE, R/W, CMD, LB, UB, and I/O-I/O1 are unrelated to the sequential port control and operation except for CMD which must not be used concurrently with the sequential port operation (due to the counter and register control). CMD should be HIGH (CMD = VIH) during sequential port access. 4. SOE must be HIGH (SOE=VIH) prior to write conditio only if the previous cycle is a read cycle, since the data being written must be an input at the rising edge of the clock during the cycle in which SR/W = VIL.. SI/OIN refers to SI/O-SI/O1 inputs. 6. "LAST" refers to the previous value still being output, no change. 7. Termination of a write is done on the LOW-to-HIGH traition of if SR/W or SCE is HIGH. 8. When CLKEN=LOW, the address is incremented on the next rising edge before any operation takes place. See the diagrams called "Sequential Counter Enable Cycle after Reset, Read (and write) Cycle"

8 Truth Table IV: Sequential Address Pointer Operatio (1,,,4,) Inputs/Outputs SLD SSTRT1 SSTRT SOE MODE H L H X Start address for Buffer #1 loaded into Address Pointer. H H L X Start address for Buffer # loaded into Address Pointer. L H H H (6) Data on SI/O-SI/O1 loaded into Address Pointer. 1. H = VIH, L = VIL, X = Don't Care, and High-Z = High-impedance.. RST is continuously HIGH. The conditio of SCE, CNTEN, and SR/W are unrelated to the sequential address pointer operatio.. CE, OE, R/W, LB, UB, and I/O-I/O1 are unrelated to the sequential port control and operation, except for CMD which must not be used concurrently with the sequential port operation (due to the counter and register control). CMD should be HIGH (CMD = VIH) during sequential port access. 4. Address pointer can also change when it reaches an end of buffer address. See Flow Control Bits table.. When SLD is sampled LOW, there is an internal delay of one cycle before the address pointer changes. The state of CNTEN is ignored and the address is not incremented during the two cycles. 6. SOE may be LOW with SCE deselect or in the write mode using SR/W. 16 tbl 14 Address Pointer Load Control (SLD) In SLD mode, there is an internal delay of one cycle before the address pointer changes in the cycle following SLD. When SLD is LOW, data on the inputs SI/O-SI/O1 is loaded into a data-in register on the LOW-to-HIGH traition of. On the cycle following SLD, the address pointer changes to the address location contained in the data-in register. SSTRT1, SSTRT may not be low while SLD is LOW, or during the cycle following SLD. The SSTRT1 and SSTRT require only one clock cycle, since these addresses are pre-loaded in the registers already. SLD MODE (1) SLD (1) A B C SI/O-1 ADDRIN DATAOUT SSTRT(1 or ) 16 drw 8 NOTE: 1. At edge (A), SI/O-SI/O1 data is loaded into a data-in register. At edge (B), contents of the data-in register are loaded into the address pointer (i.e. address pointer changes). At edge (A), SSTRT1 and SSTRT must be HIGH to eure for proper sequential address pointer loading. At edge (B), SLD and SSTRT1, must be HIGH to eure for proper sequential address pointer loading. For SSTRT1 or SSTRT, the data to be read will be ready for edge (B), while data will not be ready at edge (B) when SLD is used, but will be ready at edge (C). Sequential Load of Address into Pointer/Counter (1) MSB H H H Address Loaded into Pointer LSB SI/O BITS NOTE: 1. "H" = VIH for the SI/O intput state. 16 drw 9 8

9 Reset (RST) Setting RST LOW resets the control state of the SARAM. RST functio asynchronously of, (i.e. not registered). The default states after a reset operation are as follows: Register Contents Address Pointer EOB Flags Cleared to High State Buffer Flow Mode BUFFER CHAINING Start Address Buffer #1 (1) End Address Buffer #1 49 (4K) Start Address Buffer # 496 (4K+1) End Address Buffer # 8191 (8K) Registered State SCE = VIH, SR/W = VIL 16 tbl 1 BUFFER COMMAND MODE (CMD) Buffer Command Mode (CMD) allows the random access port to control the state of the two buffers. Address pi A-A and I/O pi I/ O-I/O1 are used to access the start of buffer and the end of buffer addresses and to set the flow control mode of each buffer. The Buffer Command Mode also allows reading and clearing the status of the EOB flags. Seven different CMD cases are available depending on the conditio of A-A and R/W. Address bits A-A1 and data I/O bits I/O1-I/O1 are not used during this operation. Random Access Port CMD Mode (1) Case # A-A R/W DESCRIPTIONS 1 (1) Write (read) the start address of Buffer #1 through I/O-I/O1. 1 (1) Write (read) the end address of Buffer #1 through I/O-I/O1. (1) Write (read) the start address of Buffer # through I/O-I/O (1) Write (read) the end address of Buffer # through I/O-I/O1. (1) Write (read) flow control register. 6 1 Write only - clear EOB1 and/or EOB flag Read only - flag status register. 8 1/111 (X) (Reserved) 1. R/W input "(1)" indicates a write() or read(1) occurring with the same address input. 16 tbl 16 Cases 1 through 4: Start and End of Buffer Register Description (1,) Address Loaded into Buffer MSB H H H LSB I/O BITS 16 drw 1. "H" = VOH for I/O in the output state and "Don't Cares" for I/O in the input state.. A write into the buffer occurs when R/W = VIL and a read when R/W = VIH. EOB1/SOB1 and EOB/SOB are chosen through address A-A while CMD = VIL and CE = VIH. Case : Buffer Flow Modes Within the SARAM, the user can designate one of four buffer flow modes for each buffer. Each buffer flow mode defines a unique set of actio for the sequential port address pointer and EOB flags. In BUFFER CHAINING mode, after the address pointer reaches the end of the buffer, it sets the corresponding EOB flag and continues from the start address of the other buffer. In STOP mode, the address pointer stops incrementing after it reaches the end of the buffer. In LINEAR mode, the address pointer ignores the end of buffer address and increments past it, but sets the EOB flag. MASK mode is the same as LINEAR mode except EOB flags are not set

10 Flow Control Register Description (1,) MSB 1 H H H H H H H H H H H 4 1 LSB I/O BITS Counter Release (STOP Mode Only) Buffer #1 flow control Buffer # flow control 16 drw "H" = VOH for I/O in the output state and "Don't Cares"' for I/O in the input state.. Writing a into bit 4 releases the address pointer after it is stopped due to the STOP mode and allows sequential write operatio to resume. This occurs asynchronously of, and therefore caution should be taken. The pointer will be at address EOB+ on the next rising edge of that is enabled by CNTEN. The pointer is also released by RST, SLD, SSTRT1 and SSTRT operatio. Flow Control Bits Flow Control Bit 1 & Bit (Bit & Bit ) Mode Functional Description BUFFER CHAINING EOB1 (EOB) is asserted (active LOW output) when the pointer matches the end address of Buffer #1 (Buffer #). The pointer value is changed to the start address of Buffer # (Buffer #1) (1,) 1 STOP EOB1 (EOB) is asserted when the pointer matches the end address of Buffer #1 (Buffer #). The address pointer will stop incrementing when it reaches the next address (EOB address + 1), if CNTEN is LOW on the next clock's rising edge. Otherwise, the address pointer will stop incrementing on EOB. Sequential write operatio are inhibited after the address pointer is stopped. The pointer can be released by bit 4 of the flow control register. (1,,4) LINEAR EOB1 (EOB) is asserted when the pointer matches the end address of Buffer #1 (Buffer #). The pointer keeps incrementing for further operatio. (1) 11 MASK EOB1 (EOB) is not asserted when the pointer reaches the end address of Buffer #1 (Buffer #), although the flag status bits will be set. The pointer keeps incrementing for further operatio. 1. EOB1 and EOB may be asserted (set) at the same time, if both end addresses have been loaded with the same value.. CMD flow control bits are unchanged, the count does not continue advancement.. If EOB1 and EOB are equal, then the pointer will jump to the start of Buffer #1. 4. If counter has stopped at EOBx and was released by bit 4 of the flow control register, CNTEN must be LOW on the next rising edge of otherwise the flow control will remain in the STOP mode. Cases 6 and 7: Flag Status Register Bit Description (1) 1 MSB H H H H H H H H H H H H H H 1 LSBI/O BITS 16 tbl 17 NOTE: 1. "H" = VOH for I/O in the output state and "Don't Cares" for I/O in the input state. Cases 6: Flag Status Register Write Conditio (1) Flag Status Bit, (Bit 1) Functional Description Clears Buffer Flag EOB1, (EOB). 1 No change to the Buffer Flag. () 16 tbl Either bit or bit 1, or both bits, may be changed simultaneously. One may be cleared while the second is left alone or cleared.. Remai as it was prior to the CMD operation, either HIGH (1) or LOW (). Cases 8 and 9: (Reserved) Illegal operatio. All outputs will be HIGH on the I/O bus during a READ. EndofbufferflagforBuffer#1 EndofbufferflagforBuffer# 16 drw 1 Case 7: Flag Status Register Read Conditio Flag Status Bit, (Bit 1) Functional Description EOB1 (EOB) flag has not been set, the pointer has not reached the end of the buffer. 1 EOB1 (EOB) flag has been set, the pointer has reached the end of the buffer. 16 tbl 19

11 Random Access port: AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (,4,) 78X 78X 78X 78X4 Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. READ CYCLE trc Read Cycle Time 4 taa Address Access Time 4 tace Chip Enable Access Time 4 tbe Byte Enable Access Time toe Output Enable Access Time 1 toh Output Hold from Address Change tclz Chip Select Low-Z Time (1) tblz Byte Enable Low-Z Time (1) tolz Output Enable Low-Z Time (1) tchz Chip Select High-Z Time (1) tbhz Byte Enable High-Z Time (1) tohz Output Enable High-Z Time (1) tpu Chip Select Power Up Time tpd Chip Select Power Down Time 4 Unit 16 tbl a Random Access Port: AC Electrical Characteristics Over the Operating Temperature and Supply Voltage (,4,) 78X 78X 78X 78X4 Symbol WRITE CYCLE Parameter Min. Max. Min. Max. Min. Max. Min. Max. twc Write Cycle Time 4 tcw Chip Enable to End-of-Write 1 taw Address Valid to End-of-Write () 1 tas Address Set-up Time twp Write Pulse Width () 1 tbp Byte Enable Pulse Width () 1 twr Write Recovery Time Z Write Enable Output in High-Z Time (1) tdw Data Set-up Time 1 1 Data Hold Time tow Output Active from End-of-Write 1. Traition measured at mv from steady state. This parameter is guaranteed with the AC Output Test Load (Figure 1) by device characterization, but is not production tested.. 'X' in part number indicates power rating (S or L).. OE is continuously HIGH, OE = VIH. If during the R/W controlled write cycle the OE is LOW, twp must be greater or equal to Z + tdw to allow the I/O drivers to turn off and on the data to be placed on the bus for the required tdw. If OE is HIGH during the R/W controlled write cycle, this requirement does not apply and the minimum write pulse is the specified twp. For the CE controlled write cycle, OE may be LOW with no degradation to tcw timing. 4. CMD access follows standard timing listed for both read and write accesses, (CE = VIH when CMD = VIL) or (CMD = VIH when CE = VIL).. Industrial temperature: for specific speeds, packages and powers contact your sales office Unit 16 tbl 1a

12 Waveform of Read Cycles: Random Access Port (1,) trc ADDR taa toh CE tacs() tclz tchz LB, UB tbe tbhz tblz OE tolz toe tohz I/OOUT ValidDataOut 16 drw 1 1. R/W is HIGH for read cycle.. Address valid prior to or coincident with CE traition LOW; otherwise taa is the limiting parameter. Waveform of Read Cycles: Buffer Command Mode ADDR trc CMD (1) taa tacs toh tclz tchz LB, UB tbe tbhz OE tblz I/OOUT tolz toe Valid Data Out tohz 16 drw 14 NOTE: 1. CE = VIH when CMD = VIL. 1

13 Waveform of Write Cycle No.1 (R/W Controlled Timing) Random Access Port (1,6) twc ADDR taw R/W CE, LB, UB (8) tas () () () twp twr I/OIN tdw Valid Data In OE tohz I/OOUT Z Data Out (4) (4) Data Out tacs tbe tow 16 drw 1 Waveform of Write Cycle No. (CE, LB, and/or UB Controlled Timing) Random Access Port (1,6,7) ADDR twc CE, LB, UB (8) () taw R/W tas twr tcw () () tbp () I/OIN tdw Valid Data 16 drw R/W, CE, or LB and UB must be inactive during all address traitio.. A write occurs during the overlap of R/W = VIL, CE = VIL and LB = VIL and/or UB = VIL.. twr is measured from the earlier of CE (and LB and/or UB) or R/W going HIGH to the end of the write cycle. 4. During this period, I/O pi are in the output state and the input signals must not be applied.. If the CE LOW traition occurs simultaneously with or after the R/W LOW traition, the outputs remain in the High-impedance state. 6. OE is continuously HIGH, OE = VIH. If during the R/W controlled write cycle the OE is LOW, twp must be greater or equal to Z + tdw to allow the I/O drivers to turn off and on the data to be placed on the bus for the required tdw. If OE is HIGH during the R/W controlled write cycle, this requirement does not apply and the minimum write pulse is the specified twp. For the CE controlled write cycle, OE may be LOW with no degregation to tcw timing. 7. I/OOUT is never enabled, therefore the output is in HIGH-Z state during the entire write cycle. 8. CMD access follows the standard CE access described above. If CMD = VIL, then CE must = VIH or, when CE = VIL, CMD must = VIH

14 Sequential Port: AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (1,) 78X 78X 78X 78X4 Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit READ CYCLE tcyc Sequential Clock Cycle Time 4 tch Clock Pulse HIGH tcl Clock Pulse LOW Count Enable and Address Pointer Set-up Time 6 6 Count Enable and Address Pointer Hold Time tsoe Output Enable to Data Valid 8 1 tolz Output Enable Low-Z Time () tohz Output Enable High-Z Time () tcd Clock to Valid Data 4 tckhz Clock High-Z Time () tcklz Clock Low-Z Time () teb Clock to EOB tbl a Sequential Port: AC Electrical Characteristics Over the Operating Temperature and Supply Voltage (1,) 78X 78X 78X 78X4 Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit WRITE CYCLE tcyc Sequential Clock Cycle Time 4 tfs Flow Restart Time 1 1 Chip Select and Read/Write Set-up Time 6 6 Chip Select and Read/Write Hold Time tds Input Data Set-up Time 6 6 Input Data Hold Time 16 tbl a 1. 'X' in part number indicates power rating (S or L).. Traition measured at mv from steady state. This parameter is guaranteed with the AC Output Test Load (Figure 1) by device characterization, but is not production tested.. Industrial temperature: for specific speeds, packages and powers contact your sales office. 14

15 Sequential Port: AC Electrical Characteristics Over the Operating Temperature and Supply Voltage (1,) 78X 78X 78X 78X4 Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit RESET CYCLE trspw Reset Pulse Width 1 1 twers Write Enable HIGH to Reset HIGH trsrc Reset HIGH to Write Enable LOW trsfv Reset HIGH to Flag Valid 1 NOTE: 1. 'X' in part number indicates power rating (S or L).. Industrial temperature: for specific speeds, packages and powers contact your sales office. 16 tbl 4a Sequential Port: Write, Pointer Load Non-Incrementing Read tcyc tch tcl CNTEN () () SLD (1) SI/OIN Dx tds A HIGH IMPEDANCE SR/W SCE SOE tcd tsoe tcsz tckhz tolz tohz SI/OOUT D D D 1. If SLD = VIL, then address will be clocked in on the 's rising edge.. If CNTEN = VIH for the 's rising edge, the internal address counter will not advance.. Pointer is not incremented on cycle immediately following SLD even if CNTEN is LOW. tcklz 16 drw

16 Sequential Port: Write, Pointer Load, Burst Read CNTEN tch tcyc tcl () () SLD (1) SI/OIN Dx tds A HIGH IMPEDANCE tds D SR/W SCE tcd SOE tsoe SI/OOUT tolz tcklz D D1 tohz () 16 drw If SLD = VIL, then address will be clocked in on the 's rising edge.. If CNTEN = VIH for the 's rising edge, the internal address counter will not advance.. Pointer is not incremented on cycle immediately following SLD even if CNTEN is LOW. Read STRT/EOB Flag Timing - Sequential Port (1) tcyc tch tcl (4) CNTEN SSTRT1/ (1) HIGH IMPEDANCE SI/OIN Dx () tds D SR/W SCE () SOE SI/OOUT EOB1/ tolz tsoe () tcd tcklz D 16 D1 teb D tohz () 16 drw19 (Also used in the Figure "Read STRT/EOB Flag Timing") 1. If SSTRT1 or SSTRT = VIL, then address will be clocked in on the 's rising edge.. If CNTEN = VIH for the 's rising edge, the internal address counter will not advance.. SOE will control the output and should be HIGH on power-up. If SCE = VIL and is clocked in while SR/W = VIH, the data addressed will be read out within that cycle. If SCE = VIL and is clocked in while SR/W = VIL, the data addressed will be written to if the last cycle was a read. SOE may be used to control the bus contention and permit a write on this cycle. 4. Unlike SLD case, CNTEN is not disabled on cycle immediately following SSTRT.. If SR/W = VIL, data would be written to D again since CNTEN = VIH. 6. SOE = VIL makes no difference at this point since the SR/W = VIL disables the output until SR/W = VIH is clocked in on the next rising clock edge.

17 Waveform of Write Cycles: Sequential Port CNTEN tcyc tch tcl () (4) SLD (1) SI/OIN Dx tds A tds D HIGH IMPEDANCE tds D1 SR/W (4) SCE SOE () tcd tckhz SI/OOUT tcklz D tohz HIGH IMPEDANCE 16 drw Waveform of Burst Write Cycles: Sequential Port tch tcyc tcl CNTEN () () SLD (1) tds tds SI/OIN Dx A D D1 D SR/W () SCE SOE () tcklz SI/OOUT HIGH IMPEDANCE NOTES : 1. If SLD = VIL, then address will be clocked in on the 's rising edge.. If CNTEN = VIH for the 's rising edge, the internal address counter will not advance.. Pointer is not incrementing on cycle immediately following SLD even if CNTEN is LOW. 4. If SR/W = VIL, data would be written to D again since CNTEN = VIH.. SOE = VIL makes no difference at this point since the SR/W = VIL disables the output until SR/W = VIH is clocked in on the next rising clock edge. tcd 16 drw 1 D

18 Waveform of Write Cycles: Sequential Port (STRT/EOB Flag Timing) tch tcl CNTEN (4) () SSTRT1/ (1) SI/OIN Dx D tds D1 D D HIGH IMPEDANCE SR/W () SCE () SOE (6) tcklz tcd SI/OOUT HIGH IMPEDANCE D EOB1/ teb 16 drw (Also used in the Figure "Read STRT/EOB Flag Timing") 1. If SSTRT1 or SSTRT = VIL, then address will be clocked in on the 's rising edge.. If CNTEN = VIH for the 's rising edge, the internal address counter will not advance.. SOE will control the output and should be HIGH on power-up. If SCE = VIL and is clocked in while SR/W = VIH, the data addressed will be read out within that cycle. If SCE = VIL and is clocked in while SR/W = VIL, the data addressed will be written to if the last cycle was a read. SOE may be used to control the bus contention and permit a write on this cycle. 4. Unlike SLD case, CNTEN is not disabled on cycle immediately following SSTRT.. If SR/W = VIL, data would be written to D again since CNTEN = VIH. 6. SOE = VIL makes no difference at this point since the SR/W = VIL disables the output until SR/W = VIH is clocked in on the next rising clock edge. 18

19 Sequential Counter Enable Cycle After Reset, Write Cycle (1,4,6) RST CNTEN () SI/OIN D D1 D D D4 16 drw Sequential Counter Enable Cycle After Reset, Read Cycle (1,4) RST SR/W () CNTEN () SI/OOUT D () D1 D D 16 drw 4 1. 'D' represents data input for Address=, 'D1' represents data input for Address=1, etc. 1. If CNTEN=VIL then 'D1' would be written into 'A1' at this point.. Data output is available at a tcd after the SR/W=VIH is clocked. The RST sets SR/W=LOW internally and therefore disables the output until the next clock. 4. SCE=VIL throughout all cycles.. If CNTEN=VIL then 'D1' would be clocked out (read) at this point. 6. SR/W=VIL

20 Random Access Port - Reset Timing trspw RST trsrc R/W, SR/WCMD or (UB + LB) (4) twers trsfv EOB(1 or ) Flag Valid 16 drw Random Access Port Restart Timing of Sequential Port (1). x tcyc tfs R/W () CLR Block () (Internal Signal) 16 drw 6 1. The sequential port is in the STOP mode and is being restarted from the random port by the Bit 4 Counter Release (see Case ).. "" is written to Bit 4 from the random port at address [A - A] =, when CMD = VIL and CE = VIH. The device is in the Buffer Command Mode (see Case ).. CLR is an internal signal only and is shown for reference only. 4. Sequential port must also prohibit SR/W or SCE from being LOW for twers and trsrc periods, or must not toggle from LOW-to-HIGH until after trsrc.

21 Ordering Information 78 Device Type X Power XX Speed X Package X Process/ Temperature Range Blank I (1) B G PF Commercial ( C to+7 C) Industrial (-4 C to+8 C) Military ( C to +1 C) Compliant to MIL-PRF-8 QML 84-pin PGA (G84-) 8-pin TQFP (PN8-1) 4 S L Commercial Only Commercial Only Commercial & Military Commercial & Military Standard Power Low Power Speed in nanoseconds NOTE: 1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office K (8K x 16) Sequential Access Random Access Memory 16 drw 7, Datasheet Document History 1/7/99: Initiated datasheet document history Converted to new format 6/4/99: Changed drawing format 11//99: Replaced IDT logo 4/18/: Page Changed "Clock" to "Inputs/Outputs" in Random pin description table Added "Outputs" in Sequential pin description table Changed ±mv to mv in notes //: Page 4 Increased storage temperature parameter Clarified TA parameter Page DC Electrical parameters changed wording from "open" to "disabled" 1/9/9: Page 1 Removed "IDT" from orderable part number CORPORATE HEADQUARTERS for SALES: for Tech Support: 64 Silver Creek Valley Road or San Jose, CA 918 fax: DualPortHelp@idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc