HIGH-SPEED 3.3V 1K X 8 DUAL-PORT STATIC RAM

Transcription

1 HIGH-PEED 3.3V 1K X 8 DUA-PORT TATIC RAM Features High-speed access Commercial: //55 (max.) ow-power operation IDT71V Active: 3mW (typ.) tandby: 5mW (typ.) IDT71V Active: 3mW (typ.) tandby: 1mW (typ.) Functional Block Diagram On-chip port arbitration logic Interrupt flags for port-to-port communication Fully asynchronous operation from either port Battery backup operation, 2V data retention ( Only) TT-compatible, single 3.3V ±.3V power supply Industrial temperature range (-4 O C to +85 O C) is available for selected speeds Green parts available, see ordering information OE CE R/W OER CER R/WR I/O- I/O7 I/O Control I/O Control I/OR-I/O7R BUY (1) (1) BUYR A9 A Address Decoder MEMORY ARRAY Address Decoder A9R AR 1 1 CE OE R/W ARBITRATION and INTERRUPT OGIC CER OER R/WR INT (2) 1. IDT71V: BUY outputs are non-tristatable push-pulls. 2. INT outputs are non-tristable push-pull output structure drw 1 INTR (2) 8 Integrated Device Technology, Inc. 1 OCTOBER 8 DC 3741/1

2 Description The IDT71V is a high-speed 1K x 8 Dual-Port tatic RAM. The IDT71V is designed to be used as a stand-alone 8-bit Dual-Port RAM. Both devices provide two independent ports with separate control, address, and I/O pi that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMO high-performance technology, these devices typically operate on only 3mW of power. ow-power () versio offer battery backup data retention capability, with each Dual- Port typically couming µw from a 2V battery. The IDT71V devices are packaged in 64-pin TQFPs. Pin Configuratio (1,2,3) INDEX INT BUY R/W CE VCC VCC CER R/WR BUYR INTR OE A A1 A2 A3 A4 A5 A6 A7 A8 A9 I/O I/O1 I/O IDT71VTF PP64-1 (4) 64-Pin TQFP Top View (5) OER A R A 1R A 2R A 3R A 4R A 5R A 6R A 7R A 8R A 9R I/O7R I/O 6R, I/O3 I/O4 I/O5 I/O6 I/O7 GND GND I/OR I/O1R I/O2R I/O3R I/O4R I/O5R 3741 drw 3 1. All VCC pi must be connected to the power supply. 2. All GND pi must be connected to the ground supply. 3. Package body is approximately 1mm x 1mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate the orientation of the actual part-marking

3 Absolute Maximum Ratings (1) ymbol Rating Com'l & Ind Unit VTERM (2) TBIA TTG Terminal Voltage with Respect to GND Temperature Under Bias torage Temperature -.5 to +4.6 V -55 to +1 o C -65 to +15 o C TJN (3) Junction Temperature +15 o C IOUT DC Output Current 5 ma 1. tresses greater than those listed under ABOUTE MAXIMUM RATING may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio above those indicated in the operational sectio of the specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect reliability. 2. VTERM must not exceed Vcc +.3V for more than % of the cycle time or 1 maximum, and is limited to < ma for the period of VTERM > Vcc +.3V. 3. This is the absolute maximum junction temperature for the device. No DC Bias. Capacitance (1) (TA = + O C, f=1.mhz) 3741 tbl 1 ymbol Parameter Conditio (2) Max. Unit Recommended DC Operating Conditio ymbol Parameter Min. Typ. Max. Unit VCC upply Voltage V GND Ground V VIH Input High Voltage 2. VCC+.3V V VI Input ow Voltage -.3 (1).8 V NOTE: 1. VI (min.) = -1.5V for pulse width less than. Maximum Operating Temperature and upply Voltage (1,2) Grade Ambient Temperature GND Vcc Commercial O C to +7 O C V 3.3V +.3 Industrial -4 O C to +85 O C V 3.3V This is the parameter TA. This is the "itant on" case temperature. 2. Industrial temperature: for specific speeds, packages and powers, contact your sales office tbl tbl 3 CIN Input Capacitance VIN = 3dV 9 pf COUT (3) Output Capacitance VOUT = 3dV 1 pf 3741 tbl 4 1. This parameter is determined by device characterization but is not production tested. 2. 3dv references the interpolated capacitance when the input and output signals switch from V to 3V or from 3V to V. DC Electrical Characteristics Over the Operating Temperature and upply Voltage Range (VCC = 3.3V ±.3V) 71V 71V ymbol Parameter Test Conditio Min. Max. Min. Max. Unit II Input eakage Current (1) VCC = 3.6V, VIN = V to VCC 1 5 µa IO Output eakage Current CE = VIH, VOUT = V to VCC 1 5 µa VO Output ow Voltage (I/O-I/O7) IO = 4mA.4.4 V VOH Output High Voltage IOH = -4mA V NOTE: 1. At Vcc < 2.V input leakages are undefined. upply CurrentVIN > VCC -.2V or <.2V 3741 tbl

4 DC Electrical Characteristics Over the Operating Temperature and upply Voltage Range (1,6,7) (VCC = 3.3V ±.3V) 71VX 71VX 71VX55 ymbol Parameter Test Condition Version ICC IB1 IB2 IB3 IB4 Dynamic Operating Current (Both Ports Active) tandby Current (Both Ports - TT evel Inputs) tandby Current (One Port - TT evel Inputs) Full tandby Current (Both Ports - CMO evel Inputs) Full tandby Current (One Port - CMO evel Inputs) CE and CER = VI, Outputs Disabled f = fmax (3) COM' IND CE and CER= VI, COM' f = fmax (3) CE"A" = VI and CE"B" = VIH (5) Active Port Outputs Disabled, f=fmax (3) CE and CER > VCC -.2V VIN > VCC -.2V or VIN <.2V, f = (4) CE"A" <.2V and CE"B" > VCC -.2V (5) VIN > VCC -.2V or VIN <.2V Active Port Outputs Disabled f=fmax (3) IND COM' IND COM' IND COM' IND Typ. (2) Max. Typ. (2) Max. Typ. (2) Max Unit ma ma ma ma ma 1. 'X' in part number indicates power rating ( or ) 2. VCC = 3.3V, TA = + C, and are not production tested. ICCDC = 7mA (Typ.) 3. At f = fmax, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC. 4. f = mea no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 6. Refer to chip enable Truth Table I. 7. Industrial temperature: for specific speeds, packages and powers contact your sales office tbl 6 Data Retention Characteristics ( Version Only) ymbol Parameter Test Condition 71V Min. Typ. (1) Max. Unit VDR VCC for Data Retention 2. V ICCDR Data Retention Current Ind. µa VCC = 2V, CE > VCC -.2V Com'l tcdr (3) Chip Deselect to Data Retention Time VIN > VCC -.2V or VIN <.2V tr (3) Operation Recovery Time trc (2) 1. VCC = 2V, TA = + C, and is not production tested. 2. trc = Read Cycle Time. 3. This parameter is guaranteed by device characterization but not production tested tbl

5 AC Test Conditio Input Pulse evels Input Rise/Fall Times Input Timing Reference evels Output Reference evels Output oad GND to 3.V 3 Max. 1.5V 1.5V Figures 1 and tbl 8 Data Retention Waveform DATA RETENTION MODE VCC 3.V VDR 2.V 3.V CE tcdr VDR tr VIH VIH 3741 drw 4, 3.3V 3.3V 59Ω 59Ω DATA OUT BUY INT 4Ω pf DATA OUT 4Ω 5pF 3741 drw 5 Figure 1. AC Output Test oad Figure 2. Output Test oad (For thz, tz, twz and tow) * Including scope and jig. AC Electrical Characteristics Over the Operating Temperature and upply Voltage Range (3,4) 71VX 71VX 71VX55 ymbol Parameter Min. Max. Min. Max. Min. Max. Unit READ CYCE trc Read Cycle Time 55 taa Address Access Time 55 tace Chip Enable Access Time 55 taoe Output Enable Access Time 12 toh Output Hold from Address Change tz Output ow-z Time (1,2) thz Output High-Z Time (1,2) tpu Chip Enable to Power Up Time (2) tpd Chip Disable to Power Down Time (2) Traition is measured mv from ow- or High-impedance voltage with Output Test oad (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. 'X' in part number indicates power rating ( or ). 4. Industrial temperature: for specific speeds, packages and power contact your sales office tbl

6 Timing Waveform of Read Cycle No. 1, Either ide (1) ADDRE trc taa toh toh DATAOUT BUYOUT PREVIOU DATA VAID DATA VAID tbdd (2,3) 3741 drw 6 1. R/W = VIH, CE = VI, and is OE = VI. Address is valid prior to the coincidental with CE traition OW. 2. tbdd delay is required only in case where the opposite is port is completing a write operation to same the address location. For simultaneous read operatio BUY has no relatiohip to valid output data. 3. tart of valid data depends on which timing becomes effective last taoe, tace, taa, and tbdd. Timing Waveform of Read Cycle No. 2, Either ide (3) CE tace (4) taoe (2) thz OE (1) tz (2) thz DATAOUT ICC CURRENT tpu 5% (1) tz VAID DATA (4) tpd 5% I 3741 drw 7 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is desserted first, OE or CE. 3. R/W = VIH and the address is valid prior to or coincidental with CE traition OW. 4. tart of valid data depends on which timing becomes effective last taoe, tace, and tbdd

7 AC Electrical Characteristics Over the Operating Temperature and upply Voltage (4,5) 71VX 71VX 71VX55 ymbol Parameter Min. Max. Min. Max. Min. Max. Unit WRITE CYCE twc Write Cycle Time 55 tew Chip Enable to End-of-Write 4 taw Address Valid to End-of-Write 4 ta Address et-up Time twp Write Pulse Width 4 twr Write Recovery Time tdw Data Valid to End-of-Write 12 thz Output High-Z Time (1,2) tdh Data Hold Time (3) twz Write Enable to Output in High-Z (1,2) tow Output Active from End-of-Write (1, 2,3) 3741 tbl 1 1. Traition is measured mv from ow- or High-impedance voltage with Output Test oad (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. The specification for tdh must be met by the device supplying write data to the RAM under all operating conditio. Although tdh and tow values will vary over voltage and temperature, the actual tdh will always be smaller than the actual tow. 4. 'X' in part number indicates power rating ( or ). 5. Industrial temperatures: for specific speeds, packages and powers contact your sales office

8 Timing Waveform of Write Cycle No. 1,(R/W Controlled Timing) (1,5,8) ADDRE OE CE taw twc (7) thz (6) ta twp (2) (3) twr (7) thz R/W twz (7) tow DATA OUT (4) (4) tdw tdh DATA IN 3741 drw 8 Timing Waveform of Write Cycle No. 2, CE Controlled Timing (1,5) twc ADDRE taw CE (6) (2) (3) ta tew twr R/W tdw tdh DATA IN 3741 drw 9 1. R/W or CE must be HIGH during all address traitio. 2. A write occurs during the overlap (tew or twp) of CE = VI and R/W= VI. 3. twr is measured from the earlier of CE or R/W going HIGH to the end of the write cycle. 4. During this period, the l/o pi are in the output state and input signals must not be applied. 5. If the CE OW traition occurs simultaneously with or after the R/W OW traition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal (CE or R/W) is asserted last. 7. This parameter is determined be device characterization, but is not production tested. Traition is measured mv from steady state with the Output Test oad (Figure 2). 8. If OE is OW during a R/W controlled write cycle, the write pulse width must be the larger of twp or (twz + tdw) to allow the I/O drivers to turn off data to be placed on the bus for the required tdw. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twp

9 AC Electrical Characteristics Over the Operating Temperature and upply Voltage Range (6,7) 71VX 71VX 71VX55 ymbol Parameter Min. Max. Min. Max. Min. Max. BUY TIMING (M/=VIH) Unit tbaa BUY Access Time from Address Match tbda BUY Disable Time from Address Not Matched tbac BUY Access Time from Chip Enable tbdc BUY Disable Time from Chip Enable twh Write Hold After BUY (5) 4 twdd Write Pulse to Data Delay (1) tddd Write Data Valid to Read Data Delay (1) tap Arbitration Priority et-up Time (2) tbdd BUY Disable to Valid Data (3) Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read with BUY". 2. To eure that the earlier of the two ports wi. 3. tbdd is a calculated parameter and is the greater of, twdd twp (actual) or tddd tdw (actual). 4. To eure that the Write Cycle is inhibited on Port B during contention on Port A. 5. To eure that the Write Cycle is completed on Port B after contention on Port A. 6. 'X' in part number indicates power rating ( or ). 7. Industrial temperature: for specific speeds, packages and powers contact your sales office tbl 11 Timing Waveform of Write with Port-to-Port Read with BUY (1,2,3,4) twc ADDR"A" MATCH twp R/W"A" DATAIN"A" ADDR"B" tap (1) tdw VAID MATCH tdh tbda tbdd BUY"B" twdd DATAOUT"B" 1. To eure that the earlier of the two ports wi. 2. CE = CER = VI 3. OE = VI for the reading port. 4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A". tddd VAID 3741 drw

10 Timing Waveform of Write with BUY (3) twp R/W'A' twb BUY'B' R/W'B' (2) (1) twh, 1. twh must be met for BUY drw BUY is asserted on port 'B' blocking R/W'B', until BUY'B' goes HIGH. 3. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A". Timing Waveform of BUY Arbitration Controlled by CE Timing (1) ADDR 'A' AND 'B' ADDREE MATCH CE'B' (2) tap CE'A' BUY'A' tbac tbdc 3741 drw All timing is the same for left and right ports. Port A may be either left or right port. Port B is the opposite from port A. 2. If tap is not satisified, the BUY will be asserted on one side or the other, but there is no guarantee on which side BUY will be asserted. Timing Waveform of BUY Arbitration Controlled Address Match Timing (1) trc OR twc ADDR'A' ADDR'B' (2) tap ADDREE MATCH ADDREE DO NOT MATCH BUY'B' tbaa tbda 3741 drw All timing is the same for left and right ports. Port A may be either left or right port. Port B is the opposite from port A. 2. If tap is not satisified, the BUY will be asserted on one side or the other, but there is no guarantee on which side BUY will be asserted

11 AC Electrical Characteristics Over the Operating Temperature and upply Voltage Range (1,2) 71VX 71VX 71VX55 ymbol Parameter Min. Max. Min. Max. Min. Max. Unit INTERRUPT TIMING ta Address et-up Time twr Write Recovery Time tin Interrupt et Time 45 tinr Interrupt Reset Time 'X' in part number indicates power rating ( or ). 2. Industrial temperature: for specific speeds, packages and powers contact your sales office tbl 12 Timing Waveform of Interrupt Mode (1) INT ets twc ADDR'A' (3) ta INTERRUPT ADDRE (2) (4) twr R/W'A' INT'B' (3) tin 3741 drw 14 INT Clears trc ADDR'B' ta (3) INTERRUPT CEAR ADDRE OE'B' (3) tinr INT'A' 3741 drw All timing is the same for left and right ports. Port A may be either left or right port. Port B is the opposite from port A. 2. ee Interrupt Truth Table II. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first

12 Truth Tables Table I. Non-Contention Read/Write Control (4) eft or Right Port (1) R/W CE OE D-7 Function X H X Z Port Disabled and in Power-Down Mode, IB2 or IB4 X H X Z CER = CE = VIH, Power-Down Mode, IB1 or IB3 X DATAIN Data on Port Written Into Memory (2) H DATAOUT Data in Memory Output on Port (3) H H Z High Impedance Outputs 1. A A9 AR A9R. 2. If BUY =, data is not written. 3. If BUY =, data may not be valid, see twdd and tddd timing. 4. 'H' = VIH, '' = VI, 'X' = DON T CARE, 'Z' = HIGH IMPEDANCE 3741 tbl 13 Table II. Interrupt Flag (1,4) eft Port Right Port R/W CE OE A9-A INT R/WR CER OER A9R-AR INTR Function X 3FF X X X X X (2) et Right INTR Flag X X X X X X 3FF H (3) Reset Right INTR Flag X X X X (3) X 3FE X et eft INT Flag X 3FE H (2) X X X X X Reset eft INT Flag 1. Assumes BUY = BUYR = VIH 2. If BUY = VI, then No Change. 3. If BUYR = VI, then No Change. 4. 'H' = HIGH,' ' = OW,' X' = DON T CARE 3741 tbl 14 Table III Address BUY Arbitration Inputs Outputs CE CER AO-A9 AOR-A9R BUY (1) BUYR (1) Function X X NO MATCH H H Normal H X MATCH H H Normal X H MATCH H H Normal MATCH (2) (2) Write Inhibit (3) 3741 tbl Pi BUY and BUYR are both outputs for IDT71V. BUYX outputs on the IDT71V are non-tristatable push-pull. 2. '' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address and enable inputs of this port. If tap is not met, either BUY or BUYR = OW will result. BUY and BUYR outputs can not be OW simultaneously. 3. Writes to the left port are internally ignored when BUY outputs are driving OW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUYR outputs are driving OW regardless of actual logic level on the pin

13 Functional Description The IDT71V provides two ports with separate control, address and I/O pi that permit independent access for reads or writes to any location in memory. The IDT71V has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE = VIH). When a port is enabled, access to the entire memory array is permitted. Interrupts If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INT) is asserted when the right port writes to memory location 3FE (HEX), where a write is defined as the CE = R/W = VI per Truth Table II. The left port clears the interrupt by accessing address location 3FE access with CER = OER = VI, R/W is a "don't care". ikewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 3FF (HEX) and to clear the interrupt flag (INTR), the right port must access the memory location 3FF. The message (8 bits) at 3FE or 3FF is user-defined, since it is an addressable RAM location. If the interrupt function is not used, address locatio 3FE and 3FF are not used as mail boxes, and are part of the random access memory. Refer to Table II for the interrupt operation. Busy ogic Busy ogic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is Busy. The BUY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUY logic is not required or desirable for all applicatio. In some cases it may be useful to logically OR the BUY outputs together and use any BUY indication as an interrupt source to flag the event of an illegal or illogical operation

14 Ordering Information XXXX Device Type A 999 A A A Power peed Package Process/ Temperature Range Blank I (1) Commercial ( C to +7 C) Industrial (-4 C to +85 C) G (2) Green TF 64-pin TQFP (PP64-1) 55 Commercial Only Commercial Only Commercial Onlyl peed in nanoseconds ow Power tandard Power 71V 8K (1K X 8-Bit) MATER Dual-Port RAM NOTE: 1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office. 2. Green parts available. For specific speeds, packages and powers contact your sales office drw 16 Datasheet Document History 12/9/98: Initiated datasheet document history Converted to new format Cosmetic and typographical correctio Added additional notes to pin configuratio 6/15/99: Changed drawing format 8/3/99: Page 2 Fixed typographical error 9/1/99: Removed Preliminary 11/12/99: Replaced IDT logo 1/17/1: Pages 1 and 2 Moved all of "Description" to page 2 and adjusted page layouts Page 3 Increased storage temperature parameters Clarified TA parameter Page 4 DC Electrical parameters changed wording from "open" to "disabled" Changed ±mv to mv in notes 3/14/5: Page 1 Added green availability to features Page 17 Added green indicator to ordering information Page 1 & 17 Replaced old TM logo with new TM logo 7/16/7: Page 3 Added Junction Temperature spec values to the Absolute Maximum Rating table Added footnote 3 for additional clarification of Junction Temperature 1/23/8: Page 14 Removed "IDT" from orderable part number CORPORATE HEADQUARTER for AE: for Tech upport: 624 ilver Creek Valley Road or an Jose, CA fax: DualPortHelp@idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc