HIGH SPEED 2K X 8 DUAL-PORT STATIC RAM WITH INTERRUPTS

Transcription

1 Features High-speed access Commercial: //35/55 (max.) Industrial: /55 (max.) Low-power operation IDT71321/IDT71421 Active: 3mW (typ.) Standby: 5mW (typ.) IDT71321/421 Active: 3mW (typ.) Standby: 1mW (typ.) Two INT flags for port-to-port communicatio Functional Block Diagram HIGH SPEED 2K X 8 DUAL-PORT STATIC RAM WITH INTERRUPTS IDT71321/ IDT71421/ LEAD FINISH (SnPb) ARE IN EOL PROCESS - ST TIME BUY EXPIRES JUNE 15, 18 MASTER IDT71321 easily expands data bus width to 16-ormore-bits using SVE IDT71421 On-chip port arbitration logic (IDT71321 only) BUSY output flag on IDT71321; BUSY input on IDT71421 Fully asynchronous operation from either port Battery backup operation 2V data retention ( only) TTL-compatible, single 5V ±1% power supply Available in 52-Pin PLCC, 52-Pin STQFP, 64-Pin TQFP, and 64-Pin STQFP Industrial temperature range ( 4 C to +85 C) is available for selected speeds Green parts available, see ordering information OEL OER CEL R/WL CER R/WR I/OL- I/O7L I/O Control I/O Control I/OR-I/O7R BUSYL (1,2) (1,2) BUSYR A1L AL Address Decoder MEMORY ARRAY Address Decoder A1R AR CEL OEL R/WL ARBITRATION and INTERRUPT LOGIC CER OER R/WR INTL (2) 1. IDT71321 (MASTER): BUSY is open drain output and requires pullup resistor of 27Ω. IDT71421 (SVE): BUSY is input. 2. Open drain output: requires pullup resistor of 27Ω. INTR 2691 drw 1 (2) 18 Integrated Device Technology, Inc. 1 FEBRUARY 18 DSC-2691/16

2 IDT71321/ and IDT71421/ Description The IDT71321/IDT71421 are high-speed 2K x 8 Dual-Port Static RAMs with internal interrupt logic for interprocessor communicatio. The IDT71321 is designed to be used as a stand-alone 8-bit Dual- Port Static RAM or as a "MASTER" Dual-Port Static RAM together with the IDT71421 "SVE" Dual-Port in 16-bit-or-more word width systems. Using the IDT MASTER/SVE Dual-Port Static RAM approach in 16-or-more-bit memory system applicatio results in full speed, error-free operation without the need for additional discrete logic. Both devices provide two independent ports with separate control, Pin Configuratio (1,2,3) address, and I/O pi that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Fabricated using CMOS high-performance technology, these devices typically operate on only 3mW of power. Low-power () versio offer battery backup data retention capability, with each Dual- Port typically couming µw from a 2V battery. The IDT71321/IDT71421 devices are packaged in 52-pin PLCC, 52-pin STQFP, 64-pin TQFP, and 64-pin STQFP. I/O 3L I/O 2L I/O 1L I/O L A 9L A 8L A 7L A 6L A 5L A 4L A 3L A 2L A 1L I/O 4L I/O 5L I/O 6L I/O 7L NC GND I/O R I/O 1R I/O 2R I/O 3R I/O 4R I/O 5R I/O 6R /421 J52 (4) A L OEL A 1L INT L BUSYL R/W L CEL V CC CER R/W R BUSYR INT R A 1R I/O 7R NC A 9R A 8R A 7R A 6R A 5R A 4R A 3R A 2R A 1R A R OER 2691 drw 2 OER AR A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O7R I/O6R 1. All VCC pi must be connected to power supply. 2. All GND pi must be connected to ground supply. 3. J52 package body is approximately.75 in x.75 in x.17 in. PN64 package body is approximately 14mm x 14mm x 1.4mm. PP64 package body is approximately 1mm x 1mm x 1.4mm. 4. This package code is used to reference the package diagram. A1R INTR BUSYR R/WR CER VCC VCC CEL R/WL BUSYL INTL A1L EX OEL AL A1L A2L A3L A4L A5L A6L A7L A8L A9L / PN64 / PP64 (4) I/OL I/O1L I/O2L I/O5R I/O4R I/O3R I/O2R I/O1R I/OR GND GND I/O7L I/O6L I/O5L I/O4L I/O3L 2691 drw

3 IDT71321/ and IDT71421/ Pin Configuratio (continued) (1,2,3) AL OEL A1L INTL BUSYL R/WL CEL VCC CER R/WR BUSYR INTR A1R EX A1L A2L A3L A4L A5L A6L A7L A8L A9L I/OL I/O1L I/O2L I/O3L /421 PP52 (4) OER AR A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O7R 1. All VCC pi must be connected to power supply. 2. All GND pi must be connected to ground supply. 3. PP52 package body is approximately 1mm x 1mm x 1.4mm. 4. This package code is used to reference the package diagram., 2691 drw 3a I/O4L I/O5L I/O6L I/O7L GND I/OR I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R Capacitance (1) (TA = + C, f = 1.MHz) TQFP Only Symbol Parameter Conditio (2) Max. Unit 1. This parameter is determined by device characterization but is not production tested. 2. 3dv references the interpolated capacitance when the input and output signals switch from V to 3V or from 3V to V. Absolute Maximum Ratings (1) Symbol Rating Commercial ustrial VTERM (2) TBIAS TSTG IOUT CIN Input Capacitance VIN = 3dV 9 pf COUT Output Capacitance VOUT = 3dV 1 pf Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature DC Output Current 2691 tbl Unit -.5 to +7. V -55 to +1 o C - to +15 o C 5 Recommended Operating Temperature and Supply Voltage (1,2) Grade Ambient Temperature GND 1. This is the parameter TA. This is the "itant on" case temperature. 2. Industrial temperature: for specific speeds, packages and powers contact your sales office. Recommended DC Operating Conditio Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage V GND Ground V VIH Input High Voltage (2) V VIL Input Low Voltage -.5 (1).8 V 1. VIL (min.) = -1.5V for pulse width less than VTERM must not exceed Vcc + 1%. Vcc Commercial O C to +7 O C V 5.V + 1% Industrial -4 O C to +85 O C V 5.V + 1% 2691 tbl tbl tbl 1 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio above those indicated in the operational sectio of the specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect reliability. 2. VTERM must not exceed VCC + 1% for more than % of the cycle time or 1 maximum, and is limited to < for the period of VTERM > VCC + 1%

4 IDT71321/ and IDT71421/ DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (1,4) (VCC = 5.V ± 1%) 71321X 71421X 71321X 71421X Symbol Parameter Test Condition Version Typ. Max. Typ. Max. Unit ICC ISB1 ISB2 ISB3 Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports - CMOS Level Inputs) CEL and CER = VIL, Outputs Disabled f = fmax (2) COM'L CEL and CER = VIH COM'L f = fmax (2) CE"A" = VIL and CE"B" = VIH (5) Active Port Outputs Disabled, f=fmax (2) CEL and CER > VCC -.2V, VIN > VCC -.2V or VIN <.2V, f = (3) COM'L COM'L ISB4 Full Standby Current (One Port - CMOS Level Inputs) CE"A" <.2V and CE"B" > VCC -.2V (5) VIN > VCC -.2V or VIN <.2V Active Port Outputs Disabled, f = fmax (2) COM'L tbl 4a 71321X X X X55 Symbol Parameter Test Condition Version Typ. Max. Typ. Max. Unit ICC ISB1 ISB2 ISB3 Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports - CMOS Level Inputs) CEL and CER = VIL, Outputs Disabled f = fmax (2) COM'L CEL and CER = VIH COM'L f = fmax (2) CE"A" = VIL and CE"B" = VIH (5) Active Port Outputs Disabled, f=fmax (2) CEL and CER > VCC -.2V, VIN > VCC -.2V or VIN <.2V, f = (3) COM'L COM'L ISB4 Full Standby Current (One Port - CMOS Level Inputs) CE"A" <.2V and CE"B" > VCC -.2V (5) VIN > VCC -.2V or VIN <.2V Active Port Outputs Disabled, f = fmax (2) COM'L tbl 4b 1. 'X' in part numbers indicates power rating ( or ). 2. At f = fmax, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using AC TEST CONDITIONS of input levels of GND to 3V. 3. f = mea no address or control lines change. Applies only to inputs at CMOS level standby. 4. Vcc = 5V, TA=+ C for Typ and is not production tested. Vcc DC = 1 (Typ) 5. Port "A" may be either left or right port. Port "B" is opposite from port "A"

5 IDT71321/ and IDT71421/ DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 5.V ± 1%) Symbol Parameter Test Conditio Min. Max. Min. Max. Unit ILI Input Leakage Current (1) VCC = 5.5V, VIN = V to VCC ILO Output Leakage Current (1) CE = VIH, VOUT = V to VCC, VCC - 5.5V 1 5 µa 1 5 µa VOL Output Low Voltage (I/O-I/O7) IOL = V VOL Open Drain Output Low Voltage (BUSY/INT) IOL = V VOH Output High Voltage IOH = V NOTE: 1. At Vcc < 2.V leakages are undefined tbl 5 Data Retention Characteristics ( Version Only) Symbol Parameter Test Condition Min. Typ. (1) Max. Unit VDR VCC for Data Retention 2. V ICCDR Data Retention Current VCC = 2.V, CE > VCC -.2V COM'L 1 15 µa VIN > VCC -.2V or VIN <.2V 1 4 µa tcdr (3) Chip Deselect to Data Retention Time tr (3) Operation Recovery Time trc (2) 1. VCC = 2V, TA = + C, and is not production tested. 2. trc = Read Cycle Time 3. This parameter is guaranteed but not production tested tbl 6 Data Retention Waveform DATA RETENTION MODE VCC 4.5V VDR 2.V 4.5V tcdr tr CE VIH VDR VIH 2691 drw 4,

6 IDT71321/ and IDT71421/ AC Test Conditio Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.V 5 1.5V 1.5V Figures 1,2 and tbl 7 5V 5V 1Ω 1Ω DATA OUT 775Ω 3pF* DATA OUT 775Ω 5pF* *1pF for 55 versio Figure 1. AC Output Test Load 5V Figure 2. Output Test Load (for thz, tlz, twz, and tow) * Including scope and jig. 27Ω BUSY or INT 2691 drw 5 3pF* *1pF for 55 versio Figure 3. BUSY and INT AC Output Test Load

7 IDT71321/ and IDT71421/ AC Electrical Characteristics Over the Operating Temperature Supply Voltage Range (2) 71321X 71421X 71321X 71421X Symbol Parameter Min. Max. Min. Max. Unit READ CYCLE trc Read Cycle Time taa Address Access Time tace Chip Enable Access Time taoe Output Enable Access Time toh Output Hold from Address Change 3 3 tlz Output Low-Z Time (1,3) thz Output High-Z Time (1,3) 1 1 tpu Chip Enable to Power Up Time (3) tpd Chip Disable to Power Down Time (3) 2691 tbl 8a 71321X X X X55 Symbol Parameter Min. Max. Min. Max. Unit READ CYCLE trc Read Cycle Time taa Address Access Time tace Chip Enable Access Time taoe Output Enable Access Time toh Output Hold from Address Change 3 3 tlz Output Low-Z Time (1,3) 5 thz Output High-Z Time (1,3) 15 tpu Chip Enable to Power Up Time (3) tpd Chip Disable to Power Down Time (3) Traition is measured mv from Low or High-impedance voltage Output Test Load (Figure 2). 2. 'X' in part numbers indicates power rating ( or ). 3. This parameter is guaranteed by device characterization, but is not production tested tbl 8b

8 IDT71321/ and IDT71421/ Timing Waveform of Read Cycle No. 1, Either Side (1) ADDRESS trc taa toh toh DATAOUT BUSYOUT PREVIOUS DATA VALID DATA VALID tbddh (2,3) 2691 drw 6 1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE traition LOW. 2. tbdd delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operatio BUSY has no relatiohip to valid output data. 3. Start of valid data depends on which timing becomes effective last taoe, tace, taa, and tbdd. Timing Waveform of Read Cycle No. 2, Either Side (3) tace CE (4) taoe (2) thz OE (1) (2) tlz thz DATAOUT ICC CURRENT ISS tpu 5% (1) tlz VALID DATA (4) tpd 5% 2691 drw 7 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is de-asserted first, OE or CE. 3. R/W = VIH and OE = VIL, and the address is valid prior to or coincidental with CE traition LOW. 4. Start of valid data depends on which timing becomes effective last taoe, tace, taa, and tbdd

9 IDT71321/ and IDT71421/ AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (4) 71321X 71421X 71321X 71421X Symbol Parameter Min. Max. Min. Max. Unit WRITE CYCLE twc Write Cycle Time (2) tew Chip Enable to End-of-Write 15 taw Address Valid to End-of-Write 15 tas Address Set-up Time twp Write Pulse Width (3) twr Write Recovery Time tdw Data Valid to End-of-Write 1 12 thz Output High-Z Time (1) 1 1 tdh Data Hold Time twz Write Enable to Output in High-Z (1) 1 1 tow Output Active from End-of-Write (1) 2691 tbl 9a 71321X X X X55 Symbol Parameter Min. Max. Min. Max. Unit WRITE CYCLE twc Write Cycle Time (2) tew Chip Enable to End-of-Write 3 4 taw Address Valid to End-of-Write 3 4 tas Address Set-up Time twp Write Pulse Width (3) 3 twr Write Recovery Time tdw Data Valid to End-of-Write 15 thz Output High-Z Time (1) 15 tdh Data Hold Time twz Write Enable to Output in High-Z (1) 15 3 tow Output Active from End-of-Write (1) 2691 tbl 9b 1. Traition is measured mv from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by device characterization but is not production tested. 2. For Master/Slave combination, twc = tbaa + twp, since R/W = VIL must occur after tbaa. 3. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of twp or (twz + tdw) to allow the I/O drivers to turn off data to be placed on the bus for the required tdw. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twp. 4. 'X' in part numbers indicates power rating ( or )

10 IDT71321/ and IDT71421/ Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing) (1,5,8) twc ADDRESS thz (7) OE taw CE tas (6) twp (2) twr (3) thz (7) R/W twz (7) tow DATA OUT (4) (4) tdw tdh DATA IN 2691 drw 8 Timing Waveform of Write Cycle No. 2, (CE Controlled Timing) (1,5) ADDRESS CE R/W twc taw tas (6) tew (2) (3) twr tdw tdh DATAIN 2691 drw 9 1. R/W or CE must be HIGH during all address traitio. 2. A write occurs during the overlap (tew or twp) of CE = VIL and R/W= VIL. 3. twr is measured from the earlier of CE or R/W going HIGH to the end of the write cycle. 4. During this period, the l/o pi are in the output state and input signals must not be applied. 5. If the CE LOW traition occurs simultaneously with or after the R/W LOW traition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal (CE or R/W) is asserted last. 7. This parameter is determined to be device characterization, but is not production tested. Traition is measured mv from steady state with the Output Test Load (Figure 2). 8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of twp or (twz + tdw) to allow the I/O drivers to turn off data to be placed on the bus for the required tdw. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twp

11 IDT71321/ and IDT71421/ AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (6) 71321X 71421X 71321X 71421X Symbol Parameter Min. Max. Min. Max. Unit BUSY TIMING (For MASTER 71321) tbaa BUSY Access Time from Address tbda BUSY Disable Time from Address tbac BUSY Access Time from Chip Enable tbdc BUSY Disable Time from Chip Enable twh Write Hold After BUSY (5) twdd Write Pulse to Data Delay (1) 5 5 tddd Write Data Valid to Read Data Delay (1) taps Arbitration Priority Set-up Time (2) 5 5 tbdd BUSY Disable to Valid Data (3) 35 BUSY INPUT TIMING (For SVE 71421) twb Write to BUSY Input (4) twh Write Hold After BUSY (5) twdd Write Pulse to Data Delay (1) 4 5 tddd Write Data Valid to Read Data Delay (1) X X X X55 Symbol Parameter Min. Max. Min. Max. Unit BUSY TIMING (For MASTER 71321) tbaa BUSY Access Time from Address 3 tbda BUSY Disable Time from Address 3 tbac BUSY Access Time from Chip Enable 2691 tbl 1a 3 tbdc BUSY Disable Time from Chip Enable 3 twh Write Hold After BUSY (5) twdd Write Pulse to Data Delay (1) 6 8 tddd Write Data Valid to Read Data Delay (1) taps Arbitration Priority Set-up Time (2) 5 5 tbdd BUSY Disable to Valid Data (3) 35 5 BUSY INPUT TIMING (For SVE 71421) twb Write to BUSY Input (4) twh Write Hold After BUSY (5) twdd Write Pulse to Data Delay (1) 6 8 tddd Write Data Valid to Read Data Delay (1) Port-to-port delay through RAM cells from the writing port to the reading port, refer to Timing Waveform of Write with Port-to-Port Read and BUSY." 2. To eure that the earlier of the two ports wi. 3. tbdd is a calculated parameter and is the greater of, twdd twp (actual) or tddd tdw (actual). 4. To eure that a write cycle is inhibited on port "B" during contention on port "A". 5. To eure that a write cycle is completed on port "B" after contention on port "A". 6. 'X' in part numbers indicates power rating ( or ) tbl 1b

12 IDT71321/ and IDT71421/ Timing Waveform of Write with Port-to-Port Read and BUSY (2,3,4) twc ADDR"A" MATCH twp R/W "A" DATA IN "A" ADDR"B" taps (1) tdw VALID MATCH tdh tbaa tbda tbdd BUSY"B" twdd DATAOUT"B" VALID tddd 1. To eure that the earlier of the two ports wi. taps is ignored for Slave (IDT71421). 2. CEL = CER = VIL 3. OE = VIL for the reading port. 4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A" drw 1 Timing Waveform of Write with BUSY (4) twp R/W"A" (3) twb BUSY"B" R/W"B" (2) (1) twh, 2691 drw twh must be met for both BUSY input (IDT71421, slave) or output (IDT71321, Master). 2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH. 3. twb is only for the slave version (IDT71421). 4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A"

13 IDT71321/ and IDT71421/ Timing Waveform of BUSY Arbitration Controlled by CE Timing (1) ADDR "A" AND "B" ADDRESSES MATCH CE"B" taps (2) CE"A" BUSY"A" tbac tbdc 2691 drw 12 Timing Waveform of BUSY Arbitration Controlled by Address Match Timing (1) trc or twc ADDR"A" ADDR"B" taps (2) ADDRESSES MATCH ADDRESSES DO NOT MATCH BUSY"B" tbaa tbda 1. All timing is the same for left and right ports. Port A may be either left or right port. Port B is the opposite from port A. 2. If taps is not satisfied, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (IDT71321 only) drw 13 AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (1) 71321X 71421X 71321X 71421X Symbol Parameter Min. Max. Min. Max. Unit INTERRUPT TIMING tas Address Set-up Time twr Write Recovery Time tins Interrupt Set Time tinr Interrupt Reset Time NOTE: 1. 'X' in part numbers indicates power rating ( or ) tbl 11a

14 IDT71321/ and IDT71421/ AC Electrical Characteristics Over the Operating Temperature Supply Voltage Range (1) 71321X X X X55 Symbol Parameter Min. Max. Min. Max. Unit INTERRUPT TIMING tas Address Set-up Time twr Write Recovery Time tins Interrupt Set Time 45 tinr Interrupt Reset Time 45 NOTE: 1. 'X' in part numbers indicates power rating ( or ) tbl 11b Timing Waveform of Interrupt Mode (1) Set INT ADDR"A" R/W"A" INT"B" twc INTERRUPT ADDRESS (3) tas (3) tins (2) (4) twr 2691 drw 14 Clear INT ADDR"B" tas (3) trc INTERRUPT CLEAR ADDRESS (2) OE"B" tinr (3) INT"B" 1. All timing is the same for left and right ports. Port A may be either left or right port. Port B is the opposite from port A. 2. See Interrupt Truth Table. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first drw 15,

15 IDT71321/ and IDT71421/ Truth Tables Truth Table I. Non-Contention Read/Write Control (4) Left or Right Port (1) R/W CE OE D-7 Function X H X Z Port Disabled and in Power-Down Mode, ISB2 or ISB4 X H X Z CER = CEL = VIH, Power-Down Mode, ISB1 or ISB3 L L X DATAIN Data on Port Written Into Memory (2) H L L DATAOUT Data in Memory Output on Port (3) H L H Z High Impedance Outputs 1. AL A1L AR A1R. 2. If BUSY = L, data is not written. 3. If BUSY = L, data may not be valid, see twdd and tddd timing. 4. 'H' = VIH, 'L' = VIL, 'X' = DON T CARE, 'Z' = HIGH IMPEDANCE 2691 tbl 12 Truth Table II. Interrupt Flag (1,4) Left Port Right Port R/WL CEL OEL A1L-AL INTL R/WR CER OER A1R-AR INTR Function L L X 7FF X X X X X L (2) Set Right INTR Flag X X X X X X L L 7FF H (3) Reset Right INTR Flag X X X X L (3) L L X 7FE X Set Left INTL Flag X L L 7FE H (2) X X X X X Reset Left INTL Flag 1. Assumes BUSYL = BUSYR = VIH 2. If BUSYL = VIL, then No Change. 3. If BUSYR = VIL, then No Change. 4. 'H' = HIGH, 'L' = LOW, 'X' = DON T CARE 2691 tbl 13 Truth Table III Address BUSY Arbitration CEL CER Inputs Outputs AL-A1L AR-A1R BUSYL (1) BUSYR (1) Function X X NO MATCH H H Normal H X MATCH H H Normal X H MATCH H H Normal L L MATCH (2) (2) Write Inhibit (3) 2691 tbl Pi BUSYL and BUSYR are both outputs for IDT71321 (Master). Both are inputs for IDT71421 (Slave). BUSYX outputs on the IDT71321 are open drain, not pushpull outputs. On slaves the BUSYX input internally inhibits writes. 2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address and enable inputs of this port. If taps is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin

16 IDT71321/ and IDT71421/ Functional Description The IDT71321/IDT71421 provides two ports with separate control, address and I/O pi that permit independent access for reads or writes to any location in memory. The IDT71321/IDT71421 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE = VIH). When a port is enabled, access to the entire memory array is permitted. Interrupts If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 7FE (HEX), where a write is defined as the CER = R/WR = VIL, per Truth Table II. The left port clears the interrupt by accessing address location 7FE when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 7FF (HEX) and to clear the interrupt flag (INTR), the right port must access the memory location 7FF. The message (8 bits) at 7FE or 7FF is user-defined, since it is an addressable SRAM location. If the interrupt function is not used, address locatio 7FE and 7FF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table II for the interrupt operation. Busy Logic Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is Busy. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY Logic is not required or desirable for all applicatio. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. In slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pi HIGH. If desired, unintended write operatio can be prevented to a port by tying the BUSY pin for that port LOW. The BUSY outputs on the IDT71321 (Master) are open drain type outputs and require open drain resistors to operate. If these SRAMs are being expanded in depth, then the BUSY indication for the resulting array does not require the use of an external AND gate. Width Expaion with Busy Logic Master/Slave Arrays When expanding an SRAM array in width while using BUSY logic, one master part is used to decide which side of the SRAM array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus on the IDT71321/IDT71421 SRAMs the BUSY pin is an output if the part is Master (IDT71321), and the BUSY pin is an input if the part is a Slave (IDT71421) as shown in Figure 3. 27Ω 5V BUSYL MASTER Dual Port SRAM BUSYL MASTER Dual Port SRAM BUSYL CE BUSYR CE BUSYR SVE Dual Port SRAM BUSYL SVE Dual Port SRAM BUSYL BUSYR 2691 drw 16 Figure 3. Busy and chip enable routing for both width and depth expaion with IDT71321 (Master) and (Slave) IDT71421 SRAMs. If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operatio from one port for part of a word and inhibit the write operatio from the other port for the other part of the word. The BUSY arbitration, on a Master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with either the R/W signal or the byte enables. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. CE CE BUSYR DECODER 5V BUSYR 27Ω

17 IDT71321/ and IDT71421/ Ordering Information XXXX Device Type A 999 A A A Power Speed Package Process/ Temperature Range A Blank Tube or Tray 8 Tape and Reel Blank I (1) Commercial ( C to +7 C) Industrial (-4 C to +85 C) G (2) Green J PF PP TF 52-pin PLCC (J52) 64-pin TQFP (PN64) 52-pin STQFP (PP52) 64-pin STQFP (PP64) Commercial Only Commercial ustrial Commercial Only Commercial ustrial Low Power Standard Power Speed in nanoseconds K (2K x 8-Bit) MASTER Dual-Port SRAM w/ Interrupt 16K (2K x 8-Bit) SVE Dual-Port SRAM w/ Interrupt 1. Contact your sales office for industrial temperature range availability in other speeds, packages and powers. 2. Green parts available. For specific speeds, packages and powers contact your local sales office. LEAD FINISH (SnPb) parts are in EOL process. Product Discontinuation Notice - PDN# SP drw 17 PP52 Datasheet Document History 3/24/99: Initiated datasheet document history Converted to new format Cosmetic typographical correctio Pages 2 and 3 Added additional notes to pin configuratio 6/7/99: Changed drawing format 11/1/99: Replaced IDT logo 8/23/1: Page 3 Increased storage temperature parameters Clarified TA parameter Page 4 DC Electrical parameters changed wording from "open" to "disabled" Page 16 Fixed part numbers in "Width Expaion" paragraph Changed ±5mV to mv in notes Page 4 Industrial temperature range offering added to DC Electrical Characteristics for and removed for 35 Page 7 and 9 Industrial temperature range added to AC Electrical Characteristics for Page 17 Industrial offering removed for 35 ordering information 1/17/6: Page 1 Added green availability to features Page 17 Added green indicator to ordering information Page 1 & 17 Replaced old IDTTM with new IDTTM logo

18 IDT71321/ and IDT71421/ Datasheet Document History (continued) 8//6: Page 14 Changed INT"A" to INT"B" in the CLEAR INT drawing in the Timing Waveform of Interrupt Mode 1/29/8: Page 17 Removed "IDT" from orderable part number 9/1/12: Page 1& 2 52-pin STQFP added to the features and description Page 3 PP52-1 pin configuration added Page 9 Typo corrected Page 17 Added T&R indicator and PP52-1 package information to the ordering information 6/1/16: Page 2 Changed diagram for the J52 pin configuration by rotating package pin labels and pin numbers 9 degrees clockwise to reflect pin1 orientation and added pin 1 dot at pin 1 Removed J52 chamfers and aligned the top and bottom pin labels in the standard direction Changed diagram for the PN64/PP64 pin configuration by rotating package pin labels and pin numbers 9 degrees counter clockwise to reflect pin 1 orientation and added pin 1 dot at pin 1 Page 3 PP52 pin configuration. Added the IDT logo, changed the text to be in alignment with new diagram marking specs Removed footnote 5 and its references 2//18: Pages 2 & 17 In pin configuration footnotes and in the Ordering Information: The package codes J52-1, PN64-1, PP64-1 and PP52-1changed to J52, PN64, PP64 & PP52 respectively to match standard package codes Product Discontinuation Notice - PDN# SP-17-2 Last time buy expires June 15, 18 CORPORATE HEADQUARTERS for LES: for Tech Support: 624 Silver Creek Valley Road or San Jose, CA fax: DualPortHelp@idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc