HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM

Transcription

1 HIGH-PEED.V 2K x 8 DUA-PORT TATIC RAM PREIMINARY Features True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed access Commercial: /5/ (max.) ow-power operation IDT7V7 Active: mw (typ.) tandby:.mw (typ.) IDT7V7 Active: mw (typ.) tandby: 66µW (typ.) IDT7V7 easily expands data bus width to 16 bits or more using the Master/lave select when cascading more than one device M/ = VIH for BUY output flag on Master M/ = VI for BUY input on lave Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port TT-compatible, single.v (±.V) power supply Available in 68-pin PGA and PCC, and a 8-pin TQFP Description The IDT7V7 is a high-speed 2K x 8 Dual-Port tatic RAM. The IDT7V7 is designed to be used as a stand-alone 6K-bit Dual-Port RAM or as a combination MATER/AVE Dual-Port RAM for 16-bitor-more word systems. Using the IDT MATER/AVE Dual-Port RAM approach in 16-bit or wider memory system applicatio results in full-speed, error-free operation without the need for additional Functional Block Diagram OE OER CE R/W CER R/WR I/O- I/O7 I/O Control I/O Control I/OR-I/O7R, (1,2) BUY (1,2) BUYR A14 A Address Decoder MEMORY ARRAY Address Decoder A14R AR CE OE R/W ARBITRATION INTERRUPT EMAPHORE OGIC CER OER R/WR EM INT 1. (MATER): BUY is output; (AVE): BUY is input. 2. BUY and INT outputs are non-tri-stated push-pull Integrated Device Technology, Inc. M/ 1 EMR INTR 294 drw 1 JUNE 1999 DC 294/5 This datasheet has been downloaded from at this page

2 discrete logic. This device provides two independent ports with separate control, address, and I/O pi that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT s CMO high-performance technology, these devices typically operate on only mw of power. The IDT7V7 is packaged in a ceramic 68-pin PGA and PCC and a 8-pin thin quad flatpack (TQFP). Pin Configuratio (1,2,) INDEX I/O2 I/O I/O4 I/O5 I/O6 I/O7 VCC I/OR I/O1R I/O2R VCC I/OR I/O4R I/O5R I/O6R I/O1 VCC A IDT7V7J 16 J68-1 (4) Pin PCC Top View (5) I/O7R I/O OER OE R/WR R/W EM EMR CER CE A14R A14 A1R A1 A12R A11R A11 A1R A1 A9R A9 A8R A8 A7R A7 A6R A6 A5R INDEX A5 A4 A A2 A1 A INT BUY M/ BUYR INTR AR A1R A2R AR A4R 294 drw 2 I/O1 I/O OE R/W EM CE A14 A1 VCC A12 A11 A1 A9 A8 A7 A6 1. All VCC pi must be connected to power supply. 2. All pi must be connected to ground.. J68-1 package body is approximately.95 in x.95 in x.17 in. PN8-1 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. I/O2 I/O I/O4 I/O5 I/O6 I/O7 VCC I/OR I/O1R I/O2R VCC I/OR I/O4R I/O5R I/O6R I/O7R OER R/WR EMR CER A14R A1R 7V7PF PN8-1 (4) 8-Pin TQFP Top View (5) A12R A11R A1R A9R A8R A7R A6R A5R A5 A4 A A2 A1 A INT BUY M/ BUYR INTR AR A1R A2R AR A4R 294 drw, 2

3 Pin Configuratio (1,2,) (con't.) A5 A4 A2 A BUY M/ INTR A1R AR A7 A6 A A1 INT BUYR AR A2R A4R A5R 9 A9 54 A8 2 A7R A6R 8 57 A11 56 A1 A9R 1 A8R VCC 61 A14 6 EM 58 A12 6 A1 62 CE IDT7V7G G68-1 (4) 68-Pin PGA Top View (5) 28 A11R A14R 29 A1R 27 A12R A1R 4 65 OE 64 R/W 22 EMR 2 CER 67 I/O 66 2 OER 21 R/WR I/O1 I/O2 I/O4 I/O7 I/O1R VCC I/O4R I/O7R I/O I/O5 I/O6 VCC I/OR I/O2R I/OR I/O5R I/O6R INDEX A B C D E F G H J K 1. All VCC pi must be connected to power supply. 2. All pi must be connected to ground.. Package body is approximately 1.18 in x 1.18 in x.16 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. Pin Names (1,2) 294 drw 4 eft Port Right Port Names CE CER Chip Enable R/W R/WR Read/Write Enable OE OER Output Enable A - A14 AR - A14R Address I/O - I/O7 I/OR - I/O7R Data Input/Output EM EMR emaphore Enable INT INTR Interrupt Flag BUY BUYR Busy Flag M/ VCC Master or lave elect Power Ground 294 tbl 1

4 Truth Table I: Non-Contention Read/Write Control Inputs (1) Outputs CE R/W OE EM I/O-7 Mode H X X H High-Z Deselected: Power-Down X H DATAIN Write to Memory H H DATAOUT Read Memory X X H X High-Z Outputs Disabled NOTE: 1. A A14 AR A14R 294 tbl 2 Truth Table II: emaphore Read/Write Control Inputs (1) Outputs CE R/W OE EM I/O-7 Mode H H DATAOUT Read Data in emaphore Flag H X DATAIN Write I/O into emaphore Flag X X Not Allowed NOTE: 1. There are eight semaphore flags written to via I/O and read from all I/O's (I/O-I/O7). These eight semaphores are addressed by A-A2 294 tbl Absolute Maximum Ratings (1) ymbol Rating Commercial & Industrial VTERM Terminal Voltage with Respect to Unit -.5 to +4.6 V Maximum Operating Temperature and upply Voltage (1,2) Grade Ambient Temperature Vcc Commercial O C to +7 O C V.V +. TBIA TTG IOUT Te mp e rature Under Bias torage Te mp e rature DC Output Current - to +1 o C - to +1 o C 5 ma Industrial -4 O C to +85 O C V.V tbl 5 1. This is the parameter TA. 2. Industrial temperature: for specific speeds, packages and powers contact your sales office. 1. tresses greater than those listed under ABOUTE MAXIMUM RATING may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio above those indicated in the operational sectio of this specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect reliability. 2. VTERM must not exceed Vcc +.V for more than % of the cycle time or 1 maximum, and is limited to < 2mA for the period of VTERM > Vcc +.V. Capacitance (1) (TA = + C, f = 1.MHz) TQFP Only 294 tbl 4 ymbol Parameter Conditio Max. Unit CIN Input Capacitance VIN = dv 9 pf COUT Output Capacitance VOUT = dv 1 pf Recommended DC Operating Conditio ymbol Parameter Min. Typ. Max. Unit VCC upply Voltage...6 V Ground V VIH Input High Voltage 2. VCC+. V VI Input ow Voltage -. (1).8 V 1. VI > -1.5V for pulse width less than VTERM must not exceed Vcc +.V. 294 tbl tbl 7 1. This parameter is determined by device characterization but is not production tested. 2. dv represents the interpolated capacitance when the input and output signals switch from V to V or from V to V. 4

5 DC Electrical Characteristics Over the Operating Temperature and upply Voltage Range (VCC =.V ±.V) 7V7 7V7 ymbol Parameter Test Conditio Min. Max. Min. Max. Unit II Input eakage Current (1) VCC =.6V, VIN = V to VCC IO Output eakage Current CE = VIH, VOUT = V to VCC 1 5 µa 1 5 µa VO Output ow Voltage IO = +4mA.4.4 V VOH Output High Voltage IOH = -4mA V NOTE: 1. At VCC < 2.V, input leakages are undefined. 294 tbl 8 DC Electrical Characteristics Over the Operating Temperature and upply Voltage Range (1,6) (VCC =.V ±.V) 7V7X 7V7X5 7V7X ymbol Parameter Test Condition Version Typ. Max. Typ. Max. Typ. Max. Unit ICC Dynamic Operating Current (Both Ports Active) CE = VI, Outputs Open EM = VI f = fmax () COM' IND ma IB1 tandby Current (Both Ports - TT evel Inputs) CER = CE = VIH EMR = EM = VIH f = fmax () COM' IND ma IB2 tandby Current (One Port - TT evel Inputs) CE"A" = VI and CE"B" = VIH (5) Active Port Outputs Open, f=fmax () EMR = EM = VIH COM' IND ma IB Full tandby Current (Both Ports - CMO evel Inputs) Both Ports CE and CER > VCC -.2V, VIN > VCC -.2V or VIN <.2V, f = (4) EMR = EM > VCC -.2V COM' IND ma IB4 Full tandby Current (One Port - CMO evel Inputs) CE"A" <.2V and CE"B" > VCC -.2V (5) EMR = EM > VCC -.2V VIN > VCC -.2V or VIN <.2V Active Port Outputs Open, f = fmax () COM' IND ma 294 tbl 9 1. 'X' in part number indicates power rating ( or ). 2. VCC =.V, TA = + C, and are not production tested. ICCDC = 8mA (Typ.). At f = fmax, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ trc, and using AC Test Conditio" of input levels of to V. 4. f = mea no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 6. Industrial temperature: for specific speeds, packages and powers contact your sales office. 5

6 AC Test Conditio Input Pulse evels Input Rise/Fall Times Input Timing Reference evels Output Reference evels Output oad to.v 1.5V 1.5V Figures 1 and tbl 1 DATAOUT BUY INT.V.V 59Ω 59Ω DATAOUT 45Ω pf 45Ω 5pF* Figure 1. AC Output Test oad AC Electrical Characteristics Over the Operating Temperature and upply Voltage Range (4,5) 7V7X 294 drw 5 7V7X5 294 drw 6 Figure 2. Output Test oad (for tz, thz, twz, tow) * Including scope and jig. 7V7X ymbol Parameter Min. Max. Min. Max. Min. Max. Unit READ CYCE trc Read Cycle Time 5 taa Address Access Time 5 tace Chip Enable Access Time () 5 taoe Output Enable Access Time 15 2 toh Output Hold from Address Change tz Output ow-z Time (1,2) thz Output High-Z Time (1,2) 15 2 tpu Chip Enable to Power Up Time tpd Chip Disable to Power Down Time 5 5 top emaphore Flag Update Pulse (OE or EM) taa emaphore Address Access Time Traition is measured ±2mV from ow- or High-impedance voltage with Output Test oad (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested.. To access RAM, CE = VI and EM = VIH. To access semaphore, CE = VIH and EM = VI. 4. 'X' in part number indicates power rating ( or ). 5. Industrial temperature: for specific speeds, packages and powers contact your sales office. 294 tbl 11 Timing of Power-Up Power-Down CE ICC tpu tpd IB 294 drw 7, 6

7 Waveform of Read Cycles (5) trc ADDR CE OE (4) taa tace (4) taoe (4) R/W DATAOUT (1) tz VAID DATA (4) toh thz BUYOUT (,4) tbdd 294 drw 8 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is de-asserted first, CE or OE.. tbdd delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operatio BUY has no relation to valid output data. 4. tart of valid data depends on which timing becomes effective last taoe, tace, taa or tbdd. 5. EM = VIH. AC Electrical Characteristics Over the Operating Temperature and upply Voltage (5,6) 7V7X 7V7X5 7V7X ymbol Parameter Min. Max. Min. Max. Min. Max. Unit WRITE CYCE twc Write Cycle Time 5 tew Chip Enable to End-of-Write () 2 taw Address Valid to End-of-Write 2 ta Address et-up Time () twp Write Pulse Width 2 4 twr Write Recovery Time tdw Data Valid to End-of-Write 15 2 thz Output High-Z Time (1,2) 15 2 tdh Data Hold Time (4) twz Write Enable to Output in High-Z (1,2) 15 2 tow Output Active from End-of-Write (1, 2,4) twrd EM Flag Write to Read Time tp EM Flag Contention Window tbl Traition is measured ±2mV from ow or High impedance voltage with Output Test oad (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested.. To access RAM, CE = VI and EM = VIH. To access semaphore, CE = VIH and EM = VI. Either condition must be valid for the entire tew time. 4. The specification for tdh must be met by the device supplying write data to the RAM under all operating conditio. Although tdh and tow values will vary over voltage and temperature, the actual tdh will always be smaller than the actual tow. 5. 'X' in part number indicates power rating ( or ). 6. Industrial temperature: for specific speeds, packages and powers contact your sales office. 7

8 Timing Waveform of Write Cycle No. 1, R/W Controlled Timing (1,5,8) ADDRE OE twc (7) thz CE or EM (9) taw (6) ta twp () twr R/W (7) twz tow DATAOUT (4) (4) tdw tdh DATAIN 294 drw Timing Waveform of Write Cycle No. 2, CE Controlled Timing (1,5) ADDRE twc CE or EM (9) taw (6) ta tew () twr R/W tdw tdh DATAIN 294 drw 1 1. R/W or CE must be HIGH during all address traitio. 2. A write occurs during the overlap (tew or twp) of a OW CE and a OW R/W for memory array writing cycle.. twr is measured from the earlier of CE or R/W (or EM or R/W) going HIGH to the end of write cycle. 4. During this period, the I/O pi are in the output state and input signals must not be applied. 5. If the CE or EM OW traition occurs simultaneously with or after the R/W OW traition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/W. 7. This parameter is guaranteed by device characterization, but is not production tested. Traition is measured ±2mV from steady state with the Output Test oad (Figure 2). 8. If OE is OW during R/W controlled write cycle, the write pulse width must be the larger of twp or (twz + tdw) to allow the I/O drivers to turn off and data to be placed on the bus for the required tdw. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twp. 9. To access RAM, CE = VI and EM = VIH. To access semaphore, CE = VIH and EM = VI. tew must be met for either condition. 8

9 Timing Waveform of emaphore Read after Write Timing, Either ide (1) taa toh A-A2 VAID ADDRE VAID ADDRE EM taw tew twr tace tdw top DATA DATA IN VAID DATAOUT VAID R/W ta twp tdh twrd taoe OE Write Cycle top Read Cycle 294 drw CE = VIH for the duration of the above timing (both write and read cycle). 2. DATAOUT VAID represents all I/O's (I/O-I/O7) equal to the semaphore value. Timing Waveform of emaphore Write Contention (1,,4) A"A"-A2"A" MATCH IDE "A" R/W"A" EM"A" tp A"B"-A2"B" MATCH IDE "B" R/W"B" EM"B" 294 drw DOR = DO = VI, CER = CE = VIH. 2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".. This parameter is measured from R/W"A" or EM"A" going HIGH to R/WB or EM"B" going HIGH. 4. If tp is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag. 9

10 AC Electrical Characteristics Over the Operating Temperature and upply Voltage Range (6,7) 7V7X 7V7X5 7V7X ymbol Parameter Min. Max. Min. Max. Min. Max. Unit BUY TIMING (M/ = VIH) tbaa tbda tbac BUY Access Time from Address BUY Disable Time from Address BUY Access Time from Chip Enable tbdc BUY Disable Time from Chip Enable 5 tap Arbitration Priority et-up Time tbdd BUY Disable to Valid Data () BUY TIMING (M/ - VI) twb BUY Input to Write (4) twh Write Hold After BUY (5) 2 PORT-TO-PORT DEAY TIMING twdd Write Pulse to Data Delay (1) tddd Write Data Valid to Read Data Delay (1) Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUY". 2. To eure that the earlier of the two ports wi.. tbdd is a calculated parameter and is the greater of, twdd twp (actual) or tddd tdw (actual). 4. To eure that the write cycle is inhibited on port "B" during contention on port "A". 5. To eure that a write cycle is completed on port "B" after contention on port "A". 6. 'X' in part numbers indicates power rating ( or ). 7. Industrial temperature: for specific speeds, packages and powers contact yuor sales office. 294 tbl 1 Timing Waveform of Write with Port-to-Port Read and BUY (2,4,5) twc ADDR"A" MATCH twp R/W"A" tdw tdh DATAIN "A" VAID (1) tap ADDR"B" MATCH BUY"B" tbaa tbda tbdd twdd DATAOUT "B" tddd () 1. To eure that the earlier of the two ports wi. tap is ignored for M/ = VI (AVE). 2. CE = CER = VI. OE = VI for the reading port. 4. If M/ = VI (AVE), then BUY is an input (BUY"A" = VIH and BUY"B" = "don't care", for this example). 5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A". VAID 294 drw 1 1

11 Timing Waveform of Write with BUY twp R/W"A" twb BUY"B" twh (1) R/W"B" 1. twh must be met for both BUY input (AVE) and output (MATER). 2. BUY is asserted on Port "B" blocking R/W"B", until BUY"B" goes HIGH. 294 drw 14, Waveform of BUY Arbitration Controlled by CE Timing (1) ADDR"A" and "B" ADDREE MATCH CE"A" tap CE"B" tbac tbdc BUY"B" 294 drw 15 Waveform of BUY Arbitration Cycle Controlled by Address Match Timing (1) ADDR"A" tap ADDRE "N" ADDR"B" MATCHING ADDRE "N" tbaa tbda BUY"B" 294 drw All timing is the same for left and right ports. Port A may be either the left or right port. Port B is the port opposite from Port A. 2. If tap is not satisfied, the BUY signal will be asserted on one side or the other, but there is no guarantee on which side busy will be asserted. 11

12 AC Electrical Characteristics Over the Operating Temperature and upply Voltage Range (1) 7V7X 7V7X5 7V7X ymbol Parameter Min. Max. Min. Max. Min. Max. Unit INTERRUPT TIMING ta Address et-up Time twr Write Recovery Time tin Interrupt et Time 4 tinr Interrupt Reset Time 5 NOTE: 1. 'X' in part number indicates power rating ( or ). 24 tbl 14 Waveform of Interrupt Timing (1) twc ADDR"A" INTERRUPT ET ADDRE () (4) ta twr CE"A" R/W"A" tin () INT"B" 294 drw 17 trc ADDR"B" INTERRUPT CEAR ADDRE () ta CE"B" OE"B" tinr () INT"B" 294 drw All timing is the same for left and right ports. Port A may be either the left or right port. Port B is the port opposite from port A. 2. ee Interrupt Truth Table III.. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first. 12

13 Truth Table III Interrupt Flag (1) eft Port Right Port R/W CE OE A14-A INT R/WR CER OER A14R-AR INTR Function X 7FFF X X X X X et Right INTR Flag X X X X X X 7FFF H () Reset Right INTR Flag X X X X () X 7FFE X et eft INT Flag X 7FFE H X X X X X Reset eft INT Flag 1. Assumes BUY = BUYR =VIH. 2. If BUY = VI, then no change.. If BUYR = VI, then no change. 294 tbl 15 Truth Table IV Address BUY Arbitration Inputs Outputs CE CER A-A14 AR-A14R BUY (1) BUYR (1) Function X X NO MATCH H H Normal H X MATCH H H Normal X H MATCH H H Normal MATCH Write Inhibit () 294 tbl Pi BUY and BUYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUY outputs on the IDT7V7 are pushpull, not open drain outputs. On slaves the BUY input internally inhibits writes. 2. "" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and enable inputs of this port. If tap is not met, either BUY or BUYR = OW will result. BUY and BUYR outputs can not be OW simultaneously.. Writes to the left port are internally ignored when BUY outputs are driving OW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUYR outputs are driving OW regardless of actual logic level on the pin. Truth Table V Example of emaphore Procurement equence (1,2,) Functio D - D7 eft D - D7 Right tatus No Action 1 1 emaphore free eft Port Writes "" to emaphore 1 eft port has semaphore token Right Port Writes "" to emaphore 1 No change. Right side has no write access to semaphore eft Port Writes "1" to emaphore 1 Right port obtai semaphore token eft Port Writes "" to emaphore 1 No change. eft port has no write access to semaphore Right Port Writes "1" to emaphore 1 eft port obtai semaphore token eft Port Writes "1" to emaphore 1 1 emaphore free Right Port Writes "" to emaphore 1 Right port has semaphore token Right Port Writes "1" to emaphore 1 1 emaphore free eft Port Writes "" to emaphore 1 eft port has semaphore token eft Port Writes "1" to emaphore 1 1 emaphore free 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7V7. 2. There are eight semaphore flags written to via I/O and read from all I/O's (I/O - I/O7). These eight semaphores are addressed by A -A2.. CE = VIH, EM = VI to access the semaphores. Refer to the emaphore Read/Write Control Truth Table. 294 tbl 17 1

14 Functional Description The IDT7V7 provides two ports with separate control, address and I/O pi that permit independent access for reads or writes to any location in memory. The IDT7V7 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE HIGH). When a port is enabled, access to the entire memory array is permitted. Interrupts If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INT) is asserted when the right port writes to memory location 7FFE (HEX), where a write is defined as CER = R/WR = VI per Truth Table III. The left port clears the interrupt through access of address location 7FFE when CE = OE = VI, R/W is a "don't care". ikewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 7FFF (HEX) and to clear the interrupt flag (INTR), the right port must read the memory 7FFF location 7FFF. The message (8 bits) at 7FFE or 7FFF is user-defined since it is an addressable RAM location. If the interrupt function is not used, address locatio 7FFE and 7FFF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table III for the interrupt operation. BUY MATER Dual Port RAM BUY MATER Dual Port RAM BUY CE BUYR CE BUYR AVE Dual Port RAM BUY AVE Dual Port RAM BUY 294 drw 19 Figure. Busy and chip enable routing for both width and depth expaion with IDT7V7 RAMs. Busy ogic Busy ogic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is busy. The busy pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUY logic is not required or desirable for all applicatio. In some cases it may be useful to logically OR the BUY outputs together and use any BUY indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of BUY logic is not desirable, the BUY logic can be disabled by placing the part in slave mode with the M/ pin. Once in slave mode the BUY pin operates solely as a write inhibit input pin. Normal operation can be CE BUYR CE BUYR DECODER BUYR, 14 programmed by tying the BUY pi HIGH. If desired, unintended write operatio can be prevented to a port by tying the BUY pin for that port OW. The BUY outputs on the IDT 7V7 RAM in master mode, are push-pull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the BUY indication for the resulting array requires the use of an external AND gate. Width Expaion with BUY ogic Master/lave Arrays When expanding an IDT7V7 RAM array in width while using BUY logic, one master part is used to decide which side of the RAM array will receive a BUY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the BUY signal as a write inhibit signal. Thus on the IDT7V7 RAM the BUY pin is an output if the part is used as a master (M/ pin = VIH), and the BUY pin is an input if the part used as a slave (M/ pin = VI) as shown in Figure. If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUY on one side of the array and another master indicating BUY on one other side of the array. This would inhibit the write operatio from one port for part of a word and inhibit the write operatio from the other port for the other part of the word. The BUY arbitration, on a master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUY flag to be output from the master before the actual write pulse can be initiated with the R/W signal. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. emaphores The IDT7V7 is an extremely fast Dual-Port 2K x 8 CMO tatic RAM with an additional 8 address locatio dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port RAM to claim a privilege over the other processor for functio defined by the system designer s software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port RAM or any other shared resource. The Dual-Port RAM features a fast access time, and both ports are completely independent of each other. This mea that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMO tatic RAM and can be read from, or written to, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a non-semaphore location. emaphores are protected agait such ambiguous situatio and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port RAM. These devices have an automatic powerdown feature controlled by CE, the Dual-Port RAM enable, and EM, the semaphore enable. The CE and EM pi control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition which is shown in Truth Table

15 I where CE and EM are both HIGH. ystems which can best use the IDT7V7 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software inteive. These systems can benefit from a performance increase offered by the IDT7V7's hardware semaphores, which provide a lockout mechanism without requiring complex programming. oftware handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configuratio. The IDT7V7 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very high-speed systems. D D Q semaphore flags useful in interprocessor communicatio. (A thorough discussion on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the PORT WRITE EMAPHORE REQUET FIP FOP EMAPHORE READ Figure 4. IDT7V7 emaphore ogic EMAPHORE REQUET FIP FOP Q D RPORT D WRITE EMAPHORE READ 294 drw 2, How the emaphore Flags Work The semaphore logic is a set of eight latches which are independent of the Dual-Port RAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called Token Passing Allocation. In this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active OW. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT7V7 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a OW input on the EM pin (which acts as a chip select for the semaphore flags) and using the other control pi (Address, OE, and R/W) as they would be used in accessing a standard tatic RAM. Each of the flags has a unique address which can be accessed by either side through address pi A A2. When accessing the semaphores, none of the other address pi has any effect. When writing to a semaphore, only data pin D is used. If a OW level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Truth Table V). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side s output register when that side's semaphore select (EM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (EM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Truth Table V). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been used itead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag OW and the other side HIGH. This condition will continue until a one is written to the same semaphore request latch. hould the other side s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side s request latch. The second side s flag will now stay OW until its semaphore request latch 15

16 is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. ince any semaphore request flag which contai a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. Using emaphores ome Examples Perhaps the simplest application of semaphores is their application as resource markers for the IDT7V7 s Dual-Port RAM. ay the 2K x 8 RAM was to be divided into two 16K x 8 blocks which were to be dedicated at any one time to servicing either the left or right port. emaphore could be used to indicate the side which would control the lower section of memory, and emaphore 1 could be defined as the indicator for the upper section of memory. To take a resource, in this example the lower 16K of Dual-Port RAM, the processor on the left port could write and then read a zero in to emaphore. If this task were successfully completed (a zero was read back rather than a one), the left processor would assume control of the lower 16K. Meanwhile the right processor was attempting to gain control of the resource after the left processor, it would read back a one in respoe to the zero it had attempted to write into emaphore. At this point, the software could choose to try and gain control of the second 16K section by writing, then reading a zero into emaphore 1. If it succeeded in gaining control, it would lock out the left side. Once the left side was finished with its task, it would write a one to emaphore and may then try to gain access to emaphore 1. If emaphore 1 was still occupied by the right side, the left side could undo its semaphore request and perform other tasks until it was able to write, then read a zero into emaphore 1. If the right processor performs a similar task with emaphore, this protocol would allow the two processors to swap 16K blocks of Dual-Port RAM with each other. The blocks do not have to be any particular size and can even be variable, depending upon the complexity of the software using the semaphore flags. All eight semaphores could be used to divide the Dual-Port RAM or other shared resources into eight parts. emaphores can even be assigned different meanings on different sides rather than being given a common meaning as was shown in the example above. emaphores are a useful form of arbitration in systems like disk interfaces where the CPU must be locked out of a section of memory during a trafer and the I/O device cannot tolerate any wait states. With the use of semaphores, once the two devices has determined which memory area was off-limits to the CPU, both the CPU and the I/O devices could access their assigned portio of memory continuously without any wait states. emaphores are also useful in applicatio where no memory WAIT state is available on one or both sides. Once a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed. Another application is in the area of complex data structures. In this case, block arbitration is very important. For this application one processor may be respoible for building and updating a data structure. The other processor then reads and interprets that data structure. If the interpreting processor reads an incomplete data structure, a major error condition may exist. Therefore, some sort of arbitration must be used between the two different processors. The building processor arbitrates for the block, locks it and then is able to go in and update the data structure. When the update is completed, the data structure block is released. This allows the interpreting processor to come back and read the complete data structure, thereby guaranteeing a coistent data structure. 16

17 Ordering Information IDT XXXXX A 999 A A Device Type Power peed Package Process/ Temperature Range Blank I (1) Commercial ( C to+7 C) Industrial (-4 C to +85 C) PF G J 8-pin TQFP (PN8-1) 68-pin PGA (G68-1) 68-pin PCC (J68-1) 5 Commercial Only Commercial Only Commercial Only peed in nanoseconds tandard Power ow Power 7V7 6K (2K x 8).V Dual-Port RAM 294 drw 21 NOTE: 1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office. Preliminary Datasheet: "PREIMINARY' datasheets contain descriptio for products that are in early release. Datasheet Document History: /24/99: Initiated datasheet document history Converted to new format Cosmetic and typographical correctio Page 2 and Added additional notes to pin configuratio 6/9/99: Changed drawing format CORPORATE HEADQUARTER for AE: for Tech upport: 2975 tender Way or anta Clara, CA 9554 fax: DualPortHelp@idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 17