0.35um design verifications

Transcription

1 0.35um design verifications Path end segment check (END) First check is the end segment check, This error is related to the routing metals when routing is done with a path. The finish of this path can case an extra angle to occur. This can cause an error to occur during mask making so it must be corrected. endsegment/endsegment.rpt This file contains the coordinates of the errors. Example In the endsegment.rpt file you can find the coordinates like the following: Path endsegment length 0.05 at location (10.5,30.1) in cell DIV on layer 35 is less than 1/2 of path width 0.7. This means the error is located in cell DIV at coordinates x=10.5 y=30.1 The error is located on the igs layer 35 (in C35 this is metal1) Solution To correct this error, here are some possible solutions: If using Cadence, stream out the design File / export / stream In the options dialog, set the option Convert Paths to Polygons Previous step can also be done manually by selecting the path Edit / Other / Convert To Polygon Using Cadence 6 OA, this menu can be found: Edit / Advanced / Convert to Polygon

2 ANTENNA RULE CHECK (ANT) Antenna errors can cause a charge to blow up your gate during ion-etching. The checks are done with Calibre and we can accept an antenna ratio till 300. During ion-etching of the metal routing charges are build up which can be a hazard for associated GATE oxide(plasma damage). ant/ant_{topcell}_hier_shortreport.rpt This is a text based file with an overview of the errors in your design. ant/ant_{topcell}_hier_calibre_results.gds This is a gdsii type file which can be streamed into Cadence giving a visual presentation of the error in the design (and the rpt file). Every error in the rpt file has a cell in the gds file with the same name. Please notice that these error polygons which show the error are drawn on the layer marker[err] which is igs layer 0 datatype 0. Example RULECHECK ANT_MET2_GATE_AR2... TOTAL Result Count = 187 (351) AR2 Maximum ratio of floating MET2 edge to connected GATE area > 400 This error shows a metal 2 antenna ratio errors. Solution To prevent possible plasma damage of the gate there are 2 solutions: place a diffusion diode close to the gate which creates a path for the charge to the substrate, this must be placed as close a possible to the gate without violating the DRC. This diode must be placed reversed biased. * Cadence 5: Use diode library: TECH_C35B4 cell: ND_C and place these as near the gate on the related metal routing * Cadence 6 OA: within cadence OA, it's, Create --> Via and then select ND_C * You can also draw the diode yourself using the following layers: MET1 CONT DIFF NPLUS route to topmetal4 (and back down if preferred) as close as possible to the gate, this will create a path for the charge to a S/D diffusion at the other end of the metal routing. Note, antenna violation rules can be found in the CMOS C35 Design rules manual ENG - 183, Rev.: 9.0, 0.35UM CMOS C35 Design Rules

3 DESIGN FOR MANUFACTURING CHECK (DFM) The DFM rules are yield related rules and can have an influence on the yield and the lifetime of your devices. So these are mostly important when going into production. For mpw these are not so critical, but as designer you are always able to make your design more robust when respecting these rules. dfm/dfm_{topcell}_hier_shortreport.rpt This is a text based summery file with an overview of the violations in your design. dfm/dfm_{topcel} _hier_calibre_results.gds This is a gdsii type file which can be streamed into Cadence giving a visual presentation of the error in the design (and the rpt file). Every error in the rpt file has a cell in the gds file with the same name. Please notice that these error polygons which show the error are drawn on the layer marker[err] which is igs layer 0 datatype 0. Exception DFM0009 RATIO_GATE_VIA_INSUFFICIENT_DFMC0009 DFM0012 RATIO_GATE_VIA2_INSUFFICIENT_DFMC0012 DFM0015 RATIO_GATE_VIA3_INSUFFICIENT_DFMC0015 DFM0008 : more vias can be placed here on m1/m2 connection DFM0011 : more via2 can be placed here on m2/m3 connection DFM0014 : more via3 can be placed here on m4/m3 connection This rule reflects to an electrochemical occurrence which results that a single via could get destroyed during processing and therefore we advise designers to resolve these problem by always placing multiple via s when possible. DESIGN RULE CHECK (DRC) ASSURA The Design Rule Check is the most important check. Here the design is checked according to de rules given by the foundry. Besides showing the crucial errors, also a lot of warnings and info is shown in this report. Some of them can be ignored, others must be corrected. assura/assura_topcell.rpt This is a text based summery file with an overview of the violations in your design. drc/drc_topcell.err This is a text type file containing the coordinates of all violations present.

4 DESIGN RULE CHECK (DRC) - CALIBRE The Design Rule Check is the most important check. Here the design is checked according to de rules given by the foundry. Besides showing the crucial errors, also a lot of warnings and info is shown in this report. Some of them can be ignored, others must be corrected. drc/drc_{topcell}_hier_shortreport.rpt This is a text based file with an overview of the errors in your design. drc/drc_{topcel} _hier_calibre_results.gds This is a gdsii type file which can be streamed into Cadence giving a visual presentation of the error in the design (and the rpt file). Every error in the rpt file has a cell in the gds file with the same name. Please notice that these error polygons which show the error are drawn on the layer marker[err] which is igs layer 0 datatype 0. Note Not all errors are considered crucial for the project. The responsible for checking these errors is placed on the customer. We ll give you our remarks but in general the customer can decide to wave or solve the errors. Here are some standard remarks on some errors which can be ignored. All errors in a logo, most likely metal spacing errors can be ignored as they ll not influence the working of your design. All errors related to spacing of the logo and your logic, ex a transistor near the logo can be crucial and must be corrected. All errors located in standards AMS devices (core or I/O) can be ignored. To make these devices as dense as possible, the DRC is sometimes violated but all standard cell s available are silicon proven and fully characterized as is. It is not allowed to make any adjustments or error corrections to these standard cells. Errors related to slotting and density: The fill pattern scripts where created to have a certain percentage and even distribution of metal/poly on the wafer. This because these have an influence on the yield(=number of good dies) on a wafer. Now, on mpw we have several different designs which are placed together and a minimum of dies is guaranteed. So, yield is of no importance. Therefore you can ignore the rules on mpw. The percentage and the distribution of metal/poly is only relevant with full wafer runs, cause here a big fallout could mean that extra wafers have to be started to get the required number of dies. So, these rules are not mandatory with the exception when you would go to an engineering run (production) in a later state, where yield can become important. When generating the fillers, you can draw NOFILL in area s on which you don t want the fillers to be generated. Errors related to MTOP spacing. This is a stress release and CMP rule which can influence the wafer yield which is identical to the slotting and density errors above ignored on MPW. Errors missing layers FIMP, NLDD. These layers are generated layers and the layer generation ll be done in the fab. Also there are some errors which must be corrected. All metal spacing and width errors. Exception for logo s (mentioned above), the wide metal spacing errors and the max MTOP spacing errors. All drc rules of the types min width and min spacing which are not in standard cells or in a logo. Calibre erc rules As we will perform the calibre drc which will provide some electrical rules information which is only relevant if these labels are present on the IO pads. (shorted pads, gate not connected to power, floating nets,...) You may place supply labels(vdd and GND) on the supply cell s in the layer PIN purpose pad. Notice that the erc rules in calibre are very limited and ll give some unreal errors. Most important to have a working asic is having a matching LvS which ll clear all erc errors.

5 FAQ, KNOWN ITEMS AND REMARKS start of the processing / delivery of the dies Unless specified differently the processing of our C35 MPW s starts one week after the Europractice MPW deadline found on the Europractice website or EP calendar. This concludes that all MPW participants must have a final error free design ready on Friday morning following on the MPW deadline (normally on Monday). On Friday the MPW reticle is designed and all design on which violations exists are postponed to the next MPW. Standard calculation adds 1 week of design verifications, 8 weeks of processing and 3 weeks of packaging to the MPW deadline. This concluded that the delivery of the dies ll be on the MPW deadline + 12 weeks. This date is dependent on the foundry load and/or holiday periods. Neither the foundry or Europractice give any guaranty regarding the delivery date of the ordered products. number of dies / extra wafer It is possible to require extra dies on an MPW participation. Standard 40 dies are delivered for one submission. A customer can purchase one or more extra wafers each giving him 50 extra dies. The order of the extra wafer must be ordered before the start of the MPW processing and a quote for this ll be provided case by case. If there are some wafer parts available after the MPW, the dies on this can be purchased to its first buyer. This ll have an extra sawing possibly destroying the other dies on this wafer. scribe placement Placing the scribe ll have an influence on the drc reports on your design. the scribe contains a stack of metals and violates some of the standard drc violations. For this we encourage our customer not to place the scribe themselves. We can place this scribe for you which has some advantages: smaller errors reports as the drc is done on the design without scribe. invoiced area is your design area without the scribe If you want to create your own scribe, this must fulfill some specific drc rules: scribe must be made on a grid of 5um scribe must have a spacing of at least 10um from all design structures with exception of the standard ams I/O pads which already have a spacing to a metal1 scribe node. the scribe must be made in a separate cell which may only contain the scribe and the topcell of the design. DRC ll be ran on the topcell so all data in the scribe cell is ignored for MPW! When placing the scribe yourself, the invoiced design area ll be the design inclusive scribe! design boundaries, incl labels, invoiced area When making your design, it is very helpful to place labels on the bondpads for simulation etc. These labels can extend the boundary of your design and make it invisible to check if mistakenly some real data is outside the I/O ring boundary. For this reason, we ask to remove the labels from the design and to make sure the design boundary is identical to the design size. for example making a sub cell not on the origin, can make the boundary of the topcell greater than the real design area. In general the boundary area ll be invoiced so it is very important this ll not extend from the real design size. Your Europractice contact ll always remove the labels and try to make the design boundary identical to the design size before increasing the invoice. layer generation Since some time, the fab changed their policy so all layers ll be generated in the fab during mask prep. All generated layers from the customer ll be removed and regenerated by the fab. fillers Although density and slot errors are uncritical, you can solve these errors with some filler scripts which are provided by the fab. The explanation to use these fillers can be found on the fab asic website. On request your Europractice contact can also generate the fillers on your design. As these fillers give a lot of floating net violations which ll make possible real errors invisible, the fillers are generated on the final version. As Europractice is not responsible for making any adjustments on the layout, the final filled version ll be passed back to the customer for a final confirmation. Make sure to submit your design in time if you want this fillers to be generated.

6 physical die size Although your design could have less drawn dimensions, the physical dimension of your unpackaged dies ll be bigger as each design ll get a scribe line + some spare area for the saw. Secondly for MPW, we cannot saw each design next to his scribe line, this would destroy all other designs on this MPW so we create the MPW sawing line fitting the biggest design of the sawing scheme. This can cause some dummy area surrounding your current unpackaged dies. 0.35µm Power Supply Concept Ams provides an application note with an overview of the power concept used within ams' periphery libraries. It explains the star point concept used in the 0.35µm library cells and gives hints for running LVS checks. You can find this application note on the following link: