Literacy for Integrated Circuit Reverse Engineering
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1 Literacy for Integrated Circuit Reverse Engineering Alex Radocea 1
2 Now bringing pain to the adversary at worked security at a large tech company worked security at matasano learned c and unix from swedish people at wargames.unix.se adc@intruded.net 2
3 Thanks John McMaster (siliconpr0n.org, uvicrec.blogspot.com) siliconzoo.org (SRLabs) Andrew Zonenberg Ekoparty Wouldn t be possible without John McMaster 3
4 Integrated Circuits Circuit.htm 5-component oscillator 4
5 Intel First x86 chip > 1 M transistors µm process size Source: John McMaster doku.php?id=mcmaster:intel:80486dx &s[]=map 5
6 Why reverse ICs? 6
7 Go lower level 7
8 Professionals Extracting and selling expensive secrets Security analysis IP Litigation Competitive Research Chip Art Shared Cryptographic Fuses secrets Algorithms Sidechannels Secret functionality Algorithms Fabrication techniques Layout tricks Materials Composition Fun and Mischief Unlocking Modding Simulators Hobbyists 8
9 Communities await you academic resources blogosphere archives: siliconzoo, siliconpr0n, visual6502 open source tools & software below it is physics below that only math 9
10 Decapsulation 10
11 Let s talk packaging 11
12 Single Inline Package 12
13 Double Inline Package 13
14 Surface Mount 14
15 Ball Grid Array Kl_Intel_Pentium_MMX_embedded_BGA_Bottom.jpg/220px- Kl_Intel_Pentium_MMX_embedded_BGA_Bottom.jpg 15
16 More... List_of_integrated_circuit_packaging_types 16
17 Unpackaging red_present_box_wrapped.jpg 17
18 DANGER: Safety Risks 18
19 Heat 19
20 Source: John McMaster uvicrec 20
21 Approaching Boiling Point 21
22 22
23 Friction 23
24 Lots of dremelling... Source: John McMaster uvicrec 24
25 25
26 26
27 27
28 Acid 28
29 Andrew Zonenberg 74LS154N 980s vintage 74LS154 4-to-16 demultiplexer, packaged in a PDIP 29
30 30
31 Gold bonding wires appear 31
32 32
33 This is suitable for live analysis, no damage to die 33
34 Delayering Circuit.htm 34
35 Silicon ingots 35
36 Polycrystaline Silicon Polysilicon Supply.jpg 36
37 Silicon Layer Cake Protective Glass Layer Metal Layers Vias Polysilicon Diff uss ion Lay ers Si Substrate Wells Si Main substrate 37
38 CMOS cross-section 500px-Cmos_impurity_profile.PNG 38
39 Bonding wires Source: John McMaster semipol/ ad534 39
40 Bonding wires Source: John McMaster semipol/ ad534 39
41 Bonding pads Source: John cmaster 24c02 40
42 Bonding pads Source: John cmaster 24c02 40
43 Metal routing Source: John McMaster 24c02 41
44 Cell routing: Metal Source: ohn McMaster Sidoku /03/sidoku-1.html 42
45 Cell routing: Metal Source: ohn McMaster Sidoku /03/sidoku-1.html 42
46 Cell routing: Metal Source: ohn McMaster Sidoku /03/sidoku-1.html 42
47 Cell routing: Polysilicon Source: John McMaster Sidoku 43
48 Cell routing: Polysilicon Source: John McMaster Sidoku 43
49 Cell routing: Vias Source: John McMaster Sidoku 44
50 Cell routing: Vias Source: John McMaster Sidoku 44
51 Cell routing: Vias Source: John McMaster Sidoku 44
52 Cell routing: Vias Source: John McMaster Sidoku 44
53 Cell routing: Vias Source: John McMaster Sidoku 44
54 Diffusion layers Source: John McMaster 24c
55 Diffusion layers Source: John McMaster 24c
56 Diffusion layers Source: John McMaster 24c
57 Background knowledge 46
58 Charge carriers Electrons Holes Negative charge Positive Charge Typically less effective mass Move in direction of current Typically more effective mass Move in opposite direction of current 47
59 Voltage nodes 48
60 Open 49
61 Closed 50
62 No active current between equipotential nodes 51
63 Parallel vs Series
64 PMOS: Gate active low Vin Vout X 53
65 PMOS: Gate active low Vin Vout Vin = X 53
66 PMOS: Gate active low Vin Vout X 53
67 PMOS: Gate active low Vin Vout 0 1 Vin = 1 1 X 53
68 NMOS: Gate active high Vin Vout 0 X
69 NMOS: Gate active high Vin = 0 Vin Vout 0 X
70 NMOS: Gate active high Vin Vout 0 X
71 NMOS: Gate active high Vin = 1 Vin Vout 0 X
72 Combine for CMOS Inverter Vin Vout
73 Silicon zoo inverter 56
74 Metal 57
75 Metal 57
76 Power rails 58
77 Power rails 58
78 Vias 59
79 Vias 59
80 Vias 59
81 Polysilicon 60
82 Polysilicon 60
83 Diffusion 61
84 Diffusion -channel 61
85 Diffusion -channel N- channel 61
86 Silicon zoo inverter A Y 62
87 Silicon zoo inverter A Y 62
88 Silicon zoo inverter A Y 62
89 Silicon zoo inverter A Y 0 62
90 Silicon zoo inverter A Y 0 62
91 Silicon zoo inverter A Y
92 Silicon zoo inverter A Y
93 Silicon zoo inverter A Y
94 Silicon zoo inverter A Y
95 Silicon zoo inverter A Y
96 CMOS NAND 63
97 CMOS NAND Parallel 63
98 CMOS NAND Parallel Series 63
99 Silicon zoo NAND 64
100 Metal 65
101 Metal 65
102 Power rails 66
103 Power rails 66
104 Vias 67
105 Vias 67
106 Polysilicon 68
107 Polysilicon 68
108 Diffusion 69
109 Diffusion 69
110 Diffusion 69
111 Silicon zoo NAND A B Y
112 Silicon zoo NAND A B Y
113 Silicon zoo NAND A B Y
114 Silicon zoo NAND A B Y
115 Silicon zoo NAND A B Y
116 Silicon zoo NAND A B Y
117 Silicon zoo NAND Parallel A B Y
118 Silicon zoo NAND Parallel A B Y Series
119 Silicon zoo flip flop not so easy solvers whiteboarded this one! 71
120 Simulation with Magic CAD Convert image to polygons Simulate siliconzoo.org/tutorial.html 72
121 73
122 74
123 Completed drawing 75
124 Getting real Need a scientist Need tools Need to write software 76
125 DYI Imaging Costs Technology µm Cost Eyes 1000 Free Metallurgical microscope Desktop SEM Used SEM $1,000- $10,000 $25,000- $70,000 $50,000 - $250,000 p3x 22nm FIB - circuit editor $1-5M 77
126 Automated capture Automated stage and image capture Details: leveling fishbowl effect feature detection for stitching 78
127 Image recognition tasks Automated routing Polygon translation 79
128 Open Communities siliconpr0n.org siliconzoo.org visual6502.org opencircuitdesign.com 80
129 Software Magic & IRSIM: opencircuitdesign.com DeGate: degate.org Hugin: KLayout: 81
130 Preguntas? 82
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