Layout Analysis Embedded Memory

Transcription

1 Sample Report For any additional technical needs concerning semiconductor and electronics technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: Fax:

2 Table of Contents Table of Contents 1 Layout Analysis Embedded Memory 1.1 List of Figures 1.2 List of Tables 2 Device Overview 2.1 Introduction 2.2 Device Summary 3 Device Identification 3.1 Die 4 Memory Block Analysis 4.1 Annotated Die Photograph Memory Blocks 4.2 Memory Block Measurements 4.3 Memory Cell Plan View SEM Analysis 5 Statement of Measurement Uncertainty and Scope Variation About Chipworks

3 Overview Layout Analysis Embedded Memory This report gives an overview of the memories on a die, reporting on the physical size, logical size, and cell size of the largest memories overall on the chip, the most commonly used memory, the smallest memory, and the largest of each type of memory. This report contains the following information: Package photos Package X-ray Depot (bare die) die photograph Die size measurements Annotated metal 1 or poly die photographs showing the largest memory of each type, the 10 largest memories, the most common memory, and the smallest memory on the die Physical measurements of the memories listed above Cell size measurements for the smallest cell of each type of the memories listed above SEM plan-view images of cell layout at poly for the smallest cell of each type of memory (all SRAM variants, edram, OTP, and eflash) Number of rows, columns, bits, and cell efficiency of the memories listed above Table summarizing memory area and die utilization of the memories listed above (percentage of die, logical and actual bit size)

4 Overview List of Figures 3 Device Identification Die and Paddle X-Ray Die Die Markings Die Markings Die Markings 3 4 Memory Block Analysis Annotated Metal 1 Die Photograph Memory ROM Poly ROM Metal EEPROM Poly EEPROM Metal T SRAM Poly T SRAM Metal List of Tables 2 Device Overview Device Identification Device Summary 4 Memory Block Analysis Memory Block Measurements

5 Device Overview Device Overview 2.1 Introduction This report is a functional analysis (FAR) of the Contactless IC. Three types of memory are found on the die, ROM, EEPROM and a 6T SRAM. There is approximately 839 Kb of ROM, 29 Kb of EEPROM, and 4 Kb of SRAM. A VPP generator circuit is located next to the EEPROM, providing an internally generated voltage, required for the flash memory. Table Device Identification Package markings Die markings Date code Device Identification Table Device Identification

6 Device Overview Device Summary Table Device Summary Manufacturer Foundry Part number Type Date code Package markings Package type Die markings Die size (die edge seal) Process type Number of metal layers Number of poly layers Minimum transistor gate Process generation Feature measured to determine process generation Device Summary Table Device Summary

7 Device Identification Device Identification 3.1 Die Figure is an X-ray image of the die and its supporting metal header. The die is mounted inside a credit card (not shown), with two bond wires connecting the die to its supporting paddle. Two antenna wires are also seen contacting the paddle. Figure 3.1.1Die and Paddle X-Ray Figure Die and Paddle X-Ray antenna wire die Figure Die and Paddle X-Ray

8 Device Identification 3-2 The die is shown in Figure The die measures 1.95 mm x 2.72 mm within the die seals and has a 5.3 mm 2 area. Figure 3.1.2Die Figure Die Figure Die

9 Device Identification 3-3 The die markings found on the are shown in Figure through Figure Figure 3.1.3Die Markings 1 Figure Die Markings 1 Figure Die Markings 1 Figure 3.1.4Die Markings 2 Figure Die Markings 2 Figure Die Markings 2 Figure 3.1.5Die Markings 3 Figure Die Markings 3 Figure Die Markings 3

10 Memory Block Analysis Memory Block Analysis 4.1 Annotated Die Photograph Memory Blocks Three types of memory exist on the die: ROM, EEPROM, and 6T SRAM. Figure shows the type and location of each memory block. Figure 4.1.1Annotated Metal 1 Die Photograph Memory Figure Annotated Metal 1 Die Photograph Memory 6T SRAM ROM EEPROM Figure Annotated Metal 1 Die Photograph Memory

11 Memory Block Analysis Memory Block Measurements Table lists the measurements for the individual memory array blocks, identified in Section 4.1. The memory block length, width and area are given along with the unit cell area, as derived from the SEM analysis of Section 4.3. The logical blocks size were derived by dividing the memory macro block by the unit cell area. The actual size was obtained by counting the wordlines and bitlines in the selected blocks, and includes normal bits and any possible redundant bits. Table Memory Type (mm) Memory Block Measurements Block Length Block Width (mm) Block Area (mm²) Unit Cell Area (µm²) Logical Block Size (Bits) Memory Block Measurements Actual Wordlines Actual Bitlines Table Memory Block Measurements Actual Block Size (Bits) Efficiency (%) ROM ,176, , EEPROM , , T SRAM , ,

12 Memory Block Analysis Memory Cell Plan View SEM Analysis Figure and Figure are plan-view SEM images of the ROM at poly and metal 1, respectively. Each ROM cell is 0.81 µm long and 0.66 µm wide, yielding a cell area of 0.53 µm 2. The poly wordlines run horizontally in the image. Figure 4.3.1ROM Poly Figure ROM Poly Figure ROM Poly

13 Memory Block Analysis 4-4 Figure 4.3.2ROM Metal 1 Figure ROM Metal 1 Figure ROM Metal 1

14 Memory Block Analysis 4-5 Figure and Figure are plan-view SEM images of the EEPROM at poly and metal 1, respectively. Each EEPROM cell is 3.64 µm long by 1.24 µm wide, yielding a cell area of 4.51 µm 2. Figure 4.3.3EEPROM Poly Figure EEPROM Poly Figure EEPROM Poly

15 Memory Block Analysis 4-6 Figure 4.3.4EEPROM Metal 1 Figure EEPROM Metal 1 Figure EEPROM Metal 1

16 Memory Block Analysis 4-7 Figure and Figure are plan-view SEM images of the 6T SRAM at poly and metal 1, respectively. Each 6T SRAM cell is 3.44 µm long by 1.45 µm wide multi-port SRAM cell with a unit cell area of 5.0 µm 2. The wordlines implemented above metal 1, likely run vertically with respect to the plan-view poly image. Figure T SRAM Poly Figure T SRAM Poly Figure T SRAM Poly

17 Memory Block Analysis 4-8 Figure T SRAM Metal 1 Figure T SRAM Metal 1 Figure T SRAM Metal 1

18 Statement of Measurement Uncertainty and Scope Variation Statement of Measurement Uncertainty and Scope Variation Statement of Measurement Uncertainty Chipworks calibrates length measurements on its scanning electron microscopes (SEM), transmission electron microscope (TEM), and optical microscopes, using measurement standards that are traceable to the International System of Units (SI). Our SEM/TEM cross-calibration standard was calibrated at the National Physical Laboratory (NPL) in the UK (Report Reference LR0304/E /SEM4/190). This standard has a 146 ± 2 nm (± 1.4%) pitch, as certified by NPL. Chipworks regularly verifies that its SEM and TEM are calibrated to within ± 2% of this standard, over the full magnification ranges used. Fluctuations in the tool performance, coupled with variability in sample preparation, and random errors introduced during analyses of the micrographs, yield an expanded uncertainty of about ± 5%. The materials analysis reported in Chipworks reports is normally limited to approximate elemental composition, rather than stoichiometry, since calibration of our SEM and TEM based methods is not feasible. Chipworks will typically abbreviate, using only the elemental symbols, rather than full chemical formulae, usually starting with silicon or the metallic element, then in approximate order of decreasing atomic % (when known). Elemental labels on energy dispersive X-ray spectra (EDS) will be colored red for spurious peaks (elements not originally in sample). Elemental labels in blue correspond to interference from adjacent layers. Secondary ion mass spectrometry (SIMS) data may be calibrated for certain dopant elements, provided suitable standards were available. A stage micrometer, calibrated at the National Research Council of Canada (CNRC) (Report Reference LS ), is used to calibrate Chipworks optical microscopes. This standard has an expanded uncertainty of 0.3 µm for the stage micrometer s 100 µm pitch lines. Random errors, during analyses of optical micrographs, yield an expanded uncertainty of approximately ± 5% to the measurements. Statement of Scope Variation Due to the nature of reverse engineering, there is a possibility of minor content variation in Chipworks standard reports. Chipworks has a defined table of contents for each standard report type. At a minimum, the defined content will be included in the report. However, depending on the nature of the analysis, additional information may be provided in a report, as value-added material for our customers.

19 About Chipworks About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at: Chipworks 3685 Richmond Rd. Suite 500 Ottawa, Ontario K2H 5B7 Canada T: F: Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com