STMicroelectronics STM32F103ZET6 32 Bit MCU Embedded NOR Flash

Transcription

1 32 Bit MCU Embedded NOR Flash Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: Fax:

2 Process Review Table of Contents 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2.1 Package and Die 2.2 Die Features 3 Planar Analysis 3.1 Flash Memory Array Architecture 4.1 Flash Memory Array Plane of Cross-Sectioning 4.2 Cross-Sectional Analysis Parallel to Sourceline 4.3 Cross-Sectional Analysis Parallel to Bitline 5 Critical Dimensions 5.1 Metals, Contacts, and Vias 5.2 Transistors, Poly, and Isolation 6 Process 6. 7 Functional Analysis 7. 8 References 9 Statement of Measurement Uncertainty and Scope Variation Report Evaluation

3 Overview List of Figures Package Photograph Top Package Photograph Bottom Package X-Ray Plan View Die Photograph Die Markings Die Corner Minimum Pitch Bond Pads 3 Planar Analysis Annotated Die Photograph Plan-View Image of Memory Array at Diffusion Large Block Plan-View Image of Memory Array at Poly 2 Large Block Plan-View Image of Memory Array at Poly 2 Block Detail Plan-View Image of Memory Array Metal Plan-View Image of Memory Array Metal Array at Poly 2 Planes of Cross-Sectioning Sourceline General Structure Sourceline Detail Bitline Contacts General Structure Bitline Contacts Detail Wordline Contacts Detail Wordline and Floating Gate Detail Metal 1 Bitline General Structure Pair of Flash Memory Cells Si Etch Detail of Flash Memory Cell Glass Etch SEM Image Along Metal 1 Sourceline Strap Si Etch 6 Process General Device Structure Minimum Pitch Metal Minimum Gate Length Transistor Minimum Contacted Gate Pitch 7 Functional Analysis Major Functional Blocks

4 Overview List of Tables Device Summary Summary of Major Findings Package and Die Dimensions Metals, Contacts, and Vias Transistors, Poly, and Isolation 5 Critical Dimensions Metals Contacts and Vias Transistors, Poly, and Isolation

5 About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at: Chipworks 3685 Richmond Rd. Suite 500 Ottawa, Ontario K2H 5B7 Canada T: F: Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com