Spidergon STNoC: The technology that adds value to your System. Marcello Coppola
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1 Spidergon STNoC: The technology that adds value to your System Marcello Coppola
2 Agenda Setting the stage Overview on Spidergon STNoC Spidergon STNoC backbone User experience Communication Primitives & Services Spidergon STNoC today Conclusions 2
3 Moore s law in real life Few applications Pseudo static behavior Many applications Dynamic behavior 1 algorithm ASIC 1 application MEM B CPU U S Single micprocessor SoC MEM MEM MEM IP CPU CPU CPU C R O S B A R CrossBar-based multiprocessor SoC Middleware Operating system SW & HW multi-tasking Heterogeneous multiprocessing On-chip communication network Memory hierarchy SW Configurable SoC platform Infrastructure SW HW 3
4 Multicore SoC architecture: 2004 vision Masters HOST HOST CPU CPU DSP DMA VLIW VLIW DSP DSP DSP DSP HW HW IP IP Programmable Parallel Engine interconnect SoC interconnect Ext Ext Mem Mem Ctrl Ctrl Embedded Embedded Mem Embedded Embedded Mem Mem IO IO IO IO Mem Embedded Mem In package memory secondary target Registers Slaves towards. Open Confi gurabl e Heterogeneous Mul ti core Pl atforms
5 Agenda Setting the stage Overview on Spidergon STNoC Spidergon STNoC backbone User experience Communication Primitives & Services Spidergon STNoC today Conclusions 5
6 Spidergon STNoC at a glance Best in class for multi-protocol support (AMBA, STBUS, custom) Solving wire congestion and time closure problems without any area penalty Reduce SoC NRE Several Innovative Services Configurable end extensible technology Fully integrated with state-ofthe-art verification environment Allow post silicon reconfigurability by software 6
7 Spidergon STNoC technology Spidergon STNoC is set of Communication Primitives and Services implemented on top of a distributed on-chip network (NoC backbone) that connects several components. Communication Primitives Platform Services Read/Write Security Power IOMMU Fault Tolerance AXI3 AXI4 STBus Cache Coherence QoS Multi-paths Virtual Channels Socket Interoperability Spidergon STNoC Backbone 7
8 Agenda Setting the stage Overview on Spidergon STNoC Spidergon STNoC backbone User experience Communication Primitives & Services Spidergon STNoC today Conclusions 8
9 Spidergon STNoC backbone The on-chip network is based on 3 well-defined configurable components called: Network Interface Router Physical link
10 Communication Primitives Natively support (without bridges) different socket protocols (AXI, STBUS, OCP, custom, etc.) Efficient upsize and downsize conversion 32 A X I parallel wires A X I NI flits Router O C P O C P NI flits Router 64 parallel wires
11 Network Interface IP protocol Shell Handshake Handshake IP IP protocol protocol Encodes Encodes IP IP protocol protocol Programming Programming Security Security access access Kernel SSTNoC SSTNoC packet packet assembling assembling Frequency Frequency Conversion Conversion Error/Power Error/Power Management Management Error Man. Unit Unit SSTNoC Interface SSTNoC packets ni_i_top shl_req krn_req emu_top sl_us_itf shl_rsp krn_rsp sl_ds_itf error_management_on request path response path
12 Network Interface Features Data bus / flit Size Conversion Upsize Downsize No conversion Frequency Conversion Gray counters (any even number of FIFO locations) 2 to 4 Synch. Flip Flops 0 to 3 cycles configurable crossing latency Store & Forward IP Prot to S-STNoC (packet, chunk, msg) S-STNoC to IP prot (S-STNoC packet) Error Management Security Management Transaction ordering support Single/Multiple Target QoS support Programming Unit Routing (Dir1, Dir2, DestID fields) QoS FBA fields Security STBus T1 or APB interface
13 Spidergon Router The Router implements the network and the data link layers of the NoC protocol, offering best effort and possible quality of service (QoS) in terms of both latency and throughput It is responsible for the transmission of the flits The router supports 2 Virtual Channels Left Hierarchy ROUTER Across Right Network Interface flit_be flit flit_id flit_id_3 flit_id_err flit_id_atomic four_be val credit 0 flit_data us_flit Example 72-bit flit 13
14 Spidergon STNoC request/response networks Spidergon STN oc technology allow s you to design separated request/ response netw orks Initiators Targets Initiators Targets Initiators Request response network request network response network Router Router Router request & response switch Less wires per router 14
15 Router Features Each Link (L, R, A, NI, H), Port (DS, US), VN (VN1, VN2) is individually instantiable and configurable Back routing support Configurable flit size: flit payload size16/18, 32/36, 64/72, 128/144 bits, plus flit extra bits Optional registers on credits IB with/without bypass capability and Optional retiming stage: configurable crossing latency (1 cycle or 2 cycles) Configurable Output Queue size: 0 64 flits When zero, OQ is not instantiated Configurable number of Output Queues to NI QoS Support Configurable basic arbitration scheme within a faction: LRU, RR, pk_priority Configurable virtual channel arbitration scheme: LRU/RR, VN_priority (w/ & w/o lock packet) Routing Unit support for hierarchical networks: H link is a gateway between 2 S-STNoC sub-networks Routing Unit support for Spidergon Routing or Source Routing mechanisms
16 Physical Link Com posed by a set of wires, an upstream logic and a downst ream logic Enable efficient physical im plem entation Synchronous version, Adapt ive version Optim ized flow control with virtual channel support Fixed upstream interface Fixed downstream interface flitid Spidergon component US DS valid credit flit Spidergon component 16
17 GALS: some previous works 1. Pausible Clocking Yun (ICCAD-96); Villiger et al./eth (ASYNC-03) 2. Latency-Insensitive Systems Carloni, Sangiovanni-Vincentelli et al. (ICCAD-99); 3. Static Scheduling Casu, Macchiarulo (DAC-04) 3. Fine-Grain Synchronous Handshaking Jacobsen et al./ibm (ASYNC-02) 17
18 Latency Insensitive Design (LTI) [ICCAD99] P1 P2 P3 P4 Pearls (synchronous IP cores) Shells ( speaking the latency insensitive protocol) Channels (short wires) Channels (long wires) P6 P5 P7 Source: L. Carloni 18
19 Latency Insensitive Design (LTI) [ICCAD99] P1 RS RS P3 RS Relay Stations RS P2 P4 RS RS Pearls (synchronous IP cores) Shells ( speaking the latency insensitive protocol) Channels (short wires) Channels (long wires) RS P6 RS P7 P5 RS Source: L. Carloni 19
20 Adaptive Link Different link configurations for different purposes us ds us ds RelayStation: configuration used to break long link (backend oriented) us ds freq. conv us ds Alink with freq. conv: used to cross frequency domain us ds size conv us ds Alink with size conv: used to adapt flit size us ds Volt. conv us ds Alink with volt. conv: used to support multiple voltage domain 20
21 Features and configurability Each VN (VN1, VN2) is individually instantiable and configurable (both DS and US are activated on the selected VN) Configurable flit size: flit payload size 16/18, 32/36, 64/72, 128/144 bits, plus flit extra bits Optional registers on credits IB with/without bypass capability and optional retiming stage: configurable crossing latency Configurable virtual channel arbitration scheme: LRU/RR, VN_priority (w/ & w/o lock packet) DS/US flit size conversion support (instantiates FIFOs) Frequency conversion support (instantiates bisynchronous FIFOs) When FIFOs on, can support Store&Forward: Per NoC packet Per NoC packet per flit threshold Separate FIFOs for header and payloads: Optimized Header FIFO width Flexibility for advanced S&F control Depending on traffic type, removes unnecessary Payload FIFO NOTE: DS/US flit sizes cannot both be lower than header width NOTE2: DS and US flit extra bits sizes cannot be random. Either they are zero (at least one of them) or they stay in the same ratio as DS and US flit payload sizes NOTE3: four_be conversion/management not supported for flit payload size 16/18
22 Agenda Setting the stage Overview on Spidergon STNoC Spidergon STNoC backbone User experience Communication Primitives & Services Spidergon STNoC today Conclusions 22
23 The User Experience How a product behaves and is used by people in the real world every product that is used by someone has a user experience: newspapers, ketchup bottles, reclining armchairs, cardigan sweaters. (Garrett, 2003) User Experience the way people feel about it their pleasure and satisfaction when using it, looking at it, holding it, opening or closing it
24 The best experience out of the box. Action Multicore Feedback L2 L2 L2 Multicore L1 Multicore Multicore Core On-demand accelerators Video Graphics Imaging Audio System Functions On-Chip Network PCIe Connectivity USB MIPI Memory CTRL Periperals PHY PHY PHY
25 Agenda Setting the stage Overview on Spidergon STNoC Spidergon STNoC backbone User experience Communication Primitives & Services Spidergon STNoC today Conclusions 25
26 Spidergon STNoC: the Software A software Library (libstnoc) and set of device drivers to programme interconnection behaviour of SoC architecture and to take advantage of built-in NoC services (Power, QoS, Security, MMU, Diagnostic, etc.) 26
27 Spidergon STNoC driver The driver exposes in files the NoC configuration information (base address, routing type etc) Routing, QoS, and security information Through writable files, writing to the files updates the configuration registers Last Register status Possible destinations Alternative paths for source routing
28 Spidergon STNoC Library: Libstnoc Libstnoc provides a high level C API, abstracted from the details of register format A simple interface to allow applications to optimize the NoC at any time for their requirements. High level get and set functions for routing, QoS. Error handling/valid data checks before applying to the registers. Higher level functionality: profile switching / requirements based reprogramming of the NoC. Libstnoc
29 NoC aware applications on Android The Conent Provider, provides access to STNoC functionality to the whole Java based Android Application Framework. Possible Applications. GUI on-device debug interface for the NoC. Parameters adjustment when receiving a phone call, in flight mode, in standby etc. Adjustments for performance or low power.
30 Platform Services: An example Communication Primitives Platform Services AXI3 Read/Write AXI4 STBus Cache Coherence Security QoS Power QoS Multi-paths IOMMU Virtual Channels Fault Tolerance Socket Interoperability Spidergon STNoC Backbone
31 Dynamic resource usages: the web browser The Software Stack: An overview Libstnoc STNoC Driver 31
32 Dynamic resource usages: face time 32
33 Service: Programmable QoS long devxxxread (struct airecord *pai) { if (pai->pact) [ return S_devXxx_OK; /* zero */ } pai->pact = TRUE devxxxbeginasyncio(pai->dpvt); return S_devXxx_OK; } Average DDR BW is 1GB/s DMA 6% Initiators 24% 43% 16% Graphics Video Core S-STNoC ethernet PCI CPU Graphics Audio 11% DMA Video Core Audio Peripherals
34 Towards IPU IPU = Interconnect Processing Unit IPU Services are implemented in hardware and/or software Communication Primitives Low level Platform Services Source: Design of cost efficient Interconnect processing unit:spidergon STNoC, ISBN:
35 Agenda Setting the stage Overview on Spidergon STNoC Spidergon STNoC backbone User experience Communication Primitives & Services Spidergon STNoC today Conclusions 35
36 Where is Spidergon STNoC today? Spidergon STNoC is not only a standard NoC technology but it is an innovative technology able to provide real product differentiation through a set of smart hardware/software software services ST on-chip communication network strategy in following years in consumer, multimedia, mobile etc. External company licensing (eg. STE) 36
37 Spidergon in real SoC: The hybrid NoC 37
38 For more info Book published by CRC press Spidergon STNOC book ISBN: Publication Date: September 2008 Web based info from European/Catrene funded projects 3DIM3 COMCAS MODERN SHAPES.. 38
39 39
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