Fully Depleted SOI Technologies. Bich-Yen Nguyen

Transcription

1 Fully Depleted SOI Technologies Bich-Yen Nguyen

2 Acknowledgements SOITEC Team: Jean-Michel Bidault Nicolas Daval Frederic Allibert Ludovic Ecarnot Konstantin Bourdelle Walter Schwarzenbach Mariam Sadaka Phuong Nguyen Carlos Mazure Olivier Bonnin Christophe Malevillle Justin Wang CEA/Leti Team: Olivier Weber Francois Andrieu Maul Vinet Olivier Faynot IBM Team: Kangguo Cheng Ali Khakifirooz Bruce Doris Ghavam Shahidi STM Team: Qing Liu Franck Arnaud Nicolas Planes Giorgio Cesana Global Foundries : Scott Luning 2

3 CMOS Landscape Beyond 28nm Node Value propositions of the Planar Fully Depletet SOI Technology Performance and Power Benchmarking FDSOI Device and Substrate Roadmap Summary

4 CMOS Landscape Beyond 28nm 4

5 Challenges of Continued CMOS Scaling Increased standby power dissipation Amplified V th variability Source: IBM, T.C. Chen, ISSCC Impact Yield Limit Vdd scaling

6 Leakage Power is still a Major Issue Despite the Use of Hi-K Dielectric High-K/Metal Gate Stack SiON/Poly Gate Stack Source: IBS 6

7 New Device Architectures nm 45 nm 22nm 65nm 32nm Strained Silicon Introduction of New Materials High-K / Metal Gate Introduction of New Device Architecture Fully Depleted Devices MOS-AK/GSA Workshop, April

8 Fully Depleted Technology Landscape Intel IBM STM Foundries 16/14 nm Foundries Foundries

9 Value Propositions of the Planar Fully Depleted SOI Technology 9

10 Alternate FD Device Architectures: Planar FDSOI or Vertical Multi-Gate FinFET-SOI G S D Minimum Design Disruption S G D Buried OX Max scalability S G D Bulk Si Conventional Planar Bulk Transistor Bulk Si Planar Single-or double Gate FDSOI Buried oxide Vertical Multiple-Gate FinFET SOI

11 The End of Conventional MOSFET- The Era of FD Device Architecture 22nm Planar 11

12 Planar ETSOI Structure and Advantages Gate Material Junctions Film & BOX Isolation Body Bias Thin Silicon Channel Ground Plane Hybrid Bulk Total dielectric isolation Lower S/D capacitances Lower S/D leakages Latch-up immunity Ultra thin Body (TSi~1/3LG) Excellent short channel immunity =>Low SCE, small SS & DIBL No channel doping, no pocket implant Improved V T variation Ultra thin BOX option Back bias control Ground plane implantation V T adjustment Source: STM J. Hartmann,, GSA Apr. 2012

13 Threshold Voltage Mismatch vt (mv.µm m) A v Source: Thean et al, Freescale, IEDM2003 Measurement Bulk 1 Bulk 2 Bulk 3 Bulk 4 PDSOI FDSOI 60% Reduction 50% Reduction nmos pmos A vt = q 2 N ch W dep / C ox A Vt (mv.um) Benchmarking Bulk platform FDSOI MOSFETs This work FDSOI IBM alliance 32nm ST FDSOI ST 45nm Intel 65nm Intel 45nm ST 65nm ST GAA IBM 90nm IMEC FinFET Hitachi FDSOI Source: O. Weber et al, Leti CEA, IEDM2007 Gate length L (nm) Square Vd=1V circle Vd=50mV Device matching important to SRAM/Analog circuits (eg. Current mirrors) FDSOI (undoped channel) features 50-60% mismatch improvement over bulk CMOS and PDSOI (doped channel) 13

14 Scaling rules down to 8nm node TCAD with Electrostatic considerations Required TSOI (nm) NanoWire TSOI (thick BOX=145nm) TSOI (UTBOX case) nm 10nm 25nm T BOX = 145nm T BOX = 25nm DIBL=100mV/V L G (nm) 5nm Tsi Scalability possible down to L G ~10nm, thanks to UTBOX Courtesy of CEA-LETI, O. Faynot et. al. IEDM 2010; 14

15 Multi-VT Solution with Dual Metal Gate/GP ld voltage (V) 0,8 0,6 0,4 0,2 0 Logic SRAM LVT RVT HVT SHVT nmos GP-N GP-P GP-N GP-P nmos pmos TiN LVT TaAlN BOX BOX N-GP P-GP Metal nmos pmos TiN RVT TaAlN BOX BOX P-GP N-GP GP change change nmos TaAlN BOX N-GP nmos TaAlN BOX P-GP HVT SHVT pmos TiN BOX P-GP pmos TiN BOX N-GP Threshol -0,2-0,4-0,6 GP-P pmos GP change GP-N metal change GP-P GP-N -0,8 TiN TaAlN/TaN O. Webber et al., IEDM 10 Multi Vt requirement for SoC can be achieved for FDSOI device using dual WF metal-gate and ground-plane approach without back-bias MOS-AK/GSA Workshop,, April 11-12, 2013

16 Body Bias: Speed & Power Control FDSOI Workshop San Francisco, Feb FDSOI MOS-AK/GSA Workshop, April 11-12,,

17 Multi-VT Modulation for ETSOI with Back Bias Leti- VLSI 2010 Q. Liu, ST, VLSI 2010 VT tuning with BOX = 10nm and VBB, GP N and PMOS: VT modulation of 200mV for 10nm BOX No degradation of Ion-Ioff trade-off with back-bias up to +/-2V 17

18 C2 - Confidential 18

19 C2 - Confidential 19

20 ETSOI Structure by IBM Lg= 25nm Tsi= 6nm B - SiGe K. Cheng et al, IBM, VLSI 2009 In-situ boron doped SiGe S/D: Lower S/D resistance Reduces parasitic capacitance 20

21 20nm FDSOI Performance Improvement VLSI nm FDSOI on Thick BOX K. Cheng et al, IBM, VLSI 2011 Ion for both N- and PMOS improved by optimizing S/D resistant and Tinv. 20nm FDSOI RO delay at 0.9v improved by 20% as compared to those of 28nm Bulk RO C2 -at Confidential 1v 21

22 Boosting FDSOI Performance with subtrate & strain engineering IBM, A. Khalifizoor-VLSI 2012 More perf gain DC performance of FDSOI is comparable to state of the art planar-bulk devices Smaller Lg and junction area => better AC performance 22

23 C2 - Confidential 23

24 C2 - Confidential 24

25 FDSOI in a Nutshell FD SOI solves most of the CMOS scaling challenges FD SOI is SoC friendly FD SOI design is equivalent to Bulk FD SOI process cost equivalent to Bulk LP (28nm) FD SOI is a scalable technology FD SOI is risk-free alternative to FinFET for LP/G products 25

26 Planar FD SOI Value Proposition FD SOI brings a easy manufacturing path to develop high h performance and low power CMOS process derivatives Simple planar technology and transistor architecture High performance at low supply voltage Easy way to build different VTs for SoC design On top of poly biasing, body biasing bring tremendous flexibility to the SoC design FD SOI enables time effective technology and design solutions Re-use of most of the Bulk process FEOL modules, BEOL is fully identical Migrating digital it Bulk libraries i and designs to FD SOI is a re-characterization ti and signoff FD SOI wafer easily etched to implement bulk structures and IPs EDA flow and design techniques remain identical as Bulk FD SOI delivers a same performance as those 28nm HP technologies, without back bias (BB) or higher performance with BB at the cost of a 28nm LP process 26

27 Planar FDSOI vs. Bulk Performance/Power Benchmark 27

28 CONFIDENTIAL

29 CONFIDENTIAL

30 CONFIDENTIAL

31 IBM Research (A/ /µm) FP + I OF I OFFN RO Comparison (ETSOI vs. FinFET) ETSOI FinFET V 10-8 V DD = 0.9V 0.8V 0.7V Delay (ps/stage) I off = 200nA/µm V DD RO Delay (ps/stage) 0.9V 0.7V ETSOI finfet* 13.5 *C. Auth, et al. Presented at Symp. VLSI Tech., 2012 ETSOI RO is faster than state-of-the-art the art finfet Courtesy of Bruce Doris, IBM K. Cheng et al. IEDM

32 Yield Learning Equivalent to Bulk Process

33 Planar FDSOI Adoption and Roadmap 33

34 CONFIDENTIAL

35 CONFIDENTIAL

36 FD SOI Migration Path 28nm FDSOI 28nm SLP 113CPP 90Mx 113CPP 90Mx nm FDSOI 20nm LPM 90CPP 64Mx 90CPP 64Mx Courtesy of ST Low risk and effective TTM strategy to migrate Bulk platforms to FD SOI Straightforward path to re re-characterize characterize 20nm LPM design environment to 14nm FD SOI 36

37 Soitec FD-2D Substrate Options Ultra Thin Top Silicon Layer Ultra Thin Buried Oxide Base Silicon Ultra Thin Top Silicon Layer Ultra Thin Buried Oxide S G D Base Silicon Base Silicon Ultra Thin Top Silicon Layer Ultra Thin Buried Oxide Base Silicon S G D Soitec FD-2D Evo20 S G Base Silicon D Soitec FD-2D Evo14 with ssoi Sampling now: SOI + strain Soitec FD-2D Evo28 In prod now Base Silicon Sampling now 28 nm 22 nm / 20 nm 15 nm / 14 nm 37

38 FD-2D Substrate Uniformity: Thin SOI & Thin Box SOI BOX Base wafer Perc centage Percentage nm BOX 250 ±6 A W2W Range < 7 A Wafer-to-wafer thickness (Å) BOX Thickness Mean Min Mean Max A A A BOX Thickness Mean Within wafer thickness (Å) BOX Thickness Range Min Mean Max 2.7 A 44A A SOI Thickness 3.13 A 6sigma +4Å +2Å 120Å -2Å -4Å W2W thickness 120 ±5 5A ints SOI rol (Å) All wafers, all po thickness contr BOX Thickness Range 1 year production at prime spec 12 April

39 Summary 39

40 Planar FD SOI Summary 1. FD SOI provides outstanding benefits for high performance, battery powered devices Leading edge performance across the full Vdd range Good speed vs leakage trade-off Record Vdd min for logic and SRAM Full flexibility in IP design with dynamic voltage scaling and biasing Better performances than a G process at the cost of an LP technology 2. FD SOI offers a low risk design and manufacturing path for CMOS process derivatives at 28, 20 and 14nm No major disruption from current Bulk CMOS process manufacturing Same EDA flow and design techniques as planar Bulk Digital designs easy to re-characterize on FD SOI 3. Industry first Fully-Depleted SOC using 28nm FDSOI technology was demonstrated by STM/STE with 3GHz performance 4. 28nm and 14nm FD SOI will be available in foundries in 2013 and 2014, respectively

41 FD-SOI provides unique value Faster Transistors run at higher frequencies up than bulk CMOS enabling faster processors This puts more powerful devices in the hands of the end user Cooler Transistors are more power efficient than bulk CMOS with lower leakage and much wider range of operation points down to lower voltages End user devices run cooler and last longer. Simpler The manufacturing process for FD-SOI is much simpler than alternatives and making extensive use of existing fab infrastructure Design porting from bulk is simple and fast Chip architecture t and construction ti are simpler and software is simpler for devices manufacturers 41 (10)

42 Thank You