Physical IP Solutions

Transcription

1 Physical IP Solutions Bryan Lawrence Solutions Marketing 1 Physical IP Product Focus Library platforms Standard cells Embedded memory I/O functionality High-speed interfaces Serial PHYs DDR DDR Pervasive SoC IP Standard Cells Serial PHYs I/O Cells 2

2 ARM Artisan Physical IP Platforms Mainst ream Pl atform Perfo rmance Platfo rm Den sity Optimiz ed Platfo rm High-Speed PHYs SAGE-X Standard Cell Advantage Standard Cell Metro Standard Cell PCI-Express Single/Dual Port SRAM Single/Dual Port SRAM Single/Dual Port SRAM Serial-ATA 1/2-Port Register File 1/2-Port Register File 1/2-Port Register File XAUI ROM Via or Diffusion ROM Via or Diffusion ROM Via or Diffusion DDR/DDR2/GDDR3 GPIO Inline/Staggered GPIO Inline/Staggered GPIO Inline/Staggered Power Management Kit Power Management Kit Analog/Mixed Signal PLLs, DLLs Specialt y I/Os Analog/Mixed Signal PLLs, DLLs Specialt y I/Os Analog/Mixed Signal PLL, VREG, OSC, Specialt y I/Os 3 Library Platforms Power Performance Area pow er pow er 1/5 pow er 1/2 performance System requirement performance System requirement performance System requirement area area area 80% ~100% 4

3 Advantage Overview Perfo rmance Platfo rm Advantage Standard Cell Single/Dual Port SRAM 1/2-Port Register File ROM Via or Diffusion GPIO Inline/Staggered Power Management Kit Analog/Mixed Signal PLLs, DLLs Specialt y I/Os Performance-optimized physical IP products for nanom eter designs Memories provide 40% speed improvement and 50% power improvement over Classic architectures Standard cells provide up to 25% speed improvement over Classic architecture Lower die costs Flex-Repair redundancy for yield DFM for improved yield Ring-less power routing to reduce area Targeted at high-performance design Replaces Classic architecture at 90nm and below Available for 130nm, 90nm and 65nm processes 5 Advantage Platform Standard Cell Libraries Advantage Advantage-HS Advantage- CE Target designs Speed and density optimized High Performance Highest Performance Speed Power Area # Tracks high 9/ Well taps separate separate separate Metal usage M1 only M1 only M1 only Wide selection of standard cell libraries enables optimal design performance Use different libraries in different blocks 6

4 Metro Overview Den sity Optimiz ed Platfo rm Metro Standard Cell Single/Dual Port SRAM 1/2-Port Register File ROM Via or Diffusion GPIO Inline/Staggered Power Management Kit Analog/Mixed Signal PLL, VREG, OSC, Specialt y I/Os Density and power-optimized physical IP products Enables designs with up to 80% lower power than traditional products Using voltage islands and dynamic voltage/frequency scaling Dynamic and static power management Enables multi-voltage SoC designs and complements ARM Intelligent Energy Manager (IEM) Compatible with latest releases of EDA vendor power-optimized flows Increased design productivity Targets battery-powered applications Area efficient Moderate performance Improved yield Available for 180nm, 130nm, 90nm and 65nm processes 7 Metro Standard Cell Features & Benefits Dynamic power reduction techniques Clock-gating cells enable clock-based power management Careful attention to P:N ratio and stage ratios to limit switching currents Distribution of drive strengths minimizes over-design Shorter cell height minimizes power at moderate speed while providing high density Leakage Power reduction techniques Cell GDS supports mix and match of different V t in adjacent cells Well contacts outside cell enable leakage reduction through well biasing Timing views (.lib) with State-dependent leakage power for best estimation of power dissipation. 8

5 Generator Range Ports Single-Port SRAM 256bits - 512Kbits 1 R/W Port Dual-Port SRAM 128bits - 256Kbits 2 R/W Ports Single-Port Register File 64bits - 32Kbits 1 R/W Port Two-Port Register File 16bits - 16Kbits 1 R Port, 1 W Port ROM 128bits - 2Mbits 1 R Port 9 Feature Design-for-Manufacturability (DFM) compliant design and characterization techniques Flex-Repair redundancy Extra timing margin adjustment Benefit Improv ed yield Lower die cost Soft Error Repair RTL Integrated BIST Muxes ArtiGrid Over-the-cell power routing Low -v oltage functionality and characterization Power down modes: standby, retention and shutdown Shorter development time Lower die cost Smaller die area Lower die cost Dynamic power control Leakage power control 10

6 ARM Power Management Kit Available in both Metro and Advantage platforms Voltage level shifter and isolation cells Up and down shifting with optional enable signal MT-CMOS power gates Power control of voltage islands via switchable voltage rails using header- (shown) or footer-switch cells VDD1 VDD1 VDD2 VDD2 Retention flip-flops Maintain FF state after power down for leakage reduction VDD1 Global VSS Global VDD VDD2 Note: P ictur e shows a conc eptual implementation Enables implementation of advanced power management system architectures 11 Power Optimized Designs Enabled Metro Advantage Dynamic Power Control Clock gating standard cells Voltage level shifters Extended operating range of standard cells and memories DVFS support Leakage Power Control Multi V T support in standard cells Power gating of standard cells Retention flip flops Power gating and power down modes in memories 12

7 I/O Products Complete the Platform Speed Specialty I/O SSTL I, II HSTL I, II LVDS SSTL_18 USB 1.1 General Purpose I/O Input only I/O; 2 24 ma drive Multiple slew rates Output only LVTTL, Schmitt trigger inputs Oscillators, Analog pads 250 nm 180nm 130 nm 90 nm 65 nm Process Geometry 13 Extensive EDA Support Standard EDA Packages Comprehensive coverage Consistent deliverables Verilog and VHDL/Vital Synthesis/timing/power Place-and-route abstracts Schematic symbols GDSII files and LVS netlists EDAPlus Extended support Signal integrity Noise Power DFT Downloadable From the Web 14

8 ARM Supports Leading Manufacturers Atmel AMD LSI Logic National Jazz IBM Infineon ST NEC Hynix Sanyo DongbuAnam Seiko Epson Tower SMIC Sharp HHNEC Sony HeJian TSMC UMC Chartered Vanguard 1 st Silicon Silterra IDM Foundry 15 Connecting Manufacturers with Designers World s Leading IC Manufacturers ARM Physical IP User Community 2,000+ Companies, Estimated 10,000 Design Teams 16

9 ARM Access Library Program Innovative business model enables easy access to products for customers using pure-play foundries Access library program Foundry licenses platform products from ARM Platform products developed by ARM and distributed on ARM website License agreement between ARM and design customer License fees paid by foundry Royalties paid by foundry 17 Access Library Program License $ Foundry Product License Foundry Completed Designs Production Orders SOC Design Teams Fabless IC Companies IDMs Partners Foundry IP Products Optional Support Foundry Wafer Production Royalty $ SOC Design Teams Fabless IC Companies IDMs Partners SOC Design Teams Fabless IC Companies IDMs Partners 18

10 Access Program Product Availability Choices Chartered IBM TSMC UMC SMIC Tower 1 st Silicon Dongbu HeJian HHNEC MagnaChip Silterra Vanguard 250nm nm nm 1 Metro for 9FLP/10LP, Advantage for 9SF/10SF(HS); products for 10LP/10SF under development 2 Metro for L130e, Classic for other 130, Advantage for L90SP 3 Advantage for CLN 90G/G-OD/GT available; CLN65G under development nm nm Velocity High-Speed Interfaces Library platforms Standard cells Embedded memory I/O functionality High-speed interfaces Serial PHYs DDR DDR Pervasive SoC IP Standard Cells I/O Cells Serial PHYs 20

11 Velocity High-Speed Interfaces CPU Graphics PCIe System Controller Controller DDR Subsystem Hard Disk Driv e I/O Controller Local I/O SATA PCIe Gb Ethernet Add-in Cards XAUI Router/Switch Serdes Backplane 21 Serial Link: New System Economics Serial I/O 0.13um 230K/mm** u pitch Taking the Path to Higher Performance and Lower Cost 0.18um 115K/mm**2 Parallel I/O u pitch Active Area Unused Area I/O Area 0.13um 230K/mm** u pitch Smaller die size Smaller package size Fewer package pins Less power Scalable bandwidth High-Speed Serial Interfac es Offer Many Advantages 22

12 Velocity High-Speed Interfaces 130nm Series 90nm Series 65nm Series PCI Express XAUI/1-3.2Gbps Backplane 1-6.4Gbps Backplane Serial ATA DDR 1/2 GDDR3 In Development Engineered to save you time and money Superior jitter performance, small size and low power Scalable, advanced platform architecture to meet future higher bandwidth requirements Extensive programmable features offer integration flexibility Built-in test for improved manufacturability 23 Small Size and Low Power TX/RX Lane PCS Layer SerDes Core ESD < 250µm < 600µm Application Dependent Low-power features < 65mW/lane average Most of the circuitry, including driver, run off 1.0V/1.2V Extensive power down controls for precise control Smallest size in the industry < 0.20mm 2 per lane Area includes ESD, BIST with pattern generators and receivers in each lane 24

13 Broad Lane Configuration Support 16 Lane PHY 8 Lane PHY 4 Lane PHY 2 Lane PHY 1 Lane PHY Flexible configurations ready for instantiation Standard configurations of 1, 2, 4, 8 and 16 lanes Standard bump pitches of 175µm, 200µm, 225µm 25 Extensive Manufacturing Test Support ARM has designed a comprehensive built in self test capability that enables a standard tester to be used in production Analog test bus High-speed analog BIST CDR/Phase Interpolator test Serial Control Register (SCR) Scan built in to all digital JTAG support DC and AC FIFO Parallel Loopback RX De-Serializer - TX Serializer RCLK Loopback RX CDR Line Loopback Serial Loopback TX RX AC JTAG To Package Fr om Package 26

14 Designed for Easy Implementation Excellent noise immunity and signal integrity Fully differential circuitry in transmitter, receiver, PLL On-chip regulator for VCO power supply minimizes effects of power supply noise Built-in seawall isolation to protect macro from substrate noise Few external components required On-chip AC coupling capacitors, only 1 external resistor required Comprehens ive docum entation available User guide, integration guide, testing guide Test plan and characterization report 27 Velocity High-Speed Interfaces Proven In Silicon 2.5Gbps Extremely low jitter 3.125Gbps 6.25Gbps Superior jitter performance Translates into an extremely resilient design Will deliver extremely low bit error rates Extra design margin Cheaper package, connectors, PCBs 28

15 Flexible Velocity PHY Test and Demo Board All ARM Velocity PHYS are silicon proven Boards available for evaluation on a loan basis 29 Velocity High-Speed Interfaces Pervasive SoC IP Library platforms Standard cells Embedded memory I/O functionality DDR Serial PHYs High-speed interfaces Serial PHYs DDR Standard Cells I/O Cells 30

16 Flexible DDR Solution Phase Locked Loop (PLL) Master Delay Locked Loop (DLL) Slave DLL I/O Pads Slave DLL I/O Pads Off Chip Interface IO pads repeat 8 times Flexible implementation to optimize solution area, power, performance Switchable architecture allows DDRI, DDRII, GDDR3 Up to 1.8Gb/s(GDDR3) data throughput Backwards compatible with DDR (2.5V I/O drive) using lower drive strengths Contains dynamic calibrator for on-die termination and pullup/pull-down driver network for PVT variations 31 I/O Placement Flexibility Go around the c hip corner Match supply / decap pad frequency to actual needs. (varies widely with package type) Power group I/O group 32

17 DDR Solutions for 130nm and 90nm Standard/App Soft IP Hard IP Controller Analog I/Os DDR I SDRAM 2.5V Up To 400Mb/s ARM PL340 (also supports Mobile-DDR) 800Mbs DLL 533MHz PLL DDR1/2 DDR II 1.8V SDRAM/ RLDRAM Up To 800Mb/s ARM PL341 (Q2, 2006) 800Mbs DLL 533MHz PLL DDR1/2 GDDR III 1.8V SDRAM/ RLDRAM Up To 1.6Gb/s 3 rd Party 1800Mbs DLL 800MHz PLL GDDR3 33 Summary Physical IP is a key part of the ARM product portfolio Optimized physical IP enables new benefits: Unique power, performance and area solutions Faster time to market through use of IP that works together easily Manufacturing flexibility Best commercial terms for SoC production Leading foundry and EDA support Low risk solutions Silicon and system validated Extensive offering, capabilities and experience Single source for processors, high-speed interfaces, memory interfaces, specialty I/Os, analog, standard cells, standard I/Os, and memories R&D team, support, silicon, lab 34